超高速ADC时钟稳定与编码电路设计
|
摘要
模数转换器是模拟信号转换成数字信号的主要单元,而数字信号处理系统的广泛应用,使得模数转换器越来越得到重视,对模数转换器的要求也越来越高。而当模数转换器的速度和精度提高时,受时钟抖动影响的孔径时间不确定性会越来越严重地引起采样点偏移,导致采样保持电路的信噪比降低,极大地限制了整个ADC的性能提高。
本文针对8Bit 1.6GSPS时钟交织折叠内插式超高速ADC对时钟系统锁相环、比较器和误码校正等单元的性能分配和指标要求,从基本原理、电路设计以及版图设计等方面对低抖动的单频点锁相环、超高速比较器和误码校正技术进行了深入分析和研究。
主要研究了压控振荡器的锁定时间与锁相环系统参数之间的关系,通过锁相环的线性模型s域分析,推导得出其开闭环传输函数,进而确定锁相环中各模块的主要参数;基于0.35μm CMOS数模混合工艺,设计了鉴频鉴相器、电荷泵、压控振荡器、分频器、比较器和误码校正电路等单元电路;提出了一种抑制电荷共享的电荷泵电路结构,使电荷泵的充放电电流失配度明显降低;结合电流模单元和双转单电路,有效抑制了压控振荡器中电源噪声和衬底噪声的影响:鉴频鉴相器中采用动态D触发器和异常逻辑判断/控制回路,消除了传统鉴频鉴相器的“死区”现象。
对完整的时钟稳定电路仿真结果显示:在3.3V电源电压,25℃,TT工艺角条件下,锁相环系统的锁定时间约为2.2μs,相位锁定时控制电压的纹波很小,稳定在1.895V,VCO输出频率范围为35MHz~1.3GHz,输出需求频率为400MHz。电源电压为3.3V时,整个电路的功耗为32.68mW,时钟稳定电路的相位噪声为-126.85dBc/Hz@1MHz;比较器的比较上升时间为0.2ns,下降时间为0.25ns。此外,在设计指标要求的不同PVT(Process-Voltage-Temperature)条件下,各电路模块均能正常工作。
The Analog-to-Digital Converter (ADC) is the main unit between Analog signals and Digital signal. And the digital signal system widely used makes ADC has been more attention, the requirement of the ADC is also increasing in the development. But when the sampling rate and the resolution of ADCs become higher and higher, the effects of clock jitter aperture time uncertainty will cause the sampling offset more and more seriously, resulting in lower signal to noise ratio (SNR) of sample and hold (S/H) circuit, which greatly limits the overall ADC performance improvement.
This thesis starts at the study of a Phase-Locked Loop (PLL) applied to the clock system, Comparator and Error Correction of a 8Bit 1.6GSPS ultra high speed time-interleaved folding and interpolating ADC, and the deep analysis of the low jitter single output frequency PLL, High Speed Comparator and Error Correction are unfolded from basic principles, system level design, transistor circuits design and layouts design.
The relationship between VCO lock time and PLL system parameters is researched. According to PLL linear model by S domain analysis, deriving that the open loop transfer function, determine the PLL in the main parameters of each module. Some module unit circuits, including PFD, CP, VCO, Divider, Comparator and Error correction are designed based on 0.35μm CMOS mixed-signal process. A charge pump circuit of reducing charge sharing has been developed, the circuit decreased charging and discharging current mismatch. the VCO can inhibit the power noise and substrate noise by combination of current-mode unit and two-to-one circuit, and the PFD using dynamic D flip-flop and exception logic eliminate the PFD device“dead zone”phenomenon.
Moreover, the simulation results of the whole clock stability circuit show that the PLL lock time is about 2.2μs at the 3.3V supply voltage, 25℃and the TT process corner. when the PLL is locked in, the controlling voltage of VCO has little ripple, stable at 1.895V, The output frequency range of VCO is 35MHz~1.3GHz, and the linearity of VCO is good with the output frequency of 400MHz. The power of the whole circuit is 32.68mW at 3.3V power supply. In addition, the phase noise of the whole clock stability circuit is -126.85dBc/Hz@1MHz. The Comparator simulation results show that the rise time is 0.2ns, and the fall time is 0.25ns. Also, the PLL can operate well under different process corners.
本文针对8Bit 1.6GSPS时钟交织折叠内插式超高速ADC对时钟系统锁相环、比较器和误码校正等单元的性能分配和指标要求,从基本原理、电路设计以及版图设计等方面对低抖动的单频点锁相环、超高速比较器和误码校正技术进行了深入分析和研究。
主要研究了压控振荡器的锁定时间与锁相环系统参数之间的关系,通过锁相环的线性模型s域分析,推导得出其开闭环传输函数,进而确定锁相环中各模块的主要参数;基于0.35μm CMOS数模混合工艺,设计了鉴频鉴相器、电荷泵、压控振荡器、分频器、比较器和误码校正电路等单元电路;提出了一种抑制电荷共享的电荷泵电路结构,使电荷泵的充放电电流失配度明显降低;结合电流模单元和双转单电路,有效抑制了压控振荡器中电源噪声和衬底噪声的影响:鉴频鉴相器中采用动态D触发器和异常逻辑判断/控制回路,消除了传统鉴频鉴相器的“死区”现象。
对完整的时钟稳定电路仿真结果显示:在3.3V电源电压,25℃,TT工艺角条件下,锁相环系统的锁定时间约为2.2μs,相位锁定时控制电压的纹波很小,稳定在1.895V,VCO输出频率范围为35MHz~1.3GHz,输出需求频率为400MHz。电源电压为3.3V时,整个电路的功耗为32.68mW,时钟稳定电路的相位噪声为-126.85dBc/Hz@1MHz;比较器的比较上升时间为0.2ns,下降时间为0.25ns。此外,在设计指标要求的不同PVT(Process-Voltage-Temperature)条件下,各电路模块均能正常工作。
The Analog-to-Digital Converter (ADC) is the main unit between Analog signals and Digital signal. And the digital signal system widely used makes ADC has been more attention, the requirement of the ADC is also increasing in the development. But when the sampling rate and the resolution of ADCs become higher and higher, the effects of clock jitter aperture time uncertainty will cause the sampling offset more and more seriously, resulting in lower signal to noise ratio (SNR) of sample and hold (S/H) circuit, which greatly limits the overall ADC performance improvement.
This thesis starts at the study of a Phase-Locked Loop (PLL) applied to the clock system, Comparator and Error Correction of a 8Bit 1.6GSPS ultra high speed time-interleaved folding and interpolating ADC, and the deep analysis of the low jitter single output frequency PLL, High Speed Comparator and Error Correction are unfolded from basic principles, system level design, transistor circuits design and layouts design.
The relationship between VCO lock time and PLL system parameters is researched. According to PLL linear model by S domain analysis, deriving that the open loop transfer function, determine the PLL in the main parameters of each module. Some module unit circuits, including PFD, CP, VCO, Divider, Comparator and Error correction are designed based on 0.35μm CMOS mixed-signal process. A charge pump circuit of reducing charge sharing has been developed, the circuit decreased charging and discharging current mismatch. the VCO can inhibit the power noise and substrate noise by combination of current-mode unit and two-to-one circuit, and the PFD using dynamic D flip-flop and exception logic eliminate the PFD device“dead zone”phenomenon.
Moreover, the simulation results of the whole clock stability circuit show that the PLL lock time is about 2.2μs at the 3.3V supply voltage, 25℃and the TT process corner. when the PLL is locked in, the controlling voltage of VCO has little ripple, stable at 1.895V, The output frequency range of VCO is 35MHz~1.3GHz, and the linearity of VCO is good with the output frequency of 400MHz. The power of the whole circuit is 32.68mW at 3.3V power supply. In addition, the phase noise of the whole clock stability circuit is -126.85dBc/Hz@1MHz. The Comparator simulation results show that the rise time is 0.2ns, and the fall time is 0.25ns. Also, the PLL can operate well under different process corners.
引文
[1] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd Edition. Dordrecht, the Netherlands:Kluwer Academic Publishers,2003,97-98
[2] Derek Redmayne, Eric Trelewicz, Alison Smith. Understanding the Effect of Clock Jitter on High Speed ADCs. Design Note 1013, Linear Technology Corporation,2007
[3] M. Shinagawa, Y. Akazawa, T. Wakimoto. Jitter Analysis of High-Speed Sampling Systems. IEEE Journal of Solid-State Circuits,1990,Vol.25(2):220-224
[4] Prakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal Specification driven design of Phase locked loops. IEEE International Conference on VLSI Design, 2009 22nd, 569-578
[5] Zhiheng Cao, Y. Li, Shouli Yan. A 0.4ps-rms-Jitter 1–3GHz Ring Oscillator PLL using Phase Noise Preamplification. IEEE Journal of Solid-State Circuits,2008,Vol.43(9):2079-2089
[6] Sander L. J. Gierkink. Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL with Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump. IEEE Journal of Solid-State Circuits,2008,Vol.43(12):2967-2976
[7] Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, et al. A Fully Integrated 0.13μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. IEEE Journal of Solid-State Circuits,2007,Vol.42(5):967-982
[8] Richard Gu, Wai Lee. A 1V 6.25GHz PLL with 0.5ps rms Jitter in 0.13μm CMOS. Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology,2006,1688-1691
[9] Ting-sheng Chao, Yu-Lung Lo, Wei-bing Yang. Designing Ultra-Low Voltage PLL Using A Bulk-Driven Technique. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2009
[10] Li YongKe. The Design of Wide BW frequency synthesizer based on the DDS&PLL hybrid method. The Ninth International Conference on Electronic Measurement & Instruments. ICEMI’2009, 2-689-2-692
[11]陈莹梅,王志功,章丽.一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环.半导体学报,2008,29(1):88-92
[12]伍翠萍.低抖动时钟稳定电路研究与设计:[硕士学位论文].成都:电子科技大学,2008
[13]肖磊,刘玮,杨莲兴.用于1.25GHz Serdes的低时钟抖动的环振的设计.半导体学报,2008,29(3):490-496
[14]刘永旺,王志功,李伟. 2.5Gbps/ch两通道并行时钟数据恢复电路.半导体学报,2007,28(3):460-464
[15] Jri Lee. High-Speed Circuit Designs for Transmitters in Broadband Data Links. IEEE Journal of Solid-State Circuits,2006,Vol.41(5):1004-1015
[16] Woogeun Rhee. Design of High-Performance CMOS Charge Pump in Phase-Locked Loops. Proceedings of the 1999 IEEE ISCAS,1999,Vol.2:545-548
[17] Young-Shig Choi, Dae-Hyun Han. Gain-Boosting Charge Pump for Current Matching in Phase Locked Loop. IEEE Transactions on Circuits and Systems II,2006,Vol.53(10):1022-1025
[18] Rabaety J M, Chandrakasan A, Nikolic B. Digital integrated circuit.. Upper Saddle River, New York: Printice-Hall, 1999
[19] W. B. Wilson, Un-Ku Moon, K. R. Lakshmikumar, et al. A CMOS Self-Calibrating Frequency Synthesizer. IEEE Journal of Solid-State Circuits,2000,Vol.35(10):1437-1444
[20] David M. Colleran, C. Portmann, A. Hassibi, et al. Optimization of Phase-Locked Loop Circuits via Geometric Programming. Proceedings of the IEEE 2003 Custom Integrated Circuits Conference,2003,377-380
[21] Dean Banerjee. PLL Performance, Simulation and Design, Forth Edition. Texas, USA:National Semiconductor Corporation,2006,39-41
[22] Jae-Shin Lee, Min-Sun Keel. Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops. Electronics Letters,2000,Vol.36(23):1907-1908
[23] Bing J. Sheu, Chenming Hu. Switch-Induced Error Voltage on a Switched Capacitor. IEEE Journal of Solid-State Circuits,1984,Vol.19(4):519-525
[24]李桂华,王钊,孙仲林.一种高速低功耗低相位抖动CMOS锁相环.微电子学,2001,Vol.31(5):379-382
[25]刘永旺,王志功,李伟. 1.244GHz 0.25μm CMOS低功耗锁相环.半导体学报,2006.12,Vol.27(12):2190-2195
[26]王洪魁,袁小云,张瑞智.低噪声、低功耗CMOS电荷泵锁相环设计.固体电子学研究与发展,2004.2,Vol.24(1):81-85
[27]司龙,熊元新,蒋叶强.一种多倍频选择的高倍频锁相环频率合成器.微电子学,2005.8,Vol.35(4):424-427
[28]陈颖莹.高速并行A/D转换器:[硕士学位论文].北京:北方工业大学,2008
[29]张春晖,李永明,陈弘毅.一种采用新触发器的高速CMOS前置分频器.半导体学报,2001.6,Vol.22(6):788-791
[30] Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, et.al. A 4-bit 1.356Gsps ADC for DS-CDMA UWB System. IEEE,2006, vol.12(2):339-342
[31] Rober C. Taft, Chris A. Menkus, Maria Rosaria Tursi, et.al. A 1.8-V 1.6GSample/s 8-b Self-Calibrating Folding ADC With 7.26 ENOB at Nyquist Frequency. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2004.12, Vol.39(12):2107-2115
[32] Koen Uyttenhove, Michiel S. J. Steyaert. A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-μm CMOS. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2003.7, Vol.38(7):1115-1122
[33] Yong-lu Wang, Zhou-yun Wang, Shu-tao Zhou, et.al. A 250MSPS 8-Bit Analog-to-Digital Converter Based on 0.35μm BiCMOS Technology. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2006
[34] Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, et.al. A 1.35 GS/s, 10b, 175mW Time-interleaved AD Converter in 0.13μm CMOS. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2008, Vol.43(4):778-786
[35] Bram Nauta, Ardie G. W. Venes. A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Conwerter. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 1995, Vol.30(12):1302-1308
[36] Aida Varzaghani, Chih-Kong Ken Yang. A 6-GSamples/s Multi-Level Decision Feedback Equalizer Embedded in a 4-Bit Time-interleaved Pipeline A/D Converter. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2006.4, Vol.41(4):935-944
[37] QYSTIN MOLDSVOR, GEIR S. QSTREM. An 8-bit, 200 MSPS Folding and Interpolating ADC. Analog Integrated Circuits and Signal Processing, 1998, Vol.15:37-47
[38] Dongjin Lee, Jaewin Song, Jongha Shin, Sanghoon Hwang, et.al. Design of a 1.8V 8-bit 500MSPS Foling-Interpolation CMOS A/D Converter with a Fokder Averaging Technique. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2007, 356-359
[39] Tsung-Sum Lee, Li-Dyi Luo, Chin-Sheng Lin. Design Techniques for A CMOS Low-Power Low-Voltage Fully Differential Flash Analog-to-Digital Converter .The 47th IEEE International Midwest Symposium on Circuit and Systems. 2004, 375-360
[40]熊莉英.GSPS超高速ADC系统设计与仿真:[硕士学位论文].成都:电子科技大学,2006
[41]徐阳,闵昊.一种高速电流型CMOS数模转换器设计.半导体学报,2000.6,Vol.21(6):597-601
[42]何乐年,王忆.模拟集成电路设计与仿真.北京:科学出版社,2008,390-486
[43]陈诚,王照钢,任俊彦.200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器.半导体学报,2004,Vol.25(11):1391-1397
[44]赵晖.基于锁相环结构的900MHz CMOS频率综合器设计:[博士学位论文] .上海:复旦大学,2003
[45]李玉生.超高速并行采样模拟/数字转换的研究:[博士学位论文].合肥:中国科技大学,2007
[46]王骏峰,冯军,李义慧.11.6-GHz 0.18-μm CMOS锁相环电路.东南大学学报,2007.4,Vol.23(1):35-38
[2] Derek Redmayne, Eric Trelewicz, Alison Smith. Understanding the Effect of Clock Jitter on High Speed ADCs. Design Note 1013, Linear Technology Corporation,2007
[3] M. Shinagawa, Y. Akazawa, T. Wakimoto. Jitter Analysis of High-Speed Sampling Systems. IEEE Journal of Solid-State Circuits,1990,Vol.25(2):220-224
[4] Prakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal Specification driven design of Phase locked loops. IEEE International Conference on VLSI Design, 2009 22nd, 569-578
[5] Zhiheng Cao, Y. Li, Shouli Yan. A 0.4ps-rms-Jitter 1–3GHz Ring Oscillator PLL using Phase Noise Preamplification. IEEE Journal of Solid-State Circuits,2008,Vol.43(9):2079-2089
[6] Sander L. J. Gierkink. Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL with Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump. IEEE Journal of Solid-State Circuits,2008,Vol.43(12):2967-2976
[7] Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, et al. A Fully Integrated 0.13μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. IEEE Journal of Solid-State Circuits,2007,Vol.42(5):967-982
[8] Richard Gu, Wai Lee. A 1V 6.25GHz PLL with 0.5ps rms Jitter in 0.13μm CMOS. Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology,2006,1688-1691
[9] Ting-sheng Chao, Yu-Lung Lo, Wei-bing Yang. Designing Ultra-Low Voltage PLL Using A Bulk-Driven Technique. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2009
[10] Li YongKe. The Design of Wide BW frequency synthesizer based on the DDS&PLL hybrid method. The Ninth International Conference on Electronic Measurement & Instruments. ICEMI’2009, 2-689-2-692
[11]陈莹梅,王志功,章丽.一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环.半导体学报,2008,29(1):88-92
[12]伍翠萍.低抖动时钟稳定电路研究与设计:[硕士学位论文].成都:电子科技大学,2008
[13]肖磊,刘玮,杨莲兴.用于1.25GHz Serdes的低时钟抖动的环振的设计.半导体学报,2008,29(3):490-496
[14]刘永旺,王志功,李伟. 2.5Gbps/ch两通道并行时钟数据恢复电路.半导体学报,2007,28(3):460-464
[15] Jri Lee. High-Speed Circuit Designs for Transmitters in Broadband Data Links. IEEE Journal of Solid-State Circuits,2006,Vol.41(5):1004-1015
[16] Woogeun Rhee. Design of High-Performance CMOS Charge Pump in Phase-Locked Loops. Proceedings of the 1999 IEEE ISCAS,1999,Vol.2:545-548
[17] Young-Shig Choi, Dae-Hyun Han. Gain-Boosting Charge Pump for Current Matching in Phase Locked Loop. IEEE Transactions on Circuits and Systems II,2006,Vol.53(10):1022-1025
[18] Rabaety J M, Chandrakasan A, Nikolic B. Digital integrated circuit.. Upper Saddle River, New York: Printice-Hall, 1999
[19] W. B. Wilson, Un-Ku Moon, K. R. Lakshmikumar, et al. A CMOS Self-Calibrating Frequency Synthesizer. IEEE Journal of Solid-State Circuits,2000,Vol.35(10):1437-1444
[20] David M. Colleran, C. Portmann, A. Hassibi, et al. Optimization of Phase-Locked Loop Circuits via Geometric Programming. Proceedings of the IEEE 2003 Custom Integrated Circuits Conference,2003,377-380
[21] Dean Banerjee. PLL Performance, Simulation and Design, Forth Edition. Texas, USA:National Semiconductor Corporation,2006,39-41
[22] Jae-Shin Lee, Min-Sun Keel. Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops. Electronics Letters,2000,Vol.36(23):1907-1908
[23] Bing J. Sheu, Chenming Hu. Switch-Induced Error Voltage on a Switched Capacitor. IEEE Journal of Solid-State Circuits,1984,Vol.19(4):519-525
[24]李桂华,王钊,孙仲林.一种高速低功耗低相位抖动CMOS锁相环.微电子学,2001,Vol.31(5):379-382
[25]刘永旺,王志功,李伟. 1.244GHz 0.25μm CMOS低功耗锁相环.半导体学报,2006.12,Vol.27(12):2190-2195
[26]王洪魁,袁小云,张瑞智.低噪声、低功耗CMOS电荷泵锁相环设计.固体电子学研究与发展,2004.2,Vol.24(1):81-85
[27]司龙,熊元新,蒋叶强.一种多倍频选择的高倍频锁相环频率合成器.微电子学,2005.8,Vol.35(4):424-427
[28]陈颖莹.高速并行A/D转换器:[硕士学位论文].北京:北方工业大学,2008
[29]张春晖,李永明,陈弘毅.一种采用新触发器的高速CMOS前置分频器.半导体学报,2001.6,Vol.22(6):788-791
[30] Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, et.al. A 4-bit 1.356Gsps ADC for DS-CDMA UWB System. IEEE,2006, vol.12(2):339-342
[31] Rober C. Taft, Chris A. Menkus, Maria Rosaria Tursi, et.al. A 1.8-V 1.6GSample/s 8-b Self-Calibrating Folding ADC With 7.26 ENOB at Nyquist Frequency. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2004.12, Vol.39(12):2107-2115
[32] Koen Uyttenhove, Michiel S. J. Steyaert. A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-μm CMOS. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2003.7, Vol.38(7):1115-1122
[33] Yong-lu Wang, Zhou-yun Wang, Shu-tao Zhou, et.al. A 250MSPS 8-Bit Analog-to-Digital Converter Based on 0.35μm BiCMOS Technology. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2006
[34] Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, et.al. A 1.35 GS/s, 10b, 175mW Time-interleaved AD Converter in 0.13μm CMOS. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2008, Vol.43(4):778-786
[35] Bram Nauta, Ardie G. W. Venes. A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Conwerter. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 1995, Vol.30(12):1302-1308
[36] Aida Varzaghani, Chih-Kong Ken Yang. A 6-GSamples/s Multi-Level Decision Feedback Equalizer Embedded in a 4-Bit Time-interleaved Pipeline A/D Converter. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2006.4, Vol.41(4):935-944
[37] QYSTIN MOLDSVOR, GEIR S. QSTREM. An 8-bit, 200 MSPS Folding and Interpolating ADC. Analog Integrated Circuits and Signal Processing, 1998, Vol.15:37-47
[38] Dongjin Lee, Jaewin Song, Jongha Shin, Sanghoon Hwang, et.al. Design of a 1.8V 8-bit 500MSPS Foling-Interpolation CMOS A/D Converter with a Fokder Averaging Technique. IEEE JOURNAL OF SOLID-STATE CIUCUITS, 2007, 356-359
[39] Tsung-Sum Lee, Li-Dyi Luo, Chin-Sheng Lin. Design Techniques for A CMOS Low-Power Low-Voltage Fully Differential Flash Analog-to-Digital Converter .The 47th IEEE International Midwest Symposium on Circuit and Systems. 2004, 375-360
[40]熊莉英.GSPS超高速ADC系统设计与仿真:[硕士学位论文].成都:电子科技大学,2006
[41]徐阳,闵昊.一种高速电流型CMOS数模转换器设计.半导体学报,2000.6,Vol.21(6):597-601
[42]何乐年,王忆.模拟集成电路设计与仿真.北京:科学出版社,2008,390-486
[43]陈诚,王照钢,任俊彦.200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器.半导体学报,2004,Vol.25(11):1391-1397
[44]赵晖.基于锁相环结构的900MHz CMOS频率综合器设计:[博士学位论文] .上海:复旦大学,2003
[45]李玉生.超高速并行采样模拟/数字转换的研究:[博士学位论文].合肥:中国科技大学,2007
[46]王骏峰,冯军,李义慧.11.6-GHz 0.18-μm CMOS锁相环电路.东南大学学报,2007.4,Vol.23(1):35-38