系统芯片中媒体增强数字信号处理器核设计研究
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摘要
媒体系统芯片设计开发中的关键问题，就是如何最有效地利用硅片上可用的硬件资源，提供支持目标多媒体应用的单芯片高性加比解决方案。基于总线互连的由一个或多个指令集处理器核、一个或多个专用硬件IP核、一片或多片片上存储器构成的异质体系结构成为媒体系统芯片的合理选择。在国家863计划的支持下，我们开展了系统芯片中媒体增强的数字信号处理器核的设计研究，本文作为部分成果，着重探讨了处理器核指令集结构的媒体处理增强、处理器核微结构的设计和优化以及系统总线设计和媒体数据流调度的问题。
在系统芯片中媒体数字信号处理器核的设计中，在分析媒体处理应用算法特点的基础上，本文提出对MIPS-Ⅰ指令体系相兼容的基本指令集结构进行媒体增强扩展，通过支持SIMD亚字并行操作、媒体专用指令和运算结果特殊处理等增强单发射结构处理器的媒体处理性能，借鉴Intel MMX／SSE／SSE2媒体扩展指令集的思想生成初始指令功能集合，通过与常用媒体处理核心算法的互动进一步优化媒体指令集结构，创新性地对与MIPS-Ⅰ相兼容的基本指令体系实现了后向兼容媒体增强扩展，在硬件上通过构造可拆分的数据通道等实现了对媒体增强指令集的支持，以极小的硬件附加开销获得了媒体处理性能的显著提高。
在系统芯片中媒体数字信号处理器核的设计中，在具体分析CPU流水线竞争和处理器异常的基础上，本文提出并实现了一种基于有限状态机的流水线运行控制方案，并从提高钟频和降低CPI值两个方面优化处理器性能。为避免流水时钟频率受制于某些复杂运算指令较长的运算时间，又要达到单周期完成一条运算指令的吞吐量指标，本文提出对EX级进行可伸缩超流水扩展的思想，提出并实现了一种高性加比的切换控制方案。对于单发射结构的处理器，降低CPI值的根本途径在于通过各种软硬件技术减少流水线的停顿，本文构造了一个RAW相关环路模型用于分析流水线中寄存器操作数的RAW竞争现象，并提出了一种“动态”数据旁路优化策略，可以最大程度地减少复杂流水线中因数据的RAW竞争而导致的互锁停顿，理论分析和实测结果充分表明“动态”数据旁路机构可以有效地降低流水线因RAW互锁导致的平均CPI增量。
总线设计和媒体数据流的调度是实时媒体系统芯片设计中极其关键的问题，本文以VCD、HDTV解码系统芯片的设计为具体个例，探讨了MPEG-1／2视频解码软硬件实现中的数据流调度策略。在分析视频码流输入、解码处理和视频显示的时间参数后，提出以3帧组合为软件解码的调度粒度，以及基于启动期限和完成期限的两种解码调度策略，较好地均衡了处理器性能需求和数据缓存需求。提出了一种基于静态分时复用调度／动态固定优先级仲裁的混合二级总线仲裁策略，通过分割总线时间片静态调度媒体数据流DMA传输，使之与解码流程同步配合，有效地分配和使用总线带宽，降低了片上数据缓存等硬件开销。
How to utilize the available hardware resources on the silicon chip effectively is a key issue in high performance/cost media system-on-chip (SoC) development. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware IP cores and one or more on-chip memories usually provides a good solution. The research work introduced in this paper mainly concerns the processor core design for media SoC.
Media enhancement backward extension to MIPS-I compatible ISA is presented in this paper. Based on the analysis of inherent characteristics of media application algorithms, the basic MIPS-I compatible ISA is extended to support sub-word parallel SIMD operation, special result handling, and dedicated media instructions. The media enhancement extension to MIPS-I compatible ISA is physically realized in the processor core, and improves media processing performance effectively (2-4x) with negligible additional hardware cost (2.7%).
A Finite State Machine (FSM) based centralized control scheme is presented in this paper to supervise the CPU pipeline activity. And some effective techniques are discussed to lower the clock period and CPI (Cycles Per Instruction) of the pipeline. To eliminate the clock frequency limitation by some complex instructions' long executing time and achieve single-cycle throughput, a scalable super-pipelining extension technique together with a high performance/cost pipeline shift mechanism is presented in this paper. For single-issue processor architecture, the radical solution to CPI reduction is to decease pipeline stalls exploiting available software or hardware techniques. A RAW (Read After Write) dependency loop model is developed in this paper to analyze the RAW hazards of register operands in complex pipeline. Based on this model, a "dynamic" data forwarding policy is suggested to reduce the pipeline stalls caused by data RAW hazards. Theoretical analysis and practical experiments both show that the average CPI increment caused by data RAW hazards can be reduced effectively by the dynamic data forwarding strategy.
Bus design and media data stream scheduling are key issues in real-time media SoC development. Data scheduling policies for MPEG-1/2 video decoding is discussed in this paper according to software or hardware implementation case. Two 3-frames-grained scheduling policies are suggested to make good trade-off between processing demands and on-chip buffer demands in software decoding implementation. A static time division multiplexed scheduling / dynamic fixed priority arbitration based 2-level hybrid arbitration scheme, incorporated with synchronization control, is introduced in this paper to utilize the bus bandwidth effectively and lower on-chip buffer demands in media SoC.
在系统芯片中媒体数字信号处理器核的设计中，在分析媒体处理应用算法特点的基础上，本文提出对MIPS-Ⅰ指令体系相兼容的基本指令集结构进行媒体增强扩展，通过支持SIMD亚字并行操作、媒体专用指令和运算结果特殊处理等增强单发射结构处理器的媒体处理性能，借鉴Intel MMX／SSE／SSE2媒体扩展指令集的思想生成初始指令功能集合，通过与常用媒体处理核心算法的互动进一步优化媒体指令集结构，创新性地对与MIPS-Ⅰ相兼容的基本指令体系实现了后向兼容媒体增强扩展，在硬件上通过构造可拆分的数据通道等实现了对媒体增强指令集的支持，以极小的硬件附加开销获得了媒体处理性能的显著提高。
在系统芯片中媒体数字信号处理器核的设计中，在具体分析CPU流水线竞争和处理器异常的基础上，本文提出并实现了一种基于有限状态机的流水线运行控制方案，并从提高钟频和降低CPI值两个方面优化处理器性能。为避免流水时钟频率受制于某些复杂运算指令较长的运算时间，又要达到单周期完成一条运算指令的吞吐量指标，本文提出对EX级进行可伸缩超流水扩展的思想，提出并实现了一种高性加比的切换控制方案。对于单发射结构的处理器，降低CPI值的根本途径在于通过各种软硬件技术减少流水线的停顿，本文构造了一个RAW相关环路模型用于分析流水线中寄存器操作数的RAW竞争现象，并提出了一种“动态”数据旁路优化策略，可以最大程度地减少复杂流水线中因数据的RAW竞争而导致的互锁停顿，理论分析和实测结果充分表明“动态”数据旁路机构可以有效地降低流水线因RAW互锁导致的平均CPI增量。
总线设计和媒体数据流的调度是实时媒体系统芯片设计中极其关键的问题，本文以VCD、HDTV解码系统芯片的设计为具体个例，探讨了MPEG-1／2视频解码软硬件实现中的数据流调度策略。在分析视频码流输入、解码处理和视频显示的时间参数后，提出以3帧组合为软件解码的调度粒度，以及基于启动期限和完成期限的两种解码调度策略，较好地均衡了处理器性能需求和数据缓存需求。提出了一种基于静态分时复用调度／动态固定优先级仲裁的混合二级总线仲裁策略，通过分割总线时间片静态调度媒体数据流DMA传输，使之与解码流程同步配合，有效地分配和使用总线带宽，降低了片上数据缓存等硬件开销。
How to utilize the available hardware resources on the silicon chip effectively is a key issue in high performance/cost media system-on-chip (SoC) development. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware IP cores and one or more on-chip memories usually provides a good solution. The research work introduced in this paper mainly concerns the processor core design for media SoC.
Media enhancement backward extension to MIPS-I compatible ISA is presented in this paper. Based on the analysis of inherent characteristics of media application algorithms, the basic MIPS-I compatible ISA is extended to support sub-word parallel SIMD operation, special result handling, and dedicated media instructions. The media enhancement extension to MIPS-I compatible ISA is physically realized in the processor core, and improves media processing performance effectively (2-4x) with negligible additional hardware cost (2.7%).
A Finite State Machine (FSM) based centralized control scheme is presented in this paper to supervise the CPU pipeline activity. And some effective techniques are discussed to lower the clock period and CPI (Cycles Per Instruction) of the pipeline. To eliminate the clock frequency limitation by some complex instructions' long executing time and achieve single-cycle throughput, a scalable super-pipelining extension technique together with a high performance/cost pipeline shift mechanism is presented in this paper. For single-issue processor architecture, the radical solution to CPI reduction is to decease pipeline stalls exploiting available software or hardware techniques. A RAW (Read After Write) dependency loop model is developed in this paper to analyze the RAW hazards of register operands in complex pipeline. Based on this model, a "dynamic" data forwarding policy is suggested to reduce the pipeline stalls caused by data RAW hazards. Theoretical analysis and practical experiments both show that the average CPI increment caused by data RAW hazards can be reduced effectively by the dynamic data forwarding strategy.
Bus design and media data stream scheduling are key issues in real-time media SoC development. Data scheduling policies for MPEG-1/2 video decoding is discussed in this paper according to software or hardware implementation case. Two 3-frames-grained scheduling policies are suggested to make good trade-off between processing demands and on-chip buffer demands in software decoding implementation. A static time division multiplexed scheduling / dynamic fixed priority arbitration based 2-level hybrid arbitration scheme, incorporated with synchronization control, is introduced in this paper to utilize the bus bandwidth effectively and lower on-chip buffer demands in media SoC.
引文
[1] The Columbia Encyclopedia, 5th Edition, Columbia University Press, 1993.
[2] The MPEG Home Page: http://drogo.cselt.it/mpeg/index.htm.
[3] National Television System Committee: http://www.ntsc-tv.com/ntscindex-01.htm.
[4] Leonardo Chiariglione, "The MPEG-4 Standard," Journal of the China Institute of Communications, September 1998.
[5] Leonardo Chiariglione, "Impact of MPEG Standards on Multimedia Industry," Proceedings of the IEEE, March 1998.
[6] Leonardo Chiariglione, "MPEG and multimedia communications," International Symposium on Consumer Electronics, Beijing, November 1996.
[7] G.K. Wallace, "The JPEG Still Picture Compression Standard," Communications of the ACM, April 1991.
[8] MPEG-1 Standard Draft, "MPEG-1: Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbps," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1992.
[9] MPEG-4 Committee Draft N2995, "Overview of the MPEG-4 Standard," N2995, International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1998.
[10] MPEG-7 Committee Draft N3158, "Overview of the MPEG-7 Standard," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1999.
[11] Wayne Wolf et al., "A digital video library on the World Wide Web," Proceedings, ACM Multimedia '96, ACM Press, 1996.
[12] MPEG-21 Committee Draft N3162, "First ideas on defining a Multimedia Framework(version 0.2)," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, December 1999.
[13] V.M. Bove et al., "Multimedia based on object models: Some whys and hows," IBM Systems Journal, vol. 36, no. 3 and 4, 1996, pp. 337-348.
[14] V.M. Bove et al., "The Impact of New Multimedia Representations on Hardware and Software Systems," SPIE Photonics West, Multimedia Hardware Architectures '97, San Jose, CA, January 1997.
[15] MPEG-2 Standard Draft, "MPEG-2: Generic coding of moving pictures and associated audio information," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1994.
[16] C-Cube's ZiVA-3 Advanced DVD Decoder with Integrated Audio DSP: http://www.c-cube.com/products/ziva3.html
[17] Zhao Wu, Wayne Wolf, "Parallel Architectures for Programmable Video Signal Processing," Technical Report, Princeton University, 1998.
[18] R.B. Lee, "Subword Parallelism with MAX-2," IEEE Micro, vol. 16, no. 4, August 1996, pp. 51-59.
[19] R.B. Lee, "Accelerating Multimedia with Enhanced Microprocessors," IEEE Micro,
vol. 15, no. 2, April 1995, pp. 22-32.
[20] R.B. Lee, J. Huck, "64-bit and Multimedia Extensions for the PA-RISC 2.0 Architecture," Proceedings of Compcon '96, IEEE CS Press, 1996, pp. 152-160.
[21] A. Peleg, U. Weiser, "MMX Technology Extension to the Intel Architecture," IEEE Micro, vol. 16, no. 4, August 1996, pp. 42-50.
[22] M. Tremblay et al., "VIS Speeds New Media Processing," IEEE Micro vol. 16, no. 4, August 1996, pp. 10-20.
[23] D.A. Carlson et al., "Multimedia Extensions for a 550 MHz RISC Microprocessor," IEEE Journal of Solid-State Circuits, 1997.
[24] "MIPS Digital Media Extension," Instruction Set Architecture Specification, http://www.mips.com/MDMXspec.ps.
[25] M. Phillip et al., "AltiVec Technology: Accelerating Media Processing Across the Spectrum," Proceedings of Hot Chips 10, August 1998.
[26] Motorola's AltiVec Technology: http://www.motorola.com/SPS/PowerPC/AltiVec/
[27] S. Oberman et al., "AMD 3Dnow! Technology and the K6-2 Microprocessor," Proceedings of Hot Chips 10, August 1998.
[28] T.M. Conte et al., "Challenges to Combining General-Purpose and Multimedia Processors," IEEE Computer, December 1997, pp. 33-37.
[29] R.B. Lee, M. D. Smith, "Media Processing: A New Design Target," IEEE Micro, vol. 16, no. 4, August 1996, pp. 6-9.
[30] P. Ranganathan et al., "Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions," Proc. Of the 1999 International Symposium on Computer Architecture, pp. 124-135.
[31] J. A. Fisher et al., "Custom-Fit Processors: Letting Applications Define Architectures," Proceedings of the 29th International Symposium on Microarchitecture, December 1996, pp. 324-335.
[32] R. Gove, "The MVP: A Highly-Integrated Video Compression Chip," Proceedings of the 1994 Data Compression Conference, pp. 215-224, 1994.
[33] Texas Instruments C8x: http://www.ti.com/sc/docs/dsps/products/c8x/index.htm
[34] P. Faraboschi et al., "The Latest Word in Digital and Media Processing," IEEE Signal Processing Magazine, March 1998, pp. 59-85.
[35] S. Rathnam et al., "An Architectural Overview of the Programmable Multimedia Processor, TM-1," Proceedings of COMPCON '96, pp. 319-326.
[36] TriMedia processor: http://www.trimedia.philips.com/
[37] P. Foley, "The Mpact Media Processor Redefines the Multimedia PC," Proceedings of Compcon '96, 1996, pp. 311-318.
[38] S. Purcell, "Mpact2 media processor, balanced 2X performance," Proc. of the SPIE Photonics West '97, Multimedia Hardware Architecture, Feb. 1997, pp. 102-108.
[39] C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, August 1996, pp. 34-41.
[40] L. Nguyen et al., "Establish MSP as the standard for media processing," Proc. of Hot Chips 8: A Symposium on High-Performance Chips, August 1996.
[41] "Equator Introduces MAP1000A Media Accelerated Processor," Press Release, Equator Technologies, Inc., October 1999.
[42] Texas Instruments C6x: http://www.ti.com/sc/docs/dsps/products/c6x/index.htm
[43] K. Suzuki et al., "V830R/AV: Embedded Multimedia Superscalar RISC Processor," IEEE Micro, March 1998, pp36-47.
[44] NEC's V830R/AV: http://www.ic.nec.co.jp/micro/english/product/v800/v800.html
[45] A.K. Riemens et al., "TriMedia CPU64 Application Domain and Benchmark Suite," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 580-585.
[46] J.T.J. van Eijndhoven et al., "TriMedia CPU64 Architecture," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 586-592.
[47] E.J.D. Pol et al., "TriMedia CPU64 Application Development Environment," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 593-598.
[48] G.J. Hekstra et al., "TriMedia CPU64 Design Space Exploration," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp.599-606.
[49] ATI Technologies, Inc.: http://www.ati.com/
[50] S3, Inc.: http://www.s3.com/
[51] NVidia, Inc.: http://www.nvidia.com/
[52] W.H. Wolf, "Hardware-Software Co-Design of Embedded Systems," Proceeding of the IEEE, Vol.82, No.7, July 1994, pp.967-988.
[53] R.K. Gupta et al., "Hardware-Software Co-Synthesis for Digital Systems", IEEE Design & Test of Computers, Sept. 1993, pp.29-41.
[54] R. Ernst et al., "Hardware-Software Co-Synthesis for Micro Controllers", IEEE Design & Test of Computers, Dec. 1993, pp.64-75.
[55] Giovanni De Micheli et al., "Hardware/Software Co-Design", Proceedings of the IEEE, Vol.85, No.3, Mar. 1997, pp.349-365.
[56] Stephen Edwards et al. "Design of Embedded Systems: Formal Models, Validation, and Synthesis", Proceedings of the IEEE, Vol. 85, No.3, Mar. 1997, pp. 366-377.
[57] Asawaree Kalavade, E. A. Lee. "A Hardware-Software Co-Design Methodology for DSP Application", IEEE Design & Test of Computers, Sept. 1993, pp.16-28.
[58] Jim Turley, "CPU and DSP cores vie for ASIC designer's attention", Computer Design, Jan. 1997, pp.75-86.
[59] Barbara Tuck, "Integrating IP blocks to create a system-on a chip," Computer Design, Nov. 1997, pp.49-61.
[60] Ray Weiss, "32-bit cores drive systems-on-a-chip", Computer Design, Sept. 1996, pp.82-89.
[61] 袁寿财，朱长纯，“集成电路技术：过去与未来”，半导体杂志，1998．23(2)，pp．19-33．
[62] Bejoy G. Oommann，“系统级芯片的内置式测试新技术”，CEO of Genesys Testware
Inc., 1999．
[63] 段新东，“深亚微米集成电路设计方法学与EDA技术”，集成山路设计，1997年第4期，pp．74-84．
[64] Ralf Niemann et al., "An Algorithm for Hardware/Software Partitioning Using mixed Integer Linear Programming," Boston: Kluwer Academic Publishers, vol. 1997.
[65] S.A. Khayam et al., "A generic integer programming approach to hardware/software codesign," Proceedings of IEEE INMIC 2001, Dec. 2001, pp. 6-9.
[66] S. Bakshi et al., "Partitioning and pipelining for performance-constrained hardware/software systems," IEEE Trans. VLSI Systems, vol.7, no.4, Dec, 1999, pp. 419-432.
[67] 毛讯，“高速视频解码器的设计研究”，浙江大学博十学位论文，2001年．
[68] 杨伟建，“面向HDTV信源集成解码芯片的软硬件协同设计研究”，浙江大学博士学位论文，2001年．
[69] 高丰，“基于SOC的实时操作系统研究”，浙江大学博士学位论文，2002年．
[70] 姚庆栋，张朝阳，刘鹏等，“系统集成芯片综述”，计算机自动测量与控制，2000年第3期，pp．1-4．
[71] 刘鹏，“系统集成芯片中DSP和ASIP软硬件划分模型的研究和RISC软核的研究”，863计划超大规模集成电路SOC重大专项预启动项目技术报告，2001．
[72] 刘鹏，“SOC中32位数字信号处理器芯片开发和设计平台技术研究”，863计划超大规模集成电路设计专项技术报告，2003．
[73] J. H. Yang et al., "MetaCore: an application-specific programmable DSP development system". IEEE Trans. VLSI systems, Vol.8 Issue 2, April 2000, pp173-183.
[74] B. Holmer, A. M. Despain, "Viewing instruction set design as an optimization problem," Proc. 24~(th) Int. Conf. Microarchitecture, 1991.
[75] Shunichi Ishiwata et al., "A single-chip MPEG-2 codec based on customizable media embedded processor," IEEE J. Solid-state Circuits, Vol.38, No.3, March 2003, pp.530-539.
[76] Atsushi Mizuno et al., "Design methodology and system for a configurable media embedded processor extensible to VLIW architecture," Proc. ICCD 2002.
[77] R. Gonzalez, "Xtensa: A configurable and extensible processor," IEEE Micro, April 2000.
[78] M. Gschwind, "Instruction set selection for ASIP design," Proc. CODES-99, May 1999, pp.7-11.
[79] J. Fritts et al., "Understanding multimedia application characteristics for designing programmable media processors," Proc. SPIE Multimedia Hardware Architectures, Jan. 1999.
[80] Millind Mital et al., "MMX Technology Architecture Overview", Intel Technology Journal Q3'97, http://www.intel.com/technology/itj/q31997.htm.
[81] Michael Kagen et al., "MMX Micro Architecture of Pentium Processors with MMX Technology and Pentium Ⅱ Microprocessors", Intel Technology Journal Q3'97, http://www.intel.com/technology/itj/q31997.htm.
[82] Shreekant Thakkar et al., "The Internet Streaming SIMD Extensions", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[83] James Abel et al., "Application Tuning for Streaming SIMD Extensions", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[84] Jagannath Keshava et al., "Pentium Ⅲ Processor Implementation Tradeoffs", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[85] "Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[86] "Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[87] "Intel Architecture Software Developer's Manual, Volume 3: System Programming", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[88] "IA-64 Application Developer's Architecture Guide", Intel Corporation, 1999.
[89] C. Herring, "Microprocessors, micro-controllers and systems in the new millennium, " IEEE Micro, vol. 20, No. 6, Nov. 2000, pp. 45-51.
[90] G. Frantz, "Digital signal processor trends," IEEE Micro, vol. 20, no. 6, Nov. 2000, pp. 52-59.
[91] I. Kuroda et al., "Multimedia processors," Proceedings of the IEEE, vol. 86, no. 6, Jun. 1998, pp. 1203-1221.
[92] D.A. Patterson, J. L. Hennessy, "Computer Architecture: a quantitative approach," Morgan Kaufmann Publishers Inc., 1996.
[93] K. Yoshioka et al., "An architectural extension to the media core processor for HDTV applications", APCCAS 2002, Vol. 1, Oct. 2002, pp. 29-33.
[94] P. Pirsch et al., "VLSI implementations of image and video multimedia processing systems," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 7, Nov. 1998, pp. 878-891.
[95] P. Pirsch et al., "VLSI architectures for video compression-a survey," Proceedings of the IEEE, vol. 83, no. 2, Feb. 1995, pp. 220-246.
[96] S. Agarwala et al., "A 600 MHz VLIW DSP," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, Nov, 2002, pp. 1532-1544.
[97] S. Dutta et al., "A design study of a 0.25-μm video signal processor," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 4, Aug. 1998, pp. 501-519.
[98] 石教英等编，“计算机体系结构”，浙江大学出版社，1998年10月第1版．
[99] C.J. Wang et al., "Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods," Proc. of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 1993, pp. 102-105.
[100] C.J. Wang et al., "Implementing precise interruptions in pipelined RISC processors," IEEE Micro, vol. 13, no. 4, Aug. 1993, pp. 36-43.
[101] J.E. SMITH et al., "Implementing Precise Interrupts in Pinpelined Processors," IEEE Trans. on Computers, vol. 37, no. 5, May. 1988, pp. 562-573.
[102] M.H. Samadzadeh et al., "Hardware/software cost analysis of interrupt processing strategies," IEEE Micro, vol. 21, no. 3, Jun. 2001, pp. 69-76.
[103] M. Moudgill et al., "Precise interrupts," IEEE Micro, vol. 16, no. 1, Feb. 1996, pp. 58-67.
[104] Advanced Television System Committee, "Atsc Digital Television Standard", 1995.
[105] Yukio Fujii et al., "Implementation of MPEG Transport Demultiplexer with a RISC-Based Micro controller," IEEE Transactions on Consumer Electronics, Vol.42, No.3, Aug. 1996, pp.431-438.
[106] D.H. Han et al., "ASI/PSI, RSMS Data Stream and PCR/PTS Processing Algorithm for Korea sat Digital DBS System", IEEE Transactions on Consumer Electronics, Vol.44, No.2, May. 1998, pp.398-404.
[107] J.G. Kim et al., "Design and Implementation of an MPEG-2 Transport Stream Multiplexer for HDTV Satellite Broadcasting," IEEE Transactions on Consumer Electronics, Vol.44, No.3, Aug. 1998, pp.672-678.
[108] K.T. Yang et al., "The Conditional Access Flow Using Subscriber Smart Card with Korea sat DBS Receiver," IEEE Transactions on Consumer Electronics, Vol.43, No.3, Aug. 1997, pp.330-336.
[109] James C.McKinney et al.著，严静兰 乐陶译，“美国高级电视制式委员会(ATSC)数字音频压缩标准(AC-3)(ATSCA/52)”，电子部电视电声研究所．
[110] Lin Chia-Hsing et al., "On the Bus Arbitration for MPEG 2 Video Decoder," Proceedings of Technical Papers, International Symposium on VLSI Technology, Systems, and Applications, 1995, pp.201-205.
[111] Ling Nam et al., "A Bus-Monitoring Model for MPEG Video Decoder Design," IEEE Transactions on Consumer Electronics, Vol.43, No.3, 1997, pp.526-530.
[112] Li Jui-Hua et al., "Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder," IEEE Transactions on Circuits and Systems for Video Technology, Vol.9, 1999, pp.727-736.
[113] S. H. Khayat et al., "A Proposed Bus Arbitration Scheme for Multimedia Workstations," Proceedings of the International Conference on Multimedia Computing and Systems, 1994, pp.415-423.
[114] Yu Zhenghua et al., "Design and Implementation of HDTV Source Decoder," IEEE Transactions on Consumer Electronics, Vol.44, 1998, pp.384-387.
[115] Kim Hansoo et al., "Multi-thread VLIW processor architecture for HDTV decoding," Custom Integrated Circuits Conference, 2000, pp.559-562.
[116] Yarnauchi et al., "Single chip video processor for digital HDTV," IEEE Transactions on Consumer Electronics, Vol.47, No.3, 2001, pp.394-404.
[117] Mao Xun et al., "A High Efficient Simulation Environment for HDTV Video Decoder in VLSI Design," Proceedings of SPIE, Vol.4671,2002.
[118] Liu Peng et al., "Hardware/Software Codesign for HDTV Source Decoder on System Level," Proceedings of SPIE, Vol.4671, 2002, pp.679-686.
[119] Kane Gerry. Joe Heinrich, "MIPS RISC Architecture," Prentice Hall, 1992.
[120] 刘鹏，李东晓，姚庆栋，“面向HDTV解码应用的RISC核的软硬件协同设计，”中
国电子学会电路与系统学会第16届年会(ICCAS2001)，宁波，2001．
[121] 刘鹏，杨伟建，姚庆栋，“基于RISC核的系统集成芯片协同仿真，”中国电子学会电路与系统学会第16届年会(ICCAS2001)，宁波，2001．
[122] 高丰等，“一种基于HDTV信源集成解码芯片的RTOS的设计与实现，”电路与系统学报，2002年第3期，pp．45-49．
[123] 王蕙等，“MPEG2专用视频解码VLSI中的控制策略，”电路与系统学报，2002年第1期，pp．79-82．
[2] The MPEG Home Page: http://drogo.cselt.it/mpeg/index.htm.
[3] National Television System Committee: http://www.ntsc-tv.com/ntscindex-01.htm.
[4] Leonardo Chiariglione, "The MPEG-4 Standard," Journal of the China Institute of Communications, September 1998.
[5] Leonardo Chiariglione, "Impact of MPEG Standards on Multimedia Industry," Proceedings of the IEEE, March 1998.
[6] Leonardo Chiariglione, "MPEG and multimedia communications," International Symposium on Consumer Electronics, Beijing, November 1996.
[7] G.K. Wallace, "The JPEG Still Picture Compression Standard," Communications of the ACM, April 1991.
[8] MPEG-1 Standard Draft, "MPEG-1: Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbps," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1992.
[9] MPEG-4 Committee Draft N2995, "Overview of the MPEG-4 Standard," N2995, International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1998.
[10] MPEG-7 Committee Draft N3158, "Overview of the MPEG-7 Standard," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1999.
[11] Wayne Wolf et al., "A digital video library on the World Wide Web," Proceedings, ACM Multimedia '96, ACM Press, 1996.
[12] MPEG-21 Committee Draft N3162, "First ideas on defining a Multimedia Framework(version 0.2)," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, December 1999.
[13] V.M. Bove et al., "Multimedia based on object models: Some whys and hows," IBM Systems Journal, vol. 36, no. 3 and 4, 1996, pp. 337-348.
[14] V.M. Bove et al., "The Impact of New Multimedia Representations on Hardware and Software Systems," SPIE Photonics West, Multimedia Hardware Architectures '97, San Jose, CA, January 1997.
[15] MPEG-2 Standard Draft, "MPEG-2: Generic coding of moving pictures and associated audio information," International Organization for Standardization ISO/IEC JTC1/SC29/WG11N, 1994.
[16] C-Cube's ZiVA-3 Advanced DVD Decoder with Integrated Audio DSP: http://www.c-cube.com/products/ziva3.html
[17] Zhao Wu, Wayne Wolf, "Parallel Architectures for Programmable Video Signal Processing," Technical Report, Princeton University, 1998.
[18] R.B. Lee, "Subword Parallelism with MAX-2," IEEE Micro, vol. 16, no. 4, August 1996, pp. 51-59.
[19] R.B. Lee, "Accelerating Multimedia with Enhanced Microprocessors," IEEE Micro,
vol. 15, no. 2, April 1995, pp. 22-32.
[20] R.B. Lee, J. Huck, "64-bit and Multimedia Extensions for the PA-RISC 2.0 Architecture," Proceedings of Compcon '96, IEEE CS Press, 1996, pp. 152-160.
[21] A. Peleg, U. Weiser, "MMX Technology Extension to the Intel Architecture," IEEE Micro, vol. 16, no. 4, August 1996, pp. 42-50.
[22] M. Tremblay et al., "VIS Speeds New Media Processing," IEEE Micro vol. 16, no. 4, August 1996, pp. 10-20.
[23] D.A. Carlson et al., "Multimedia Extensions for a 550 MHz RISC Microprocessor," IEEE Journal of Solid-State Circuits, 1997.
[24] "MIPS Digital Media Extension," Instruction Set Architecture Specification, http://www.mips.com/MDMXspec.ps.
[25] M. Phillip et al., "AltiVec Technology: Accelerating Media Processing Across the Spectrum," Proceedings of Hot Chips 10, August 1998.
[26] Motorola's AltiVec Technology: http://www.motorola.com/SPS/PowerPC/AltiVec/
[27] S. Oberman et al., "AMD 3Dnow! Technology and the K6-2 Microprocessor," Proceedings of Hot Chips 10, August 1998.
[28] T.M. Conte et al., "Challenges to Combining General-Purpose and Multimedia Processors," IEEE Computer, December 1997, pp. 33-37.
[29] R.B. Lee, M. D. Smith, "Media Processing: A New Design Target," IEEE Micro, vol. 16, no. 4, August 1996, pp. 6-9.
[30] P. Ranganathan et al., "Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions," Proc. Of the 1999 International Symposium on Computer Architecture, pp. 124-135.
[31] J. A. Fisher et al., "Custom-Fit Processors: Letting Applications Define Architectures," Proceedings of the 29th International Symposium on Microarchitecture, December 1996, pp. 324-335.
[32] R. Gove, "The MVP: A Highly-Integrated Video Compression Chip," Proceedings of the 1994 Data Compression Conference, pp. 215-224, 1994.
[33] Texas Instruments C8x: http://www.ti.com/sc/docs/dsps/products/c8x/index.htm
[34] P. Faraboschi et al., "The Latest Word in Digital and Media Processing," IEEE Signal Processing Magazine, March 1998, pp. 59-85.
[35] S. Rathnam et al., "An Architectural Overview of the Programmable Multimedia Processor, TM-1," Proceedings of COMPCON '96, pp. 319-326.
[36] TriMedia processor: http://www.trimedia.philips.com/
[37] P. Foley, "The Mpact Media Processor Redefines the Multimedia PC," Proceedings of Compcon '96, 1996, pp. 311-318.
[38] S. Purcell, "Mpact2 media processor, balanced 2X performance," Proc. of the SPIE Photonics West '97, Multimedia Hardware Architecture, Feb. 1997, pp. 102-108.
[39] C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, August 1996, pp. 34-41.
[40] L. Nguyen et al., "Establish MSP as the standard for media processing," Proc. of Hot Chips 8: A Symposium on High-Performance Chips, August 1996.
[41] "Equator Introduces MAP1000A Media Accelerated Processor," Press Release, Equator Technologies, Inc., October 1999.
[42] Texas Instruments C6x: http://www.ti.com/sc/docs/dsps/products/c6x/index.htm
[43] K. Suzuki et al., "V830R/AV: Embedded Multimedia Superscalar RISC Processor," IEEE Micro, March 1998, pp36-47.
[44] NEC's V830R/AV: http://www.ic.nec.co.jp/micro/english/product/v800/v800.html
[45] A.K. Riemens et al., "TriMedia CPU64 Application Domain and Benchmark Suite," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 580-585.
[46] J.T.J. van Eijndhoven et al., "TriMedia CPU64 Architecture," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 586-592.
[47] E.J.D. Pol et al., "TriMedia CPU64 Application Development Environment," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp. 593-598.
[48] G.J. Hekstra et al., "TriMedia CPU64 Design Space Exploration," Proceedings of the 1999 International Conference on Computer Design, Austin, TX, October 1999, pp.599-606.
[49] ATI Technologies, Inc.: http://www.ati.com/
[50] S3, Inc.: http://www.s3.com/
[51] NVidia, Inc.: http://www.nvidia.com/
[52] W.H. Wolf, "Hardware-Software Co-Design of Embedded Systems," Proceeding of the IEEE, Vol.82, No.7, July 1994, pp.967-988.
[53] R.K. Gupta et al., "Hardware-Software Co-Synthesis for Digital Systems", IEEE Design & Test of Computers, Sept. 1993, pp.29-41.
[54] R. Ernst et al., "Hardware-Software Co-Synthesis for Micro Controllers", IEEE Design & Test of Computers, Dec. 1993, pp.64-75.
[55] Giovanni De Micheli et al., "Hardware/Software Co-Design", Proceedings of the IEEE, Vol.85, No.3, Mar. 1997, pp.349-365.
[56] Stephen Edwards et al. "Design of Embedded Systems: Formal Models, Validation, and Synthesis", Proceedings of the IEEE, Vol. 85, No.3, Mar. 1997, pp. 366-377.
[57] Asawaree Kalavade, E. A. Lee. "A Hardware-Software Co-Design Methodology for DSP Application", IEEE Design & Test of Computers, Sept. 1993, pp.16-28.
[58] Jim Turley, "CPU and DSP cores vie for ASIC designer's attention", Computer Design, Jan. 1997, pp.75-86.
[59] Barbara Tuck, "Integrating IP blocks to create a system-on a chip," Computer Design, Nov. 1997, pp.49-61.
[60] Ray Weiss, "32-bit cores drive systems-on-a-chip", Computer Design, Sept. 1996, pp.82-89.
[61] 袁寿财，朱长纯，“集成电路技术：过去与未来”，半导体杂志，1998．23(2)，pp．19-33．
[62] Bejoy G. Oommann，“系统级芯片的内置式测试新技术”，CEO of Genesys Testware
Inc., 1999．
[63] 段新东，“深亚微米集成电路设计方法学与EDA技术”，集成山路设计，1997年第4期，pp．74-84．
[64] Ralf Niemann et al., "An Algorithm for Hardware/Software Partitioning Using mixed Integer Linear Programming," Boston: Kluwer Academic Publishers, vol. 1997.
[65] S.A. Khayam et al., "A generic integer programming approach to hardware/software codesign," Proceedings of IEEE INMIC 2001, Dec. 2001, pp. 6-9.
[66] S. Bakshi et al., "Partitioning and pipelining for performance-constrained hardware/software systems," IEEE Trans. VLSI Systems, vol.7, no.4, Dec, 1999, pp. 419-432.
[67] 毛讯，“高速视频解码器的设计研究”，浙江大学博十学位论文，2001年．
[68] 杨伟建，“面向HDTV信源集成解码芯片的软硬件协同设计研究”，浙江大学博士学位论文，2001年．
[69] 高丰，“基于SOC的实时操作系统研究”，浙江大学博士学位论文，2002年．
[70] 姚庆栋，张朝阳，刘鹏等，“系统集成芯片综述”，计算机自动测量与控制，2000年第3期，pp．1-4．
[71] 刘鹏，“系统集成芯片中DSP和ASIP软硬件划分模型的研究和RISC软核的研究”，863计划超大规模集成电路SOC重大专项预启动项目技术报告，2001．
[72] 刘鹏，“SOC中32位数字信号处理器芯片开发和设计平台技术研究”，863计划超大规模集成电路设计专项技术报告，2003．
[73] J. H. Yang et al., "MetaCore: an application-specific programmable DSP development system". IEEE Trans. VLSI systems, Vol.8 Issue 2, April 2000, pp173-183.
[74] B. Holmer, A. M. Despain, "Viewing instruction set design as an optimization problem," Proc. 24~(th) Int. Conf. Microarchitecture, 1991.
[75] Shunichi Ishiwata et al., "A single-chip MPEG-2 codec based on customizable media embedded processor," IEEE J. Solid-state Circuits, Vol.38, No.3, March 2003, pp.530-539.
[76] Atsushi Mizuno et al., "Design methodology and system for a configurable media embedded processor extensible to VLIW architecture," Proc. ICCD 2002.
[77] R. Gonzalez, "Xtensa: A configurable and extensible processor," IEEE Micro, April 2000.
[78] M. Gschwind, "Instruction set selection for ASIP design," Proc. CODES-99, May 1999, pp.7-11.
[79] J. Fritts et al., "Understanding multimedia application characteristics for designing programmable media processors," Proc. SPIE Multimedia Hardware Architectures, Jan. 1999.
[80] Millind Mital et al., "MMX Technology Architecture Overview", Intel Technology Journal Q3'97, http://www.intel.com/technology/itj/q31997.htm.
[81] Michael Kagen et al., "MMX Micro Architecture of Pentium Processors with MMX Technology and Pentium Ⅱ Microprocessors", Intel Technology Journal Q3'97, http://www.intel.com/technology/itj/q31997.htm.
[82] Shreekant Thakkar et al., "The Internet Streaming SIMD Extensions", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[83] James Abel et al., "Application Tuning for Streaming SIMD Extensions", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[84] Jagannath Keshava et al., "Pentium Ⅲ Processor Implementation Tradeoffs", Intel Technology Journal Q2'99, http://www.intel.com/technology/itj/q21999.htm.
[85] "Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[86] "Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[87] "Intel Architecture Software Developer's Manual, Volume 3: System Programming", Intel Corporation, 1999, http://www.intel.com/design/pentiumii/manuals.
[88] "IA-64 Application Developer's Architecture Guide", Intel Corporation, 1999.
[89] C. Herring, "Microprocessors, micro-controllers and systems in the new millennium, " IEEE Micro, vol. 20, No. 6, Nov. 2000, pp. 45-51.
[90] G. Frantz, "Digital signal processor trends," IEEE Micro, vol. 20, no. 6, Nov. 2000, pp. 52-59.
[91] I. Kuroda et al., "Multimedia processors," Proceedings of the IEEE, vol. 86, no. 6, Jun. 1998, pp. 1203-1221.
[92] D.A. Patterson, J. L. Hennessy, "Computer Architecture: a quantitative approach," Morgan Kaufmann Publishers Inc., 1996.
[93] K. Yoshioka et al., "An architectural extension to the media core processor for HDTV applications", APCCAS 2002, Vol. 1, Oct. 2002, pp. 29-33.
[94] P. Pirsch et al., "VLSI implementations of image and video multimedia processing systems," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 7, Nov. 1998, pp. 878-891.
[95] P. Pirsch et al., "VLSI architectures for video compression-a survey," Proceedings of the IEEE, vol. 83, no. 2, Feb. 1995, pp. 220-246.
[96] S. Agarwala et al., "A 600 MHz VLIW DSP," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, Nov, 2002, pp. 1532-1544.
[97] S. Dutta et al., "A design study of a 0.25-μm video signal processor," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 4, Aug. 1998, pp. 501-519.
[98] 石教英等编，“计算机体系结构”，浙江大学出版社，1998年10月第1版．
[99] C.J. Wang et al., "Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods," Proc. of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 1993, pp. 102-105.
[100] C.J. Wang et al., "Implementing precise interruptions in pipelined RISC processors," IEEE Micro, vol. 13, no. 4, Aug. 1993, pp. 36-43.
[101] J.E. SMITH et al., "Implementing Precise Interrupts in Pinpelined Processors," IEEE Trans. on Computers, vol. 37, no. 5, May. 1988, pp. 562-573.
[102] M.H. Samadzadeh et al., "Hardware/software cost analysis of interrupt processing strategies," IEEE Micro, vol. 21, no. 3, Jun. 2001, pp. 69-76.
[103] M. Moudgill et al., "Precise interrupts," IEEE Micro, vol. 16, no. 1, Feb. 1996, pp. 58-67.
[104] Advanced Television System Committee, "Atsc Digital Television Standard", 1995.
[105] Yukio Fujii et al., "Implementation of MPEG Transport Demultiplexer with a RISC-Based Micro controller," IEEE Transactions on Consumer Electronics, Vol.42, No.3, Aug. 1996, pp.431-438.
[106] D.H. Han et al., "ASI/PSI, RSMS Data Stream and PCR/PTS Processing Algorithm for Korea sat Digital DBS System", IEEE Transactions on Consumer Electronics, Vol.44, No.2, May. 1998, pp.398-404.
[107] J.G. Kim et al., "Design and Implementation of an MPEG-2 Transport Stream Multiplexer for HDTV Satellite Broadcasting," IEEE Transactions on Consumer Electronics, Vol.44, No.3, Aug. 1998, pp.672-678.
[108] K.T. Yang et al., "The Conditional Access Flow Using Subscriber Smart Card with Korea sat DBS Receiver," IEEE Transactions on Consumer Electronics, Vol.43, No.3, Aug. 1997, pp.330-336.
[109] James C.McKinney et al.著，严静兰 乐陶译，“美国高级电视制式委员会(ATSC)数字音频压缩标准(AC-3)(ATSCA/52)”，电子部电视电声研究所．
[110] Lin Chia-Hsing et al., "On the Bus Arbitration for MPEG 2 Video Decoder," Proceedings of Technical Papers, International Symposium on VLSI Technology, Systems, and Applications, 1995, pp.201-205.
[111] Ling Nam et al., "A Bus-Monitoring Model for MPEG Video Decoder Design," IEEE Transactions on Consumer Electronics, Vol.43, No.3, 1997, pp.526-530.
[112] Li Jui-Hua et al., "Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder," IEEE Transactions on Circuits and Systems for Video Technology, Vol.9, 1999, pp.727-736.
[113] S. H. Khayat et al., "A Proposed Bus Arbitration Scheme for Multimedia Workstations," Proceedings of the International Conference on Multimedia Computing and Systems, 1994, pp.415-423.
[114] Yu Zhenghua et al., "Design and Implementation of HDTV Source Decoder," IEEE Transactions on Consumer Electronics, Vol.44, 1998, pp.384-387.
[115] Kim Hansoo et al., "Multi-thread VLIW processor architecture for HDTV decoding," Custom Integrated Circuits Conference, 2000, pp.559-562.
[116] Yarnauchi et al., "Single chip video processor for digital HDTV," IEEE Transactions on Consumer Electronics, Vol.47, No.3, 2001, pp.394-404.
[117] Mao Xun et al., "A High Efficient Simulation Environment for HDTV Video Decoder in VLSI Design," Proceedings of SPIE, Vol.4671,2002.
[118] Liu Peng et al., "Hardware/Software Codesign for HDTV Source Decoder on System Level," Proceedings of SPIE, Vol.4671, 2002, pp.679-686.
[119] Kane Gerry. Joe Heinrich, "MIPS RISC Architecture," Prentice Hall, 1992.
[120] 刘鹏，李东晓，姚庆栋，“面向HDTV解码应用的RISC核的软硬件协同设计，”中
国电子学会电路与系统学会第16届年会(ICCAS2001)，宁波，2001．
[121] 刘鹏，杨伟建，姚庆栋，“基于RISC核的系统集成芯片协同仿真，”中国电子学会电路与系统学会第16届年会(ICCAS2001)，宁波，2001．
[122] 高丰等，“一种基于HDTV信源集成解码芯片的RTOS的设计与实现，”电路与系统学报，2002年第3期，pp．45-49．
[123] 王蕙等，“MPEG2专用视频解码VLSI中的控制策略，”电路与系统学报，2002年第1期，pp．79-82．