高频锁相环中单粒子效应失效机理与加固技术研究
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摘要
作为时钟产生和同步的电路,锁相环(PLL)被广泛应用于各种航天器的电子和通信系统中。空间辐射环境中的PLL在单粒子作用下,将产生频率或相位偏差,甚至导致振荡中止,造成通信或功能中断,从而对航天器造成灾难性的后果。随着工艺步入纳米阶段,PLL的工作频率不断提高,对单粒子的敏感性日益增加。目前,抗辐射PLL的研究存在着失效机理尚不透彻、缺乏准确的电路级模型、缺乏有效的加固方法等突出问题。因此,对高频PLL的单粒子失效机理与加固技术展开深入研究具有重要的理论和应用价值。
本文研究了单粒子效应对集成电路的各种影响、单粒子的一般加固技术与模拟方法,针对深亚微米体硅工艺下高频锁相环中的单粒子效应,深入研究了其失效机理与加固技术,研究内容包括单粒子闩锁的机理、压控振荡器的SET响应、以及鉴频鉴相器的加固技术。论文的研究成果包括以下几点:
(1)本文总结了单粒子效应对集成电路的各种影响,从体系结构级、部件级、电路级和版图级多个层级介绍了不同类型电路结构的加固设计技术,深入研究了器件级、电路级和混合级的模拟方法及各自的适用范围。分析表明,器件级的模拟及三维混合模拟能够较精确的表征单粒子效应对电路及系统产生的影响,是研究集成电路SEE响应行之有效的方法。
(2)本文系统地研究了影响SEL敏感性的关键因素。基于校准的器件模型,使用器件级模拟的方法,本文研究了粒子入射位置、粒子入射角度、温度、阱/衬底接触的位置、NMOS与PMOS间距及槽深六种因素与SEL敏感性之间的关系,得到了抗SEL加固设计的具体设计参数。本文的研究结果能够为体硅工艺下的抗SEL加固设计提供有效的指导。
(3)本文深入研究了高频PLL电路中VCO的SET响应,基于校准的器件模型,本文对一个三级VCO在不同偏置条件、入射粒子能量以及不同温度下的SET进行了混合模拟。研究结果表明,当器件工作在截止区时,入射粒子引起压控振荡器输出时钟的最大相位差最小;压控振荡器的输出时钟错误脉冲数随着入射粒子的LET增加而线性增加;随着器件工作温度的升高,轰击粒子引起压控振荡器输出时钟的最大相位差也是增加的。然后,本文从理论上对上述结果进行了解释和分析。找出了SET敏感性随偏置条件、入射粒子能量和工作温度的变化关系,并从理论上对上述结果进行了解释。
(4)本文提出了一种新型的SEU/SET设计加固的PFD。采用SPICE电路模拟方法分析验证了传统D触发器型PFD的SEE敏感性,在此基础上提出了一种新型的SEU/SET设计加固PFD。锁相环的整体模拟结果表明,本文提出的PFD与传统的PFD电学性能基本一致,鉴频鉴相精度可达0.8弧度,锁定时间保持一致。对D触发器型PFD和设计加固的PFD进行了遍历轰击模拟,结果显示本文提出的抗辐照PFD加固效果非常明显,敏感节点的数目可以降低约80%。加入该抗SEU/SET PFD结构的抗辐照PLL设计已经流片,重离子试验的准备工作正在进行,将进一步验证其抗SEE的能力。
As the clock generation and synchronization circuitry, phase-locked loop (PLL) is widely used in a variety of spacecraft electronics and communications systems. PLL under the action of a single particle in Space radiation environment , will result in frequency or phase deviation, or even result in suspension of oscillation, which may lead to the interruption of communication or function, thereby spacecraft catastrophic consequences follows. As the VLSI technology step into the nanometer stage, PLL operating frequency continues to increase, and become more and more sensitive to single event effect. At present, anti-radiation study of the PLL still has some problems, such as, the failure mechanism is not yet thorough, the lack of accurate spice-level model, and the lack of effective harden methods and so on. Therefore, research on single particle failure mechanism and radiation hardened techniques of high-frequency PLL has important theoretical and applied value.
This paper studies various effects of the single event effect on integrated circuits , some general hardened techniques and simulation methods of single event effect. In allusion to the single event effect under the high-frequency phase-locked loop with the deep sub-micron bulk silicon technology. Lucubrate its failure mechanism and hardened techniques, the study content include single event latchup mechanism and SET response to voltage-controlled oscillators, as well as the PFD device hardened techniques. Research papers include the following:
1. Summarizes the single event effect on integrated circuits in various effects, and also introduce hardened design technologies in different types of circuits in the architecture level, component level, circuit-level and layout-level, and so on. And then conduct a in-depth study of the device level, circuit level and mixed-level simulation methods and their respective scope of application.
2. Based on abroad understanding of single event latchup effect , study the sensitive nodes of the CMOS inverter when latch occurred, research on the relationship between temperature, well / substrate contact position, NMOS and PMOS drain distance, particle hit angle, the process parameters– SIT depth and LET threshold when latchup occurred, which can provide some guidance to the anti-latchup design.
3. Based on process calibration, single event transient in Voltage-Controlled Oscillators of high frequency Phase-Locked Loop in a 0.18μm bulk process is studied by TCAD Mixed-mode simulation. The impact of voltage, LET and temperature on SET is studied. Our simulation results demonstrate that the max phase difference caused by particle on VCO is weakly when NMOS works in cut-off region. The pulse error number caused by particle on VCO increases linearly as LET increases, and when the device temperature increases, the max phase difference on VCO also generally increases.
4. In this paper, a novel SEU/SET hardened PFD is proposed in order to reduce the SEE sensitivity of traditional D flip-flop type PFD. SPICE simulation shows that this structure has very high accuracy. Compared with traditional PFD, the electrical properties of PLL with radiation harden PFD has not changed. Compared the number of hit nodes which can cause PLL jitter both for D flip-flop type PFD and radiation harden PFD, the number of sensitive nodes is reduced by 80%,proving that the anti-radiation of the proposed PFD is quite effective.
本文研究了单粒子效应对集成电路的各种影响、单粒子的一般加固技术与模拟方法,针对深亚微米体硅工艺下高频锁相环中的单粒子效应,深入研究了其失效机理与加固技术,研究内容包括单粒子闩锁的机理、压控振荡器的SET响应、以及鉴频鉴相器的加固技术。论文的研究成果包括以下几点:
(1)本文总结了单粒子效应对集成电路的各种影响,从体系结构级、部件级、电路级和版图级多个层级介绍了不同类型电路结构的加固设计技术,深入研究了器件级、电路级和混合级的模拟方法及各自的适用范围。分析表明,器件级的模拟及三维混合模拟能够较精确的表征单粒子效应对电路及系统产生的影响,是研究集成电路SEE响应行之有效的方法。
(2)本文系统地研究了影响SEL敏感性的关键因素。基于校准的器件模型,使用器件级模拟的方法,本文研究了粒子入射位置、粒子入射角度、温度、阱/衬底接触的位置、NMOS与PMOS间距及槽深六种因素与SEL敏感性之间的关系,得到了抗SEL加固设计的具体设计参数。本文的研究结果能够为体硅工艺下的抗SEL加固设计提供有效的指导。
(3)本文深入研究了高频PLL电路中VCO的SET响应,基于校准的器件模型,本文对一个三级VCO在不同偏置条件、入射粒子能量以及不同温度下的SET进行了混合模拟。研究结果表明,当器件工作在截止区时,入射粒子引起压控振荡器输出时钟的最大相位差最小;压控振荡器的输出时钟错误脉冲数随着入射粒子的LET增加而线性增加;随着器件工作温度的升高,轰击粒子引起压控振荡器输出时钟的最大相位差也是增加的。然后,本文从理论上对上述结果进行了解释和分析。找出了SET敏感性随偏置条件、入射粒子能量和工作温度的变化关系,并从理论上对上述结果进行了解释。
(4)本文提出了一种新型的SEU/SET设计加固的PFD。采用SPICE电路模拟方法分析验证了传统D触发器型PFD的SEE敏感性,在此基础上提出了一种新型的SEU/SET设计加固PFD。锁相环的整体模拟结果表明,本文提出的PFD与传统的PFD电学性能基本一致,鉴频鉴相精度可达0.8弧度,锁定时间保持一致。对D触发器型PFD和设计加固的PFD进行了遍历轰击模拟,结果显示本文提出的抗辐照PFD加固效果非常明显,敏感节点的数目可以降低约80%。加入该抗SEU/SET PFD结构的抗辐照PLL设计已经流片,重离子试验的准备工作正在进行,将进一步验证其抗SEE的能力。
As the clock generation and synchronization circuitry, phase-locked loop (PLL) is widely used in a variety of spacecraft electronics and communications systems. PLL under the action of a single particle in Space radiation environment , will result in frequency or phase deviation, or even result in suspension of oscillation, which may lead to the interruption of communication or function, thereby spacecraft catastrophic consequences follows. As the VLSI technology step into the nanometer stage, PLL operating frequency continues to increase, and become more and more sensitive to single event effect. At present, anti-radiation study of the PLL still has some problems, such as, the failure mechanism is not yet thorough, the lack of accurate spice-level model, and the lack of effective harden methods and so on. Therefore, research on single particle failure mechanism and radiation hardened techniques of high-frequency PLL has important theoretical and applied value.
This paper studies various effects of the single event effect on integrated circuits , some general hardened techniques and simulation methods of single event effect. In allusion to the single event effect under the high-frequency phase-locked loop with the deep sub-micron bulk silicon technology. Lucubrate its failure mechanism and hardened techniques, the study content include single event latchup mechanism and SET response to voltage-controlled oscillators, as well as the PFD device hardened techniques. Research papers include the following:
1. Summarizes the single event effect on integrated circuits in various effects, and also introduce hardened design technologies in different types of circuits in the architecture level, component level, circuit-level and layout-level, and so on. And then conduct a in-depth study of the device level, circuit level and mixed-level simulation methods and their respective scope of application.
2. Based on abroad understanding of single event latchup effect , study the sensitive nodes of the CMOS inverter when latch occurred, research on the relationship between temperature, well / substrate contact position, NMOS and PMOS drain distance, particle hit angle, the process parameters– SIT depth and LET threshold when latchup occurred, which can provide some guidance to the anti-latchup design.
3. Based on process calibration, single event transient in Voltage-Controlled Oscillators of high frequency Phase-Locked Loop in a 0.18μm bulk process is studied by TCAD Mixed-mode simulation. The impact of voltage, LET and temperature on SET is studied. Our simulation results demonstrate that the max phase difference caused by particle on VCO is weakly when NMOS works in cut-off region. The pulse error number caused by particle on VCO increases linearly as LET increases, and when the device temperature increases, the max phase difference on VCO also generally increases.
4. In this paper, a novel SEU/SET hardened PFD is proposed in order to reduce the SEE sensitivity of traditional D flip-flop type PFD. SPICE simulation shows that this structure has very high accuracy. Compared with traditional PFD, the electrical properties of PLL with radiation harden PFD has not changed. Compared the number of hit nodes which can cause PLL jitter both for D flip-flop type PFD and radiation harden PFD, the number of sensitive nodes is reduced by 80%,proving that the anti-radiation of the proposed PFD is quite effective.
引文
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