基于FPGA的低功耗维特比译码器研究与实现
摘要
卷积码是一种在数字移动通信系统中应用极为广泛的信道纠错编码。维特比(Viterbi)译码算法是最常用的卷积码译码算法。而维特比译码器的计算量、存储容量及功耗,会随其关键参数约束长度K的值成指数增长。这个特点使得大K值的维特比译码器在数字通信系统中,特别是移动设备、环保设备、手持设备等场合的应用受到很大限制。功耗问题己成为制约维特比译码器进一步发展与应用的瓶颈。本文对维特比译码器进行低功耗研究,并设计实现了基于现场可编程门阵列(FPGA)的大约束长度(K=9)维特比译码器,对降低数字通信系统电能消耗、改善散热性能、延长手持设备的待机时间具有重要积极的实用意义。
本文采取自上而下(Top-Down)的设计方法。首先对维特比算法及其低功耗设计技术进行简要分析和总结,再根据维特比译码算法流程进行功能模块划分,并从实际应用的角度出发,根据大约数长度维特比译码器的结构特点,对各功能子模块进行低功耗优化设计,最后将其集成为维特比译码器系统。本文使用Verilog硬件描述语言进行电路设计,选用Altera公司全铜互连130nm工艺Cyclone系列FPGA,在QuartusII开发平台完成整个系统的性能验证及功耗分析,并与相关文献及Altera提供的维特比译码器MegaCore作对比分析。对比功耗分析结果表明,本设计可在保证译码器正常应用功能和纠错性能的前提下,使FPGA总功耗得以大幅度降低。
Convolution code is a widely used channel FEC in digital mobile communication system. Viterbi algorithm is a common way for the Convolution code decoding process. Meanwhile, the power and resources consumption is increased significantly with the rise of key parameter: constrain value k. This feather result the conditionality use of Viterbi algorithm which based on large constrain value, especially as mobile phone and some other equipment that need batteries. Power consumption has been the main problem of the Viterbi decoder. This paper studied the technology of low-power consumption in Viterbi decoder, and has finished this design whit FPGA. It is useful to decrease the power consumption for the digital communication system.
This paper uses a top-down design flow. First analyzes the Viterbi design flow, separate the whole decoder into several functional module. Then design the functional module into low-power consumption module according to the actually demand. At last put them together to integrate the whole Viterbi decoder system. Verilog HDL is used in this design as hardware describe language. This paper choice a 130 nm Cyclone to perform the whole design separately and QuartusII platform is used to synthesis and verification. Meanwhile some papers and a Viterbi decoder MegaCore as a reference are applied to do a power comparison. The result shows that power consumption of current design can decrease greatly while offering a necessary performance and speed.
本文采取自上而下(Top-Down)的设计方法。首先对维特比算法及其低功耗设计技术进行简要分析和总结,再根据维特比译码算法流程进行功能模块划分,并从实际应用的角度出发,根据大约数长度维特比译码器的结构特点,对各功能子模块进行低功耗优化设计,最后将其集成为维特比译码器系统。本文使用Verilog硬件描述语言进行电路设计,选用Altera公司全铜互连130nm工艺Cyclone系列FPGA,在QuartusII开发平台完成整个系统的性能验证及功耗分析,并与相关文献及Altera提供的维特比译码器MegaCore作对比分析。对比功耗分析结果表明,本设计可在保证译码器正常应用功能和纠错性能的前提下,使FPGA总功耗得以大幅度降低。
Convolution code is a widely used channel FEC in digital mobile communication system. Viterbi algorithm is a common way for the Convolution code decoding process. Meanwhile, the power and resources consumption is increased significantly with the rise of key parameter: constrain value k. This feather result the conditionality use of Viterbi algorithm which based on large constrain value, especially as mobile phone and some other equipment that need batteries. Power consumption has been the main problem of the Viterbi decoder. This paper studied the technology of low-power consumption in Viterbi decoder, and has finished this design whit FPGA. It is useful to decrease the power consumption for the digital communication system.
This paper uses a top-down design flow. First analyzes the Viterbi design flow, separate the whole decoder into several functional module. Then design the functional module into low-power consumption module according to the actually demand. At last put them together to integrate the whole Viterbi decoder system. Verilog HDL is used in this design as hardware describe language. This paper choice a 130 nm Cyclone to perform the whole design separately and QuartusII platform is used to synthesis and verification. Meanwhile some papers and a Viterbi decoder MegaCore as a reference are applied to do a power comparison. The result shows that power consumption of current design can decrease greatly while offering a necessary performance and speed.
引文
[1] C.E.Shannon. A mathematical theory of communication. B.S.T.J., 1948, 27: 22～46
[2] I.Kang, A.N.Willson. Low-power Viterbi decoder for CDMA mobile terminals. IEEE Journal of Solid-State Circuits, 1998, 33(3): 473～482
[3] S.B.Wicker. Error Control Systems for Digital Communication and Storage. First Edition. NJ: Prentice-Hall, 1995.226～259
[4] A.J.Viterbi. Error bounds for convolutional codes and asymptotically optimum decoding algorithm. IEEE Trans on Information Theory, 1967, 13(2): 260～269
[5] A. Omura. On the Viterbi algorithm. IEEE Trans on Information Theory, 1969, 15: 13～20
[6] J.G.D. Forney. the Viterbi Algorithm. Proceedings of the IEEE, 1973, 61(3): 268～278
[7] K.Seki, S.Kubota, M.Mizoguchi. Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications. Electronics-Letters, 1994, 30(8): 637～639
[8] Sudhakar.R, Mukhtar.A, Zhenzhong Gu. Low-complexity error selective Viterbi decoder. Electronics Letters, 2000,36(2): 147～148
[9] Anderson.J, Mohan.S. Sequential Coding Algorithms: A Survey and Cost Analysis. IEEE Trans on Communications,1984,32(2): 169～176
[10] Man Guo, Ahmad M.O. FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder. IEEE Trans on Circuits and Systems, 2005,52(2): 350~365
[11] Fei Sun, Zhang T. Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder. IEEE Trans on Circuits and System, 2007,54(5): 1060～1068
[12] Ming-Bo Lin. New Path History Management Circuits for Viterbi Decoders. IEEE Trans on Communications, 2000, 48(10): 1605～1608
[13] El-Dib D.A., Elmasry M.I.. Modified Register-exchange Viterbi Decoder ForLow-power Wireless Communications. IEEE Trans on Circuits and Systems, 2004,51(2): 371～378
[14] Xun Liu, Marios C. Design of High-Through Put Low-Power IS95 Viterbi Decoder. Design Automation, 2002, 39(1): 263～268.
[15]李劲,吕岩.Viterbi译码器设置门限的低功耗设计方法.仪器仪表用户, 2004, 1: 71～72
[16]高丹,朱明华,刘海涛.基于预计算的Viterbi译码器ACS单元低功耗设计.微电子学,2007,37 (4): 557～560
[17]游余新,王进祥,来逢昌等.高速低功耗Viterbi译码器的设计与实现.计算机研究与发展,2003,40(2): 360～365
[18]姜淼,徐俊,李刚等.Viterbi译码器路径度量模块的低功耗设计.齐齐哈尔大学学报,2007, 23(6): 25～26
[19]鄂炜,苏广川.Viterbi译码中的路径度量存储管理.无线电工程,2003,33(4): 30～32
[20]王春光,陈新.大约束度维特比译码器中路径存储单元的设计.现代电子技术, 2007,13: 51～54
[21]郭正伟,赵勇. Viterbi Decoder ACS单元中路径度量值存储空间的优化.现代电子技术,2007,17: 71～73
[22]王汝波,康锡章.路径度量存储器及其接口的设计.数采与监测, 2006, 22(9): 10~13
[23]王丽,王金刚.利用有限资源实现高速Viterbi解码.电子测量技术,2003,2: 39~40
[24]段华蓉.幸存路径存储和输出单元的低功耗设计.计算机技术与发展, 2007,16(12): 142～145
[25]付永庆,孙晓岩,李福昌.实现维特比译码器幸存路径存储及译码输出的一种新方法.应用科技,2003,30(3): 25～26
[26]乔锋,陈进.维特比译码算法Soft Core IP的低功耗设计.通信技术,2003, 141(9): 22～24
[27]余莉. Viterbi译码器ACS模块的设计.中国科技信息,2005,13: 9~10
[28]阳任平,陈金树. Viterbi译码器ACS单元的一种新设计.电视技术, 2006, 8: 26~28
[29]韩雁,石教英.维特比译码器VLSI设计中幸存路径存储管理的新方法.电子学报,1996,24(2): 124～127
[30]王栋良,秦建存. Viterbi译码的FPGA免回溯实现.信号与信息处理, 2007, 37 (4): 27~28
[31]陈亦灏,李成诗,李小进等.一种高速Viterbi译码器幸存路径管理模块的改进结构.微电子学与计算机,2007,24(8): 99~105
[32]蔡志龙,冯文江,杨洋.一种基于FPGA的Viterbi译码器优化算法.现代电子技术,2008,17: 105~107
[33]张红,陈新,张国成.维特比译码器中幸存路径存储器的一种新的实现方法.应用科技,2007,34(3): 19~22
[34]刘国芳,程乃平.一种维特比改进算法的研究.遥测遥控, 2006, 27 (1): 30~32
[35]罗义军,李劲,章东平.一种Viterbi译码的改进算法.电路与系统学报, 2003, 8(6): 122~124
[36]赵旦峰,刘会红.卷积码Viterbi译码算法的FPGA实现.现代电子技术,2004, 1: 41~43
[37]张权,李劲. Viterbi译码器的低功耗设计.长江大学学报(自科版), 2005, 2(10): 356~358
[38]秦东,肖斌,李志勇等. Viterbi译码器的优化设计.微电子学, 2000, 30 (3): 168~171
[39]金文学,刘秉坤,陈岚.低功耗软判决维特比译码器的设计.计算机工程,2007,33(9): 243~245
[40]罗义军.通信中Viterbi算法和均衡器的优化设计及低功耗考虑:[博士学位论文]。杭州:浙江大学,2003.
[41] Tobias Gemmeke, Michael Gnasen. ImPlementation of Sclable Power and Area Efficient High-ThoughtPut Viterbi Decoders. IEEE J.Solid-State Circuits, 2002,37(7): 941～948
[2] I.Kang, A.N.Willson. Low-power Viterbi decoder for CDMA mobile terminals. IEEE Journal of Solid-State Circuits, 1998, 33(3): 473～482
[3] S.B.Wicker. Error Control Systems for Digital Communication and Storage. First Edition. NJ: Prentice-Hall, 1995.226～259
[4] A.J.Viterbi. Error bounds for convolutional codes and asymptotically optimum decoding algorithm. IEEE Trans on Information Theory, 1967, 13(2): 260～269
[5] A. Omura. On the Viterbi algorithm. IEEE Trans on Information Theory, 1969, 15: 13～20
[6] J.G.D. Forney. the Viterbi Algorithm. Proceedings of the IEEE, 1973, 61(3): 268～278
[7] K.Seki, S.Kubota, M.Mizoguchi. Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications. Electronics-Letters, 1994, 30(8): 637～639
[8] Sudhakar.R, Mukhtar.A, Zhenzhong Gu. Low-complexity error selective Viterbi decoder. Electronics Letters, 2000,36(2): 147～148
[9] Anderson.J, Mohan.S. Sequential Coding Algorithms: A Survey and Cost Analysis. IEEE Trans on Communications,1984,32(2): 169～176
[10] Man Guo, Ahmad M.O. FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder. IEEE Trans on Circuits and Systems, 2005,52(2): 350~365
[11] Fei Sun, Zhang T. Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder. IEEE Trans on Circuits and System, 2007,54(5): 1060～1068
[12] Ming-Bo Lin. New Path History Management Circuits for Viterbi Decoders. IEEE Trans on Communications, 2000, 48(10): 1605～1608
[13] El-Dib D.A., Elmasry M.I.. Modified Register-exchange Viterbi Decoder ForLow-power Wireless Communications. IEEE Trans on Circuits and Systems, 2004,51(2): 371～378
[14] Xun Liu, Marios C. Design of High-Through Put Low-Power IS95 Viterbi Decoder. Design Automation, 2002, 39(1): 263～268.
[15]李劲,吕岩.Viterbi译码器设置门限的低功耗设计方法.仪器仪表用户, 2004, 1: 71～72
[16]高丹,朱明华,刘海涛.基于预计算的Viterbi译码器ACS单元低功耗设计.微电子学,2007,37 (4): 557～560
[17]游余新,王进祥,来逢昌等.高速低功耗Viterbi译码器的设计与实现.计算机研究与发展,2003,40(2): 360～365
[18]姜淼,徐俊,李刚等.Viterbi译码器路径度量模块的低功耗设计.齐齐哈尔大学学报,2007, 23(6): 25～26
[19]鄂炜,苏广川.Viterbi译码中的路径度量存储管理.无线电工程,2003,33(4): 30～32
[20]王春光,陈新.大约束度维特比译码器中路径存储单元的设计.现代电子技术, 2007,13: 51～54
[21]郭正伟,赵勇. Viterbi Decoder ACS单元中路径度量值存储空间的优化.现代电子技术,2007,17: 71～73
[22]王汝波,康锡章.路径度量存储器及其接口的设计.数采与监测, 2006, 22(9): 10~13
[23]王丽,王金刚.利用有限资源实现高速Viterbi解码.电子测量技术,2003,2: 39~40
[24]段华蓉.幸存路径存储和输出单元的低功耗设计.计算机技术与发展, 2007,16(12): 142～145
[25]付永庆,孙晓岩,李福昌.实现维特比译码器幸存路径存储及译码输出的一种新方法.应用科技,2003,30(3): 25～26
[26]乔锋,陈进.维特比译码算法Soft Core IP的低功耗设计.通信技术,2003, 141(9): 22～24
[27]余莉. Viterbi译码器ACS模块的设计.中国科技信息,2005,13: 9~10
[28]阳任平,陈金树. Viterbi译码器ACS单元的一种新设计.电视技术, 2006, 8: 26~28
[29]韩雁,石教英.维特比译码器VLSI设计中幸存路径存储管理的新方法.电子学报,1996,24(2): 124～127
[30]王栋良,秦建存. Viterbi译码的FPGA免回溯实现.信号与信息处理, 2007, 37 (4): 27~28
[31]陈亦灏,李成诗,李小进等.一种高速Viterbi译码器幸存路径管理模块的改进结构.微电子学与计算机,2007,24(8): 99~105
[32]蔡志龙,冯文江,杨洋.一种基于FPGA的Viterbi译码器优化算法.现代电子技术,2008,17: 105~107
[33]张红,陈新,张国成.维特比译码器中幸存路径存储器的一种新的实现方法.应用科技,2007,34(3): 19~22
[34]刘国芳,程乃平.一种维特比改进算法的研究.遥测遥控, 2006, 27 (1): 30~32
[35]罗义军,李劲,章东平.一种Viterbi译码的改进算法.电路与系统学报, 2003, 8(6): 122~124
[36]赵旦峰,刘会红.卷积码Viterbi译码算法的FPGA实现.现代电子技术,2004, 1: 41~43
[37]张权,李劲. Viterbi译码器的低功耗设计.长江大学学报(自科版), 2005, 2(10): 356~358
[38]秦东,肖斌,李志勇等. Viterbi译码器的优化设计.微电子学, 2000, 30 (3): 168~171
[39]金文学,刘秉坤,陈岚.低功耗软判决维特比译码器的设计.计算机工程,2007,33(9): 243~245
[40]罗义军.通信中Viterbi算法和均衡器的优化设计及低功耗考虑:[博士学位论文]。杭州:浙江大学,2003.
[41] Tobias Gemmeke, Michael Gnasen. ImPlementation of Sclable Power and Area Efficient High-ThoughtPut Viterbi Decoders. IEEE J.Solid-State Circuits, 2002,37(7): 941～948