基于FPGA的高速数字化接收与处理技术
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摘要
在被动探测和电子侦测系统中,对接收信号的带宽、数据传输的速率要求越来越高。
就目前而言,由于AD器件的飞速发展,12位分辨力200MS/s、12位分辨400MS/s等各种高速AD已经大量应用于电子信息系统中,接收信号的带宽已可轻易扩展到200MHz。市场上还有8位分辨率,1.5GS/s及更高采样率的AD器件。数据的传输方面一般多用USB、PCI和FPDP协议传输,USB总线在2.0协议时流水数据传输速率可达20MB/s;PCI总线可实现33/66MHz,32/64位的组合设计,其流水数据传输速率可达70MB/s~80MB/s;现在的FPDP口(前端专用并行数据端口),数据传输速率能达到400MB/s。
本论文课题研究设计的信号处理板采用12位、200Msps的AD9430对瞬时带宽大于100MHz的信号进行高速采样,获得400MByte/s的数据率,经高效实时数字化信号检测处理后,利用Virtex-ⅡPro XC2VP7的内部存储器和FX12Miniboard板载的64MB DDR SDRAM进行数据缓存,通过千兆以太网和光纤进行高速数据传输。
本论文课题研究的目的主要是解决宽带信号数字化后产生的高速数据流与低速的计算机读写速度之间的矛盾,实现高速A/D转换器产生的峰值400MB/s数据流通过光纤和千兆以太网(MAC)进行传输。本论文课题主要研究内容包括:高速高精度AD模块的设计、高速实时数字化信号检测技术的应用、数据的高速大容量缓存、光纤以及千兆以太网的数据传输等。
经实测,采用光纤传输模式能实现的100MHz带宽信号的最大连续采样缓存脉宽为80μs,采用以太网传输模式能实现的最大连续采样缓存脉宽为400μs。
In the system of the Radar passive detecting and electronic reconnaissance,the demand of the bandwidth of the data receiving and the speed of the data transmitting is becoming higher and higher.
Nowadays,as the fast development of the ADC,there are many ADCs have applied in the system of electronic and information such as the ADCs of those with 12 differentiating bits and 200 million sampling per second and those with 12 differentiating bits and 400 million sampling per second.And the bandwidth of the data receiving can extend to 200MHz easily.From the market,it is easily to get the ADCs with 8 differentiating bits and 1.5 gigabit sampling per second,even get the higher ones.With respect to the data transmitting,it is common to use USB,PCI,and FPDP protocol,and the pipelining speed of the USB bus can achieve the max speed of 50 million bytes per second on protocol 2.0,the pipelining speed of the PCI bus can achieve the speed from 132MBps to 528MBps by setting the frequency of 33 million or 66 million and bits width of 32 bits or 64 bits.Now,the FPDP protocol's speed is up to 400 MBps.
The signal-processing board in my design samples the signal whose instantaneous bandwidth more than 100 MHz with high speed by using the AD9430 which has 12 differentiating bits and 200 million sampling per second,so it gets the data rate of the 400 MBps.After digitalization signal detecting with high efficiency and real time,the board buffers the data separately by using the memory inner the Virtex-ⅡPro XC2VP7 and the DDR SDRAM with the capability of 64 million bytes on the board,so the board has the ability of transmitting the data by selecting the fibre or the Ethernet.
The main of my design is to solve the inconsistency between the high speed of the data receiving from the digitalization of the wide band signal and the slow speed of the computer's reading or writing,and is to transmit the data whose peak speed is 400Mbytes/s from the high speed ADC by fibre and gigabit Ethernet.So my design mainly conclude the design of the ADC module with high speed and high precision and application of the signal detecting and the data buffering and data transmitting by fibre and gigabit Ethernet and so on.
By measuring in the real environment,the largest width of the pulse to buffer by fibre transmitting is 80 milliseconds,and the largest width of the pulse to buffer by gigabit Ethemet is 400 milliseconds.
就目前而言,由于AD器件的飞速发展,12位分辨力200MS/s、12位分辨400MS/s等各种高速AD已经大量应用于电子信息系统中,接收信号的带宽已可轻易扩展到200MHz。市场上还有8位分辨率,1.5GS/s及更高采样率的AD器件。数据的传输方面一般多用USB、PCI和FPDP协议传输,USB总线在2.0协议时流水数据传输速率可达20MB/s;PCI总线可实现33/66MHz,32/64位的组合设计,其流水数据传输速率可达70MB/s~80MB/s;现在的FPDP口(前端专用并行数据端口),数据传输速率能达到400MB/s。
本论文课题研究设计的信号处理板采用12位、200Msps的AD9430对瞬时带宽大于100MHz的信号进行高速采样,获得400MByte/s的数据率,经高效实时数字化信号检测处理后,利用Virtex-ⅡPro XC2VP7的内部存储器和FX12Miniboard板载的64MB DDR SDRAM进行数据缓存,通过千兆以太网和光纤进行高速数据传输。
本论文课题研究的目的主要是解决宽带信号数字化后产生的高速数据流与低速的计算机读写速度之间的矛盾,实现高速A/D转换器产生的峰值400MB/s数据流通过光纤和千兆以太网(MAC)进行传输。本论文课题主要研究内容包括:高速高精度AD模块的设计、高速实时数字化信号检测技术的应用、数据的高速大容量缓存、光纤以及千兆以太网的数据传输等。
经实测,采用光纤传输模式能实现的100MHz带宽信号的最大连续采样缓存脉宽为80μs,采用以太网传输模式能实现的最大连续采样缓存脉宽为400μs。
In the system of the Radar passive detecting and electronic reconnaissance,the demand of the bandwidth of the data receiving and the speed of the data transmitting is becoming higher and higher.
Nowadays,as the fast development of the ADC,there are many ADCs have applied in the system of electronic and information such as the ADCs of those with 12 differentiating bits and 200 million sampling per second and those with 12 differentiating bits and 400 million sampling per second.And the bandwidth of the data receiving can extend to 200MHz easily.From the market,it is easily to get the ADCs with 8 differentiating bits and 1.5 gigabit sampling per second,even get the higher ones.With respect to the data transmitting,it is common to use USB,PCI,and FPDP protocol,and the pipelining speed of the USB bus can achieve the max speed of 50 million bytes per second on protocol 2.0,the pipelining speed of the PCI bus can achieve the speed from 132MBps to 528MBps by setting the frequency of 33 million or 66 million and bits width of 32 bits or 64 bits.Now,the FPDP protocol's speed is up to 400 MBps.
The signal-processing board in my design samples the signal whose instantaneous bandwidth more than 100 MHz with high speed by using the AD9430 which has 12 differentiating bits and 200 million sampling per second,so it gets the data rate of the 400 MBps.After digitalization signal detecting with high efficiency and real time,the board buffers the data separately by using the memory inner the Virtex-ⅡPro XC2VP7 and the DDR SDRAM with the capability of 64 million bytes on the board,so the board has the ability of transmitting the data by selecting the fibre or the Ethernet.
The main of my design is to solve the inconsistency between the high speed of the data receiving from the digitalization of the wide band signal and the slow speed of the computer's reading or writing,and is to transmit the data whose peak speed is 400Mbytes/s from the high speed ADC by fibre and gigabit Ethernet.So my design mainly conclude the design of the ADC module with high speed and high precision and application of the signal detecting and the data buffering and data transmitting by fibre and gigabit Ethernet and so on.
By measuring in the real environment,the largest width of the pulse to buffer by fibre transmitting is 80 milliseconds,and the largest width of the pulse to buffer by gigabit Ethemet is 400 milliseconds.
引文
[1]杨小牛,陆安南,金飚 译.宽带数字接收机[M].北京:北京电子工业出版社,2002,5.
[2]马海潮.超高速数据采集技术发展现状[J].测试技术学报,2003,17(4):287-290
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[4]夏玉立,雷宏,黄瑶.用Xilinx FPGA实现DDR SDRAM控制器[J].2007,23(9-2):209-211
[5]李贵山,陈金鹏.PCI局部总线及其应用[M].西安:西安电子科技大学出版社,2003,2.
[6]陶春荣,金艳艳.基于USB接口的数据采集系统[J].雷达与对抗,2004,(1):55-57
[7]杨小牛,楼才义,许建良.软件无线电原理与应用[M].北京:电子工业出版社,2005,7:11-14
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[10]孙航.Xilinx可编程逻辑器件的高级应用与设计技巧[M].北京:电子工业出版社,2004,8.
[11]LT1764 Series[M].Linear Technology Corporation,Inc.2000.
[12]薛小刚,葛毅敏.Xilinx ISE 9.X FPGA/CPLD设计指南[M].北京:人民邮电出版社,2007,8:235-257
[13]曹书华.基于干兆以太网的雷达数据高速采集与传输技术[D].硕士学位论文.南京:南京信息工程大学,2008.
[14]宋虎,陈建军.被动探测中的信号检测技术研究[J].雷达与对抗,2005,(4):6-9
[15]Virtex-Ⅱ Pro User Guide[M].Memec,Inc.2003.
[16]曹俊纺,陈建军,宋虎.雷达信号脉内细微特征参数分析[J].雷达与对抗,2006,(1):48-49
[17]王廷尧.以太网技术及应用[M].北京:人民邮电出版社,2005,1:3-12
[18]Virtex-4 FX12 Mini Module User Guide[M].Memec,Inc.2005.
[19]Virtex-4 User Guide[M].Xilinx,Inc.February 1,2005.
[20]Double Date Rate(DDR) SDRAM Specification[M].JESD79C.March,2003.
[21]512Mb:x4,x8,x16 DDR SDRAM Data Sheets[M].Micron Technology,Inc.2000.
[22]Xilinx Memory Interface Generator(MIG) User Guide[M].Xilinx,Inc.April 30,2007.
[23]许全泉,胡文江,苏里.基于FPGA的以太网控制器设计[J].电子元器件应用,2007,9(6):21-25
[24]杨少波,王勤民,张帆,曲晶.DDR内存接口的设计与实现[J].微计算机信息,2005,21(8-2):102-103
[25]程晓东,郑为民,唐志敏.基于DDR SDRAM控制器时序分析的模型[J].2005,31(17):182-184
[26]徐洪波,俞承芳.基于FPGA的以太网MAC子层协议设计实现.复旦学报[J],2004,43(1):50-53
[27]Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide[M].Xilinx,Inc.November 11,2006.
[28]Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.3[M].Xilinx,Inc.September 21,2006.
[29]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具Xilinx ISE使用详解[M].北京:人民邮电出版社,2005.
[30]徐欣,于红旗,易凡,等.基于FPGA的嵌入式系统设计[M].北京:机械工业出版社,2005,1.
[31]任晓东,文博.CPLD/FPGA高级应用开发指南[M].北京:电子工业出版社,2003,6.
[32]RocketIO Transceiver User Guide[M].Memec,Inc.2003.
[33]MGT Data Sheets[M].Memec,Inc.2003.
[34]祝依龙.脉冲雷达中频信号采集记录系统设计与实现[D].硕士学位论文.长沙:国防科学技术大学,2006.
[35]陆志宏.雷达侦察系统信号处理技术探讨[J].舰船电子对抗.2005(3):38-43
[36]王茹琪,张爱国.雷达接收机多通道高速数据采集系统.电子技术应用,2005,7:35-37.
[37]王长清,顾红.基于PCI总线的大容量雷达数据采集系统的设计.电子技术应用.2002.28(8):45-47
[38]李军,孙鹏举.基于高速磁盘阵列的数据采集系统及其应用.舰船电子对抗2002,25(6):17-19.
[2]马海潮.超高速数据采集技术发展现状[J].测试技术学报,2003,17(4):287-290
[3]陈昊,孙志刚,卢泽新.DDR SDRAM控制器的设计与实现.微计算机应用[J],2007,28(2):170-173
[4]夏玉立,雷宏,黄瑶.用Xilinx FPGA实现DDR SDRAM控制器[J].2007,23(9-2):209-211
[5]李贵山,陈金鹏.PCI局部总线及其应用[M].西安:西安电子科技大学出版社,2003,2.
[6]陶春荣,金艳艳.基于USB接口的数据采集系统[J].雷达与对抗,2004,(1):55-57
[7]杨小牛,楼才义,许建良.软件无线电原理与应用[M].北京:电子工业出版社,2005,7:11-14
[9]AD9430 Datasheet[M].Analog Devices,Inc.2002.
[10]孙航.Xilinx可编程逻辑器件的高级应用与设计技巧[M].北京:电子工业出版社,2004,8.
[11]LT1764 Series[M].Linear Technology Corporation,Inc.2000.
[12]薛小刚,葛毅敏.Xilinx ISE 9.X FPGA/CPLD设计指南[M].北京:人民邮电出版社,2007,8:235-257
[13]曹书华.基于干兆以太网的雷达数据高速采集与传输技术[D].硕士学位论文.南京:南京信息工程大学,2008.
[14]宋虎,陈建军.被动探测中的信号检测技术研究[J].雷达与对抗,2005,(4):6-9
[15]Virtex-Ⅱ Pro User Guide[M].Memec,Inc.2003.
[16]曹俊纺,陈建军,宋虎.雷达信号脉内细微特征参数分析[J].雷达与对抗,2006,(1):48-49
[17]王廷尧.以太网技术及应用[M].北京:人民邮电出版社,2005,1:3-12
[18]Virtex-4 FX12 Mini Module User Guide[M].Memec,Inc.2005.
[19]Virtex-4 User Guide[M].Xilinx,Inc.February 1,2005.
[20]Double Date Rate(DDR) SDRAM Specification[M].JESD79C.March,2003.
[21]512Mb:x4,x8,x16 DDR SDRAM Data Sheets[M].Micron Technology,Inc.2000.
[22]Xilinx Memory Interface Generator(MIG) User Guide[M].Xilinx,Inc.April 30,2007.
[23]许全泉,胡文江,苏里.基于FPGA的以太网控制器设计[J].电子元器件应用,2007,9(6):21-25
[24]杨少波,王勤民,张帆,曲晶.DDR内存接口的设计与实现[J].微计算机信息,2005,21(8-2):102-103
[25]程晓东,郑为民,唐志敏.基于DDR SDRAM控制器时序分析的模型[J].2005,31(17):182-184
[26]徐洪波,俞承芳.基于FPGA的以太网MAC子层协议设计实现.复旦学报[J],2004,43(1):50-53
[27]Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide[M].Xilinx,Inc.November 11,2006.
[28]Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.3[M].Xilinx,Inc.September 21,2006.
[29]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具Xilinx ISE使用详解[M].北京:人民邮电出版社,2005.
[30]徐欣,于红旗,易凡,等.基于FPGA的嵌入式系统设计[M].北京:机械工业出版社,2005,1.
[31]任晓东,文博.CPLD/FPGA高级应用开发指南[M].北京:电子工业出版社,2003,6.
[32]RocketIO Transceiver User Guide[M].Memec,Inc.2003.
[33]MGT Data Sheets[M].Memec,Inc.2003.
[34]祝依龙.脉冲雷达中频信号采集记录系统设计与实现[D].硕士学位论文.长沙:国防科学技术大学,2006.
[35]陆志宏.雷达侦察系统信号处理技术探讨[J].舰船电子对抗.2005(3):38-43
[36]王茹琪,张爱国.雷达接收机多通道高速数据采集系统.电子技术应用,2005,7:35-37.
[37]王长清,顾红.基于PCI总线的大容量雷达数据采集系统的设计.电子技术应用.2002.28(8):45-47
[38]李军,孙鹏举.基于高速磁盘阵列的数据采集系统及其应用.舰船电子对抗2002,25(6):17-19.