基于单片FPGA的数字复接系统设计
摘要
在光纤通信系统中，作为终端设备的光端机由光发射模块、光接收模块、数据接口、用户线接口和数字复接单元等几部分组成。其中数字复接单元用来将若干个低速数字信号合并成一个高速数字信号，以达到扩大传输容量和提高传输速率的目的。目前，数字复接体制主要有准同步数字体系(Parasynchronous Digital Hierarchy，简称PDH)和同步数字体系(Synchronous Digital Hierarchy，简称SDH)，从长远看，SDH终将取代PDH。但由于PDH复接系统信道利用率高，设备简单，因此，在一些小规模、小容量的通信网中，仍具有广泛的市场和应用价值。design
在数字复接系统中，发送端主要由支路时钟提取、码速调整、复接三部分组成，接收端主要由定时脉冲形成、分接、码速恢复三部分组成。在以往的电路中，PDH复接系统的许多部分是利用模拟电路实现，这具有一定的局限性：
(1)模拟电路难以集成，不利于设备的小型化；
(2)模拟电路的稳定性和抗干扰能力差；
(3)模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
(4)模拟电路会增加生产、调试过程中的难度。
本文研究的重点是数字光端机芯片中的数字复接系统的设计与实现。归纳起来本文做了以下具体工作：
(1)、设计了一种低成本、具有12路E1接口、采用单片FPGA实现、通过光纤传输的中小容量数字复接系统。
(2)、芯片内置HDB3编解码器和2Mhz数字时钟提取电路。简化了外围电路设计。
(3)、设计实现了2M数据码速调整和恢复电路，并利用数据平滑技术解决了塞入抖动问题。
(4)、系统设计采用Verilog HDL硬件描述语言编程实现，文中给出了部分计算机仿真结果。
本文的设计成果可用于数字光端机芯片以及片上系统设计中，对数字复接／分接系统的设计具有一定的参考价值。
In optical communication system, the Digital Optical Transceiver is composed of send module and recive module and data interface and user-line interface and the uint of digital Multiplexing. The digital Multiplexing is used to merge signal with low rate from many channels into a high rate data, which can enlarge communication capacity and improve the rate of transfers. There are PDH and SDH in the Multiplexing system at present. The SDH will replace the PDH eventually. But the PDH has higher channel using-rate and simple equipment. It still has large fields and application values in small scope and small capacity communication network.The digital Multiplexing system is mainly composed of digital clock extracting circuit and rate justification and Multiplexing at the send end, it has Timing pulse forming circuit and De Multiplexing and rate Recovery at the receive end. The PDH Multiplexing system is realized by using many analog cicuit, which has localization in some extend:(1) The analog circuit is diffcult to integrate and is not benefit to the small equipment.(2) The analog circuit is worse in stability and antijamming.(3) The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.(4) The analog circuit may improve the difficult during production and debugging.In this paper, the emphases on reseaching the design and realization of digital Multiplexer in optical transceivers system. In general, this paper present the work done as below:(1) Design a low cost and medium capacity Digital Multiplexing system, which has 12 channels El interface and is realized with single chip FPGA.(2) There are HDB3 encode/decode circuit and 2Mhz digital clock extracting circuit in the chip, which predigests the design in periphery circuit.(3) In this paper we design and realize the circuit of 2M positive justification/recovery, and we solve the problem of stuffing jitter by means of utilizing digital smoothing method.(4) The design is programed in Verilog-HDL, and then we present the conclusion of computer simulation respectively.This paper's production can be used on digital optical transceivers and SoC design, and it is valueable reference for the design of multiplexing/demultiplexing system.
在数字复接系统中，发送端主要由支路时钟提取、码速调整、复接三部分组成，接收端主要由定时脉冲形成、分接、码速恢复三部分组成。在以往的电路中，PDH复接系统的许多部分是利用模拟电路实现，这具有一定的局限性：
(1)模拟电路难以集成，不利于设备的小型化；
(2)模拟电路的稳定性和抗干扰能力差；
(3)模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
(4)模拟电路会增加生产、调试过程中的难度。
本文研究的重点是数字光端机芯片中的数字复接系统的设计与实现。归纳起来本文做了以下具体工作：
(1)、设计了一种低成本、具有12路E1接口、采用单片FPGA实现、通过光纤传输的中小容量数字复接系统。
(2)、芯片内置HDB3编解码器和2Mhz数字时钟提取电路。简化了外围电路设计。
(3)、设计实现了2M数据码速调整和恢复电路，并利用数据平滑技术解决了塞入抖动问题。
(4)、系统设计采用Verilog HDL硬件描述语言编程实现，文中给出了部分计算机仿真结果。
本文的设计成果可用于数字光端机芯片以及片上系统设计中，对数字复接／分接系统的设计具有一定的参考价值。
In optical communication system, the Digital Optical Transceiver is composed of send module and recive module and data interface and user-line interface and the uint of digital Multiplexing. The digital Multiplexing is used to merge signal with low rate from many channels into a high rate data, which can enlarge communication capacity and improve the rate of transfers. There are PDH and SDH in the Multiplexing system at present. The SDH will replace the PDH eventually. But the PDH has higher channel using-rate and simple equipment. It still has large fields and application values in small scope and small capacity communication network.The digital Multiplexing system is mainly composed of digital clock extracting circuit and rate justification and Multiplexing at the send end, it has Timing pulse forming circuit and De Multiplexing and rate Recovery at the receive end. The PDH Multiplexing system is realized by using many analog cicuit, which has localization in some extend:(1) The analog circuit is diffcult to integrate and is not benefit to the small equipment.(2) The analog circuit is worse in stability and antijamming.(3) The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.(4) The analog circuit may improve the difficult during production and debugging.In this paper, the emphases on reseaching the design and realization of digital Multiplexer in optical transceivers system. In general, this paper present the work done as below:(1) Design a low cost and medium capacity Digital Multiplexing system, which has 12 channels El interface and is realized with single chip FPGA.(2) There are HDB3 encode/decode circuit and 2Mhz digital clock extracting circuit in the chip, which predigests the design in periphery circuit.(3) In this paper we design and realize the circuit of 2M positive justification/recovery, and we solve the problem of stuffing jitter by means of utilizing digital smoothing method.(4) The design is programed in Verilog-HDL, and then we present the conclusion of computer simulation respectively.This paper's production can be used on digital optical transceivers and SoC design, and it is valueable reference for the design of multiplexing/demultiplexing system.
引文
[1] 王瀚晟，曾烈光．全数字化PDH复接系统的设计．电信科学，1998，4：6～7．
[2] http://www.fpga.com.cn
[3] http://www.xilinx.com (xilinx资料)
[4] 王钦笙．数字通信原理[M]．北京：人民邮电出版社，1993．
[5] 江沩．多路复用的方法及30／32路PCM帧结构．现代通信，2000，8：30～31．
[6] 王廷尧．光纤同步网讲座．光通信技术，1993，Vol 18，No 1：41～44．
[7] 王瀚晟，曾烈光．复接系统定时的数字提取技术及其性能．通信学报，1999，6，Vol 20，No 6：91～93．
[8] 卢汉生，侯山峰．采用EPLD设计的数字锁相环．光电工程，1997，10，Vol 24，No 5：59～62．
[9] 冯重熙．数字传输技术[M]．北京：人民邮电出版社，1993．
[10] 孙玉．数字复接技术．北京：人民邮电出版社，1998．
[11] ITU TG. 742.
[12] 吕志斌．数字通信网中帧同步的实现方式．微波与卫星通信，1997，3：22～24．
[13] 范亚希，葛宁．以太网到多路El适配电路设计及FPGA实现．电子技术应用，2002，11：72～75．
[14] 单长虹，孟宪元．基于FPGA的全数字锁相环路的设计．电子技术应用，2001，9：58～60．
[15] 杨静．采用在系统可编程逻辑器件实现HDB3编解码．北京联合大学学报，1998，12(1)：76～81．
[16] 郭华泉．数字微波设备中的帧复接方式．微波与卫星通信，1995，2：28～30．
[17] 谢润华，黄佩伟．多速率码流同步复接方案设计与实现．通信技术，2001，5：20～22．
[18] 习建华，龚建荣．用FPGA实现二次群复接器．数字通信，1999，3：56～57．
[19] 葛宁，冯重熙．干扰抖动的的非线性损伤及抑制方法．通信学报，1996，17(3)
[20] 曾烈光，冯重熙。数字网中的抖动．电信科学，1987(12)：49～56
[21] G. Pierobon, R. P. Valussi. "Jitter analysis of a double modulated threshold pulse stuffing synchronizer, "IEEE Transactions on Communication, Vol. 39, Issue: 4, PP. 594-602, Aoril 1991
[22] 孙玉．数字网传输损伤．北京：人民邮电出版社，1991
[23] 曾烈光．一种减小正码速调整等候抖动的新方法．通信学报，1992，13(1)：45～51
[24] J. Bhasker箸，徐振林 等译．Verilog HDL硬件描述语言．机械工业出版社，2000，7．
[25] 王小军编著VHDL简明教程[M]．乔长阁等译．北京：清华大学出版社，1997．
[26] 夏宇闻．从算法涉及到硬线逻辑的实现—复杂数字逻辑系统的Verilog HDL设计技术和方法[M]．高等教育出版社，2001．
[27] http://www.vhdl.org/
[28] http://www.verilog.org/
[29] http://www.edaen.eom (论坛)
[2] http://www.fpga.com.cn
[3] http://www.xilinx.com (xilinx资料)
[4] 王钦笙．数字通信原理[M]．北京：人民邮电出版社，1993．
[5] 江沩．多路复用的方法及30／32路PCM帧结构．现代通信，2000，8：30～31．
[6] 王廷尧．光纤同步网讲座．光通信技术，1993，Vol 18，No 1：41～44．
[7] 王瀚晟，曾烈光．复接系统定时的数字提取技术及其性能．通信学报，1999，6，Vol 20，No 6：91～93．
[8] 卢汉生，侯山峰．采用EPLD设计的数字锁相环．光电工程，1997，10，Vol 24，No 5：59～62．
[9] 冯重熙．数字传输技术[M]．北京：人民邮电出版社，1993．
[10] 孙玉．数字复接技术．北京：人民邮电出版社，1998．
[11] ITU TG. 742.
[12] 吕志斌．数字通信网中帧同步的实现方式．微波与卫星通信，1997，3：22～24．
[13] 范亚希，葛宁．以太网到多路El适配电路设计及FPGA实现．电子技术应用，2002，11：72～75．
[14] 单长虹，孟宪元．基于FPGA的全数字锁相环路的设计．电子技术应用，2001，9：58～60．
[15] 杨静．采用在系统可编程逻辑器件实现HDB3编解码．北京联合大学学报，1998，12(1)：76～81．
[16] 郭华泉．数字微波设备中的帧复接方式．微波与卫星通信，1995，2：28～30．
[17] 谢润华，黄佩伟．多速率码流同步复接方案设计与实现．通信技术，2001，5：20～22．
[18] 习建华，龚建荣．用FPGA实现二次群复接器．数字通信，1999，3：56～57．
[19] 葛宁，冯重熙．干扰抖动的的非线性损伤及抑制方法．通信学报，1996，17(3)
[20] 曾烈光，冯重熙。数字网中的抖动．电信科学，1987(12)：49～56
[21] G. Pierobon, R. P. Valussi. "Jitter analysis of a double modulated threshold pulse stuffing synchronizer, "IEEE Transactions on Communication, Vol. 39, Issue: 4, PP. 594-602, Aoril 1991
[22] 孙玉．数字网传输损伤．北京：人民邮电出版社，1991
[23] 曾烈光．一种减小正码速调整等候抖动的新方法．通信学报，1992，13(1)：45～51
[24] J. Bhasker箸，徐振林 等译．Verilog HDL硬件描述语言．机械工业出版社，2000，7．
[25] 王小军编著VHDL简明教程[M]．乔长阁等译．北京：清华大学出版社，1997．
[26] 夏宇闻．从算法涉及到硬线逻辑的实现—复杂数字逻辑系统的Verilog HDL设计技术和方法[M]．高等教育出版社，2001．
[27] http://www.vhdl.org/
[28] http://www.verilog.org/
[29] http://www.edaen.eom (论坛)