SOI横向高压器件耐压模型和新器件结构研究
摘要
SOI(Silicon On Insulator)高压集成电路因其隔离性能好、漏电流小、速度快、功耗低和抗辐照等优点已成为功率集成电路(Power Integrated Circuit,PIC)重要的发展方向。SOI横向高压器件是SOI高压集成电路的核心和关键,受到了国际上众多学者的研究。但是,由于受到纵向耐压的限制,当前真正进入实用阶段的器件结构,其击穿电压还没有超过600V,从而限制了SOI技术在千伏级高压集成电路中的应用。此外,在设计方面,当前所沿用的设计理论仍然是体硅的RESURF判据,但事实上,SOI器件结构上的特殊性使其RESURF效应和体硅器件有较大差异,这一点在设计中却往往被忽视。
本文围绕SOI高压器件的耐压问题,从理论模型和器件结构两方面展开创新研究。首次提出了两项耐压理论:S-RESURF(Single REduced SURface Field)高压器件全域耐压模型和D-RESURF(Double REduced SURface Field)高压器件统一耐压模型,设计了两种新结构器件:埋氧层固定电荷结构(Step Buried Oxide fixed Charge,SBOC)和局域电荷槽结构(Charge Captured Trenches,CCT),并进行了部分实验。
两项耐压理论是:
1) SOI S-RESURF高压器件全域耐压模型。提出均匀、阶梯和线性漂移区的SOI S-RESURF高压器件全域耐压模型,导出包含耗尽区电荷共享效应与埋氧层电场调制效应的SOI S-RESURF判据。基于电势分解法求解二维Poisson方程,得到了任意漂移区横向杂质分布的SOI S-RESURF器件在全耗尽和不全耗尽情况下的二维电势和电场分布全域解析模型,然后将其应用于均匀、阶梯和线性漂移区结构的分析,给出了最优浓度分布的理论公式和最小阶梯数判据。最后,在此理论指导下,在3μm顶层硅、1.5μm埋氧层的SOI材料上成功研制了耐压为250V,导通电阻为1.6Ωmm~2的二阶掺杂SOI LDMOS,其耐压比相同结构的均匀掺杂漂移区器件提高了57%,而导通电阻下降了11%。
2) SOI D-RESURF高压器件统一耐压模型。提出均匀、阶梯和线性掺杂SOI D-RESURF高压器件二维耐压解析模型,构成了系统的SOI D-RESURF统一耐压理论,并首次给出了普适于所有双层漂移区器件的SOI D-RESURF判据。首先借助P-top结深因子,把D-RESURF器件等效成阶梯S-RESURF器件,进而建立了具有均匀、阶梯和线性掺杂P-top层的SOI D-RESURF器件的二维势场分布模型,然后借助该模型对器件耐压特性进行了深入分析,首次定量研究了D-RESURF器件比S-RESURF器件耐压略微降低的机理,建立了浓度优化区DOR(Doping Optimal Region)。并首次得到了阶梯和线性掺杂P-top层浓度分布的理论优化公式,提出了最优P-top层阶梯数判据,为SOI D-RESURF器件的设计提供理论依
SOI HVIC (Silicon On Insulator High Voltage Integrated Circuit) is the mainstream and trend of the Power Integrated Circuit (PIC) due to the improved isolation, reduced leakage current, high speed performance, low power dissipation, and perfect irradiation hardness. As one of the key device in SOI HVIC, SOI lateral high voltage device has been deeply investigated in this field. It is shown that the breakdown voltage of SOI power device is lower than 600V due to the restriction of the vertical blocking capacity, which limits the application of 1000V-level SOI HVIC. Moreover, the conventional RESURF criterion of silicon device is still used on the design of SOI high voltage device, however, the buried oxide layer prevents the depletion region expanding into the substrate and thus brings about some new characteristic in SOI RESURF effect, and these effects are always neglected.In this thesis, the breakdown voltage problem of SOI lateral high voltage device is addressed. A unified breakdown model of S-RESURF (Single REduced SURface Field) device with varied drift doping profiles and a unified breakdown model of D-RESURF (Double REduced SURface Field) device with varied P-top doping profiles are firstly proposed. Two new SOI devices with Step Buried Oxide fixed Charge (SBOC) and Charge Captured Trenches (CCT) are developed, which break the vertical breakdown limitation of the conventional SOI device. The partial experiments are carried out.A unified breakdown model of SOI S-RESURF device with varied drift doping profiles is proposed and an S-RESURF criterion including the charge sharing effect in depletion region and the electric field modulating effect of buried oxide layer is firstly derived. By solving 2-D Poisson equation, the analytical description of the 2-D electric field and potential distributions of the device with uniform, step and linear drift doping profiles for the completely and incompletely drift regions are given. The impact of the geometry parameters and drift doping concentration on breakdown voltage is investigated for the varied drift doping profiles. An optimized drift doping profile and a minimized step number are derived to carry out a uniform surface electric field and thus maximize the breakdown voltage. Experimentally, the 250V and 1.6Ωmm2 LDMOS with two step drift doping profiles have been fabricated on the 3 urn-thick top silicon film and 1.5μm-thick buried oxide layer. The measured results have shown that the two step doping profiles bring about an increase in the breakdown voltage by as much as 57% , and also a decrease in the on-resistance by as much as 11% in comparison to the conventional uniformly doped drift device. The numerical and
experimental results have been shown to support the theoretical model for both the incompletely and completely depleted drift region.A unified breakdown model of SOI D-RESURF device with varied P-top doping profiles is developed and a D-RESURF criterion for SOI high voltage device is demonstrated for the first time. Based on solving 2-D Poisson equation, the 2-D analytical models of SOI D-RESURF device with uniform, step and linear P-top doping profiles are proposed, respectively. The three mentioned models form an integrated breakdown theory for the D-RESURF SOI device. The relationship between the structural parameters and breakdown characteristic is studied. A RESURF Doping Optimal Region (DOR) for optimizing the drift region concentration is given and extended into the design of the SOI device with double drift layer. A theoretical optimum P-top doping distribution and a minimum step-number criterion are firstly reported to realize the tradeoff among the performance, structure and process. The analytical model is verified by numerical simulations and published experimental data. A new SOI high voltage device with step buried oxide layer charge (SBOC) is proposed. Firstly, a new theory, INBOLF (INcreased Buried Oxide Layer Field) theory, is proposed to improve the vertical breakdown voltage by increasing the electric field of buried oxide layer. This breakdown theory brings out a new approach to improve the vertical blocking capacity in SOI high voltage device. Based on the theory, the immobile charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson's equation is solved to demonstrate the modulation effect of the fixed interface charges and analyze the electric field and breakdown voltage at the various geometric parameters and step number for the new SBOC device. In the lateral direction, the new device can increase the electric field of buried oxide layer from the conventional 90V/um to the critical value of SiO2 600V/um. In the vertical direction, a near uniform surface electric field can be obtained by optimizing the distribution of the fixed interface charges. As a result, 1200V breakdown voltage is firstly realized in a structure with top Si layer of 3um, buried oxide layer of 2u.m and drift length of 70um. The breakdown voltage is only 190V for the conventional device with the same geometry parameters.A new SOI high voltage device with single-sided or double-sided charge captured trench (CCT) is proposed. For the novel structure on the reverse-biased state, high density interface charge increasing from the source to the drain are distributed on the
本文围绕SOI高压器件的耐压问题,从理论模型和器件结构两方面展开创新研究。首次提出了两项耐压理论:S-RESURF(Single REduced SURface Field)高压器件全域耐压模型和D-RESURF(Double REduced SURface Field)高压器件统一耐压模型,设计了两种新结构器件:埋氧层固定电荷结构(Step Buried Oxide fixed Charge,SBOC)和局域电荷槽结构(Charge Captured Trenches,CCT),并进行了部分实验。
两项耐压理论是:
1) SOI S-RESURF高压器件全域耐压模型。提出均匀、阶梯和线性漂移区的SOI S-RESURF高压器件全域耐压模型,导出包含耗尽区电荷共享效应与埋氧层电场调制效应的SOI S-RESURF判据。基于电势分解法求解二维Poisson方程,得到了任意漂移区横向杂质分布的SOI S-RESURF器件在全耗尽和不全耗尽情况下的二维电势和电场分布全域解析模型,然后将其应用于均匀、阶梯和线性漂移区结构的分析,给出了最优浓度分布的理论公式和最小阶梯数判据。最后,在此理论指导下,在3μm顶层硅、1.5μm埋氧层的SOI材料上成功研制了耐压为250V,导通电阻为1.6Ωmm~2的二阶掺杂SOI LDMOS,其耐压比相同结构的均匀掺杂漂移区器件提高了57%,而导通电阻下降了11%。
2) SOI D-RESURF高压器件统一耐压模型。提出均匀、阶梯和线性掺杂SOI D-RESURF高压器件二维耐压解析模型,构成了系统的SOI D-RESURF统一耐压理论,并首次给出了普适于所有双层漂移区器件的SOI D-RESURF判据。首先借助P-top结深因子,把D-RESURF器件等效成阶梯S-RESURF器件,进而建立了具有均匀、阶梯和线性掺杂P-top层的SOI D-RESURF器件的二维势场分布模型,然后借助该模型对器件耐压特性进行了深入分析,首次定量研究了D-RESURF器件比S-RESURF器件耐压略微降低的机理,建立了浓度优化区DOR(Doping Optimal Region)。并首次得到了阶梯和线性掺杂P-top层浓度分布的理论优化公式,提出了最优P-top层阶梯数判据,为SOI D-RESURF器件的设计提供理论依
SOI HVIC (Silicon On Insulator High Voltage Integrated Circuit) is the mainstream and trend of the Power Integrated Circuit (PIC) due to the improved isolation, reduced leakage current, high speed performance, low power dissipation, and perfect irradiation hardness. As one of the key device in SOI HVIC, SOI lateral high voltage device has been deeply investigated in this field. It is shown that the breakdown voltage of SOI power device is lower than 600V due to the restriction of the vertical blocking capacity, which limits the application of 1000V-level SOI HVIC. Moreover, the conventional RESURF criterion of silicon device is still used on the design of SOI high voltage device, however, the buried oxide layer prevents the depletion region expanding into the substrate and thus brings about some new characteristic in SOI RESURF effect, and these effects are always neglected.In this thesis, the breakdown voltage problem of SOI lateral high voltage device is addressed. A unified breakdown model of S-RESURF (Single REduced SURface Field) device with varied drift doping profiles and a unified breakdown model of D-RESURF (Double REduced SURface Field) device with varied P-top doping profiles are firstly proposed. Two new SOI devices with Step Buried Oxide fixed Charge (SBOC) and Charge Captured Trenches (CCT) are developed, which break the vertical breakdown limitation of the conventional SOI device. The partial experiments are carried out.A unified breakdown model of SOI S-RESURF device with varied drift doping profiles is proposed and an S-RESURF criterion including the charge sharing effect in depletion region and the electric field modulating effect of buried oxide layer is firstly derived. By solving 2-D Poisson equation, the analytical description of the 2-D electric field and potential distributions of the device with uniform, step and linear drift doping profiles for the completely and incompletely drift regions are given. The impact of the geometry parameters and drift doping concentration on breakdown voltage is investigated for the varied drift doping profiles. An optimized drift doping profile and a minimized step number are derived to carry out a uniform surface electric field and thus maximize the breakdown voltage. Experimentally, the 250V and 1.6Ωmm2 LDMOS with two step drift doping profiles have been fabricated on the 3 urn-thick top silicon film and 1.5μm-thick buried oxide layer. The measured results have shown that the two step doping profiles bring about an increase in the breakdown voltage by as much as 57% , and also a decrease in the on-resistance by as much as 11% in comparison to the conventional uniformly doped drift device. The numerical and
experimental results have been shown to support the theoretical model for both the incompletely and completely depleted drift region.A unified breakdown model of SOI D-RESURF device with varied P-top doping profiles is developed and a D-RESURF criterion for SOI high voltage device is demonstrated for the first time. Based on solving 2-D Poisson equation, the 2-D analytical models of SOI D-RESURF device with uniform, step and linear P-top doping profiles are proposed, respectively. The three mentioned models form an integrated breakdown theory for the D-RESURF SOI device. The relationship between the structural parameters and breakdown characteristic is studied. A RESURF Doping Optimal Region (DOR) for optimizing the drift region concentration is given and extended into the design of the SOI device with double drift layer. A theoretical optimum P-top doping distribution and a minimum step-number criterion are firstly reported to realize the tradeoff among the performance, structure and process. The analytical model is verified by numerical simulations and published experimental data. A new SOI high voltage device with step buried oxide layer charge (SBOC) is proposed. Firstly, a new theory, INBOLF (INcreased Buried Oxide Layer Field) theory, is proposed to improve the vertical breakdown voltage by increasing the electric field of buried oxide layer. This breakdown theory brings out a new approach to improve the vertical blocking capacity in SOI high voltage device. Based on the theory, the immobile charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson's equation is solved to demonstrate the modulation effect of the fixed interface charges and analyze the electric field and breakdown voltage at the various geometric parameters and step number for the new SBOC device. In the lateral direction, the new device can increase the electric field of buried oxide layer from the conventional 90V/um to the critical value of SiO2 600V/um. In the vertical direction, a near uniform surface electric field can be obtained by optimizing the distribution of the fixed interface charges. As a result, 1200V breakdown voltage is firstly realized in a structure with top Si layer of 3um, buried oxide layer of 2u.m and drift length of 70um. The breakdown voltage is only 190V for the conventional device with the same geometry parameters.A new SOI high voltage device with single-sided or double-sided charge captured trench (CCT) is proposed. For the novel structure on the reverse-biased state, high density interface charge increasing from the source to the drain are distributed on the
引文
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