基于累加器的DSP数据通路的内建自测试技术的研究
摘要
片上系统(SoC)技术的快速发展对包括数字信号处理器(DSP)在内的各种VLSI测试带来了挑战。内建自测试(BIST)技术已成为解决VLSI测试难题和降低测试成本的重要手段。基于累加器的BIST因复用VLSI中的部分加法器作为VLSI的测试生成器、测试响应压缩器,能够减少硬件开销且性能好,近几年正成为VLSI测试领域的研究热点之一。本论文基于累加器,对DSP数据通路的BIST技术进行了创新性和探索性研究,主要包括以下五方面内容。
1.提出并详细探讨了BIST环境中DSP数据通路的一种基于扫描通路法的可测性设计方案:利用三态门,实现DSP数据通路测试状态与工作状态的转换,在测试状态下将数据通路中的部分寄存器转化成扫描链,并切断数据通路中的反馈回路。该方案通用性强、可测性好、额外硬件开销小且不会降低原VLSI性能。
2.研究了基于累加器的BIST环境中DSP数据通路的测试生成。证明了n位加/减法器的2n位测试矢量(TP)可由两个n位累加器产生的矢量合成。针对DSP数据通路中加/减法器的具体情况,通过优化TP最低位子空间,探索出了基于累加器的一种测试生成优化方法。仿真实验表明,优化TP能完全覆盖加法器的组合固定型故障。研究出了阵列乘法器的TP,证明了这些TP能由累加器生成。仿真实验表明,这些TP能完全覆盖阵列乘法器的单、双组合固定型故障。同时,分析了常输入乘法器的TP,指出这些TP可由累加器产生。
3.研究了累加器生成的TP,提出了基于累加器的BIST环境中DSP数据通路低功耗测试生成的一种有效方法:对测试矢量进行伪格雷码编码,以在测试期间降低被测电路模块的开关活动率,该编码通过复用数据通路中的加法器经济地予以实现。仿真实验表明,编码后的TP较大地降低了基于累加器的BIST测试功耗。
4.研究了基于累加器的BIST环境中DSP数据通路分阶分层的测试方法:将DSP数据通路中部分加法器复用成其测试生成器,部分寄存器复用成扫描链,根据DSP数据通路的结构规则性,按阶逐层地完成DSP数据通路的测试。该方法通用性强、测试效率高、测试时间短、故障覆盖率高、额外硬件开销小。
5.研究了基于累加器测试生成的加法器测试,提出了DSP数据通路中加法器的一种有效自测试方案。扩展了测试响应累加器压缩思想,提出了加法器的一种BIST方案。根据这些方案,对行波进位加法器分别进行了自测试、BIST的原理性电路设计。仿真实验表明,这些自测试、BIST的测试性能高,额外硬件开销小。该研究有助于解决基于累加器的BIST环境中DSP数据通路的测试生成器和响应压缩器的自测试难题。
With the rapid development of System-on-Chip technology, it brings challenges to the testing of all kinds of VLSI which include Digital Signal Processor (DSP). Built-in Self-Test (BIST) has become an important approach for testing VLSI that reduces test complexity and cost. Because reuses of some adders in VLSI as generators of test patterns (TP) and compactors of test responses result in reduction of additional hardware overhead for the VLSI test, accumulator-based BIST has good performance and has recently been highly recognized in VLSI test research field. This dissertation reports an investigation on accumulator-based BIST for DSP data path. Major works for this innovative research consist of five aspects as followings:
1. In BIST environment, A scheme of Design-for-Testability for DSP data path is proposed and investigated based on scan path method. For the scheme, tristate gates are utilized to implement the mode switches for test and work, and convert some registers in DSP data path into scan chains and cut off feedback loops in DSP data path during testing. This scheme has advantages such as good generality, good testability, and low additional hardware overhead without degradation of performance for original VLSI.
2. In accumulator-based BIST environment, TP generation for DSP data path is discussed. It is proved that 2n-bit TP for n-bit adder and subtracter can be synthesized by vectors from two n-bit accumulators. Regarding details of adder and subtracter in DSP data path, an optimized method for the TP generation based on accumulator is explored through optimizing the lowest significant subspace of the TP. Results of simulation experiments show that the optimaized TP cover combinational stuck-at faults of adder completely. TP of array multiplier are studied and it is proved that accumulator can generate them too. Simulation results show that the TP can cover all single and double combinational stuck-at faults of array multiplier. At the same time, TP of constant input multiplier are discussed and it is pointed out that accumulator can generate them.
3. TP generated by accumulators are studied and an effective method to generate TP for low power consumption testing of DSP data path in accumulator-based BIST environment is presented. Basic idea of the method is that encoded the TP produced by accumulation generator into Pseudo Gray Code to reduce the overall switching activities of the circuit module during testing. This code can be implemented economically by reusing the adder in DSP data path. Simulation results show that the encoded TP could greatly decrease test power consumption in accumulatior-based BIST environment.
4. A method for testing in order and layer is researched for DSP data path in the environment of BIST based on accumulator. For this method, some adders in DSP data path are reused as generators of its TP and some registers in data path as scan chains. According to the regularity of DSP data path architecture, testing of DSP data path is performed in order and layer. This approach has advantages such as good generality, high efficiency, short testing duration, high fault coverage and low consumption for additional hardware.
5. Adder test based on accumulaor generation is researched and an effective way is presented for the self-test of adders in DSP data path. Mind of accumulator-based compression of test response is extended, and then a BIST scheme for adders is proposed. According to the schemes, the concept designs are carried out for the self-test and BIST of ripple carry adder, respectively. Simulation shows that the self-test and BIST indicated above has the advantages, such as high testing capability and low additional hardware overhead. These researches will be helpful to solve the critical self-test issues regarding accumulation-based generator and compressor of DSP data path in accumulator-based BIST environment.
1.提出并详细探讨了BIST环境中DSP数据通路的一种基于扫描通路法的可测性设计方案:利用三态门,实现DSP数据通路测试状态与工作状态的转换,在测试状态下将数据通路中的部分寄存器转化成扫描链,并切断数据通路中的反馈回路。该方案通用性强、可测性好、额外硬件开销小且不会降低原VLSI性能。
2.研究了基于累加器的BIST环境中DSP数据通路的测试生成。证明了n位加/减法器的2n位测试矢量(TP)可由两个n位累加器产生的矢量合成。针对DSP数据通路中加/减法器的具体情况,通过优化TP最低位子空间,探索出了基于累加器的一种测试生成优化方法。仿真实验表明,优化TP能完全覆盖加法器的组合固定型故障。研究出了阵列乘法器的TP,证明了这些TP能由累加器生成。仿真实验表明,这些TP能完全覆盖阵列乘法器的单、双组合固定型故障。同时,分析了常输入乘法器的TP,指出这些TP可由累加器产生。
3.研究了累加器生成的TP,提出了基于累加器的BIST环境中DSP数据通路低功耗测试生成的一种有效方法:对测试矢量进行伪格雷码编码,以在测试期间降低被测电路模块的开关活动率,该编码通过复用数据通路中的加法器经济地予以实现。仿真实验表明,编码后的TP较大地降低了基于累加器的BIST测试功耗。
4.研究了基于累加器的BIST环境中DSP数据通路分阶分层的测试方法:将DSP数据通路中部分加法器复用成其测试生成器,部分寄存器复用成扫描链,根据DSP数据通路的结构规则性,按阶逐层地完成DSP数据通路的测试。该方法通用性强、测试效率高、测试时间短、故障覆盖率高、额外硬件开销小。
5.研究了基于累加器测试生成的加法器测试,提出了DSP数据通路中加法器的一种有效自测试方案。扩展了测试响应累加器压缩思想,提出了加法器的一种BIST方案。根据这些方案,对行波进位加法器分别进行了自测试、BIST的原理性电路设计。仿真实验表明,这些自测试、BIST的测试性能高,额外硬件开销小。该研究有助于解决基于累加器的BIST环境中DSP数据通路的测试生成器和响应压缩器的自测试难题。
With the rapid development of System-on-Chip technology, it brings challenges to the testing of all kinds of VLSI which include Digital Signal Processor (DSP). Built-in Self-Test (BIST) has become an important approach for testing VLSI that reduces test complexity and cost. Because reuses of some adders in VLSI as generators of test patterns (TP) and compactors of test responses result in reduction of additional hardware overhead for the VLSI test, accumulator-based BIST has good performance and has recently been highly recognized in VLSI test research field. This dissertation reports an investigation on accumulator-based BIST for DSP data path. Major works for this innovative research consist of five aspects as followings:
1. In BIST environment, A scheme of Design-for-Testability for DSP data path is proposed and investigated based on scan path method. For the scheme, tristate gates are utilized to implement the mode switches for test and work, and convert some registers in DSP data path into scan chains and cut off feedback loops in DSP data path during testing. This scheme has advantages such as good generality, good testability, and low additional hardware overhead without degradation of performance for original VLSI.
2. In accumulator-based BIST environment, TP generation for DSP data path is discussed. It is proved that 2n-bit TP for n-bit adder and subtracter can be synthesized by vectors from two n-bit accumulators. Regarding details of adder and subtracter in DSP data path, an optimized method for the TP generation based on accumulator is explored through optimizing the lowest significant subspace of the TP. Results of simulation experiments show that the optimaized TP cover combinational stuck-at faults of adder completely. TP of array multiplier are studied and it is proved that accumulator can generate them too. Simulation results show that the TP can cover all single and double combinational stuck-at faults of array multiplier. At the same time, TP of constant input multiplier are discussed and it is pointed out that accumulator can generate them.
3. TP generated by accumulators are studied and an effective method to generate TP for low power consumption testing of DSP data path in accumulator-based BIST environment is presented. Basic idea of the method is that encoded the TP produced by accumulation generator into Pseudo Gray Code to reduce the overall switching activities of the circuit module during testing. This code can be implemented economically by reusing the adder in DSP data path. Simulation results show that the encoded TP could greatly decrease test power consumption in accumulatior-based BIST environment.
4. A method for testing in order and layer is researched for DSP data path in the environment of BIST based on accumulator. For this method, some adders in DSP data path are reused as generators of its TP and some registers in data path as scan chains. According to the regularity of DSP data path architecture, testing of DSP data path is performed in order and layer. This approach has advantages such as good generality, high efficiency, short testing duration, high fault coverage and low consumption for additional hardware.
5. Adder test based on accumulaor generation is researched and an effective way is presented for the self-test of adders in DSP data path. Mind of accumulator-based compression of test response is extended, and then a BIST scheme for adders is proposed. According to the schemes, the concept designs are carried out for the self-test and BIST of ripple carry adder, respectively. Simulation shows that the self-test and BIST indicated above has the advantages, such as high testing capability and low additional hardware overhead. These researches will be helpful to solve the critical self-test issues regarding accumulation-based generator and compressor of DSP data path in accumulator-based BIST environment.
引文
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