一种高效同步升压型芯片中过零检测电路的研究与分析
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摘要
随着电子和通讯技术的不断发展,便携式电子设备电源管理芯片逐渐成为功率半导体集成电路最重要的应用领域之一。高集成度、高效率和低成本是此类电源芯片最重要的特点。
     鉴于检测电路在高效率电流模式电源管理芯片或者其他公路电子等模拟应用中的无法比拟的作用,当前学术界、工业界都投入了大量的精力研究比较成熟的检测方法以及相对应的高性能检测电路。
     本设计研究的目的是为变换器能够在更宽的负载范围内具有高效率,即变换器不仅在重载情况具有高效率,同时也要提升轻载的效率。当中小型功率设备处于闲置状态时,即轻载或无载状态时,转换器的控制模式由PWM控制模式自动转换到跳周期PFM模式,即PSM(Pulse Skipping Mode)模式。当用电设备休眠时,电源芯片的负载为轻载状态,意味着电感电流有可能在下一充电周期之前放电到零(Discontinuous Current Mode DCM模式),一旦电感电流为零后,稳压电容就通过同步整流管对电感充电,此时电感电流变为反向,本文提出采用零电流检测电路,当电感电流小于某值时,关闭同步整流管,使体二极管开始工作,此法最大限度延长了同步整流管工作的时间,并且避免了电感电流反向,实现了效率最大提升。考虑到电路中存在延时,其中包括零电流比较器的转换时间,逻辑电路延时,驱动电路延时和开关管关闭的延时。如果将零电流检测比较器的门限设置在电感电流刚好为零时,就很可能已经发生电感电流倒灌,所以采取提前值关断。本文中将零电流比较器的门限设置在电感电流为50mA,当电感电流下降到50mA时,零电流比较器翻转,PMOS管关闭。
     本文从对零电流检测电路的设计指标开始,先后阐述了如何选择控制模式,如何选择电阻模型,以及对开关管和整流管的尺寸进行了研究,另外为达到更高的精确度,还进行了电阻修调,最后提出了本设计的电路结构,与现有零电流检测电路结构进行比较,对结构进行了详细的原理分析和系统仿真。
     最后针对系统性能参数的变化,如性能不稳定、参数发生漂移和退化等,对本设计结构电路进行了容差分析。它大大减轻了建立电路模型的工作量和避免了对复杂运算的处理,不但能实现以EDA技术为基础的通用电路容差分析技术和方法,而且能够实现电路性能和可靠性的并行设计分析。
With the development of electric and communication technology, portable power is increasingly becoming the most important application area for power semiconductor integrated circuits. High level of integration, high efficiency and low cost are the most desired features for portable power ICs.
     In view of the high efficiency of detection circuit current-mode power management chips or other electronic highway simulation applications, such as the incomparable role in the current academia, industry has invested a lot of energy on more mature detection methods and on relatively high-performance detection circuit.
     The purpose of the design is to widen the scope of the load with high efficiency, that is, not onlyverter can load range with high efficiency, that is, not only in the heavy-duty situations converter has high efficiency, but also improve the efficiency of light-load. When small or medium-sized power equipment is in the idle state, that is, light-load or no-load conditions, the PWM control mode jumps to pulse-skipping PFM mode automaticly, PSM model. When electrical equipment is dormant, the load of power chip is in light-load conditions, which means that the inductor current may be discharge to zero before next recharge cycles (Discontinuous Current Mode DCM mode), once the inductor current is zero, the regulator capacitance will be charged through the Synchronous rectifier (SR), at that time the inductor current jumps into reverse, this paper presents a zero-current detection circuit, when the inductor current value in a small, close the SR, the Schottky begin to work to extend the maximum working hours of the SR, and avoid the reverse inductor current to achieve maximum efficiency upgrade. Taking into account delay in the circuit, including the comparison of the zero-current conversion, logic delay, delay and driving circuit interrupters closed delay. If the threshold of the zero-current detection comparator is setted exactly when the inductor current is zero, inductor current flow backward will be likely to occurre, so advanced shutdown is taken into account. This paper will compare with zero-current threshold set in the inductor current of 50mA, when the inductor current drops to 50mA, zero-current comparators and overturned, the PMOS closed.
     Based on the zero-current detection circuit design specifications, the paper has described how to choose the control mode, how to choose resistance model, as well as switch and the size of a SR research, and to achieve a higher degree of accuracy, but has also carried out Resistance tuning, the final design of the proposed structure of the circuit, the principle of detailed analysis and system simulation.
     Finally system performance parameters, such as the performance of instability, parameters drift and degradation and so on, tolerance analysis is done to the structure of the design. It greatly reduced the workload of the establishment of circuit model and avoided the handling of complex computing, not only the realization of EDA technology-based generic circuit tolerance analysis technology and methods, but also to achieve circuit performance and reliability of the parallel design.
引文
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