基于FPGA的视频转换接口的研究与设计
摘要
随着计算机、多媒体和数字通信技术的迅速发展,一方面使得视频技术得到了促进和推动,另一方面也使得不同数字显示设备之间的接口互联问题日益突出,然而在当今市场上对于数字互联问题的重视还不够,在两个不同的接口之间进行转换的设备还比较少见。
本论文详细介绍了一种基于FPGA的视频转换接口的设计方案,这个接口主要功能是实现了对输入的NTSC制式的视频信号进行转换。接口电路使用ADV7181B芯片对视频信号进行解码处理,被解码的信号为ITU_R656标准8位数据信号。本系统使用FPGA作为开发平台,由I2C总线配置模块、解交织模块、缓存模块、色度空间转换模块和VGA时序转化模块组成。其中,缓存设计采用场内行插入法实现隔行扫描变换为逐行扫描,利用流水线技术对色度空间进行转换;在ADV7123芯片解码下,图像通过VGA控制模块在VGA显示器上得到显示。
本论文中的主控制器采用Verilog HDL作为硬件描述语言,系统在Quartus II 6.0, Modelsim SE 6.0软件平台下开发,采用FPGA可编程芯片,让整个系统拥有了较大的灵活性,不仅提高了数字接口的转换速度,而且还可以很方便的利用芯片的可配置性来完成系统的在线升级维护,提升了系统的应用价值。
With the rapid development of computer, multimedia and digital communication technology, on the one hand video technology is advanced and boosted, on the other attachment of interface appears many problem to be solved among different digital display equipment. But it was paid no enough attention to on the market, and it is seldom seen between different interfaces.
A solution of embeded Video Conversion Interface based on FPGA was introduced detailed in this paper, which had the function of video conversion for format NTSC. The analog video signals were converted to the 8 bit standard digital video signals according with ITU_R656 by video A/D processor ADV7181B. The system used Altera Corporation’s FPGA as the development platform. It was composed of I2C configuration module, deinterlace module, image frame storing control module, color space conversion module and VGA timing configuration module. Among them, the cache design uses at the line insertion method for the realization of interlaced scanning transform progressive scanning. The color space conversion was used by pipeline technology, Digital video signals were sent to the image frame storages. After the color space conversion by FPGA, the system changed its schedule. The VGA controller module sent the video signals to the VGA, which made the video signals displayed by ADV7123.
Verilog HDL has been adopted in the design of the main controller in the paper. The system was developed under the platforms of Quartus II 6.0 and Modelsim SE 6.0 software. It was implemented in FPGA and made it flexible. The system can not only boost digital interface conversion velocity but also fulfill system upgraded online conveniently by chip of allocation, raise system applied value.
本论文详细介绍了一种基于FPGA的视频转换接口的设计方案,这个接口主要功能是实现了对输入的NTSC制式的视频信号进行转换。接口电路使用ADV7181B芯片对视频信号进行解码处理,被解码的信号为ITU_R656标准8位数据信号。本系统使用FPGA作为开发平台,由I2C总线配置模块、解交织模块、缓存模块、色度空间转换模块和VGA时序转化模块组成。其中,缓存设计采用场内行插入法实现隔行扫描变换为逐行扫描,利用流水线技术对色度空间进行转换;在ADV7123芯片解码下,图像通过VGA控制模块在VGA显示器上得到显示。
本论文中的主控制器采用Verilog HDL作为硬件描述语言,系统在Quartus II 6.0, Modelsim SE 6.0软件平台下开发,采用FPGA可编程芯片,让整个系统拥有了较大的灵活性,不仅提高了数字接口的转换速度,而且还可以很方便的利用芯片的可配置性来完成系统的在线升级维护,提升了系统的应用价值。
With the rapid development of computer, multimedia and digital communication technology, on the one hand video technology is advanced and boosted, on the other attachment of interface appears many problem to be solved among different digital display equipment. But it was paid no enough attention to on the market, and it is seldom seen between different interfaces.
A solution of embeded Video Conversion Interface based on FPGA was introduced detailed in this paper, which had the function of video conversion for format NTSC. The analog video signals were converted to the 8 bit standard digital video signals according with ITU_R656 by video A/D processor ADV7181B. The system used Altera Corporation’s FPGA as the development platform. It was composed of I2C configuration module, deinterlace module, image frame storing control module, color space conversion module and VGA timing configuration module. Among them, the cache design uses at the line insertion method for the realization of interlaced scanning transform progressive scanning. The color space conversion was used by pipeline technology, Digital video signals were sent to the image frame storages. After the color space conversion by FPGA, the system changed its schedule. The VGA controller module sent the video signals to the VGA, which made the video signals displayed by ADV7123.
Verilog HDL has been adopted in the design of the main controller in the paper. The system was developed under the platforms of Quartus II 6.0 and Modelsim SE 6.0 software. It was implemented in FPGA and made it flexible. The system can not only boost digital interface conversion velocity but also fulfill system upgraded online conveniently by chip of allocation, raise system applied value.
引文
[1]杨琳,张锟生,杨怀祥.彩色电视原理[M].南京:东南大学出版社,2001:29-46.
[2]马喜廷,孟荣芳.IP网络摄像机[J].电视技术,2003(5):83-85.
[3]张志芳.网络视频监控系统发展概况研究[J].计算机应用研究,2005(6):9-10.
[4] H.Y.LEE, J.KIM. A New Algorithm for Interlaced to Progressive Scan Conversion Based on Directional Correlations and its IC Design[J]. IEEE Trans on Consumer Electronics, Vol. 40, pp. 119-129, May 2004.
[5] FREDERIC D, FABRICE M. Motion Estimation Techniques for Digital TV: A Review and a New Contribution[J]. Processdings of the IEEE, 2005, 83(6): 85-87.
[6]泽德曼,赵宏图.基于FPGA&CPLD的数字IC设计方法[M].北京:北京航空航天大学出版社,2004(5):15-17.
[7]刘达、龚建荣.系统级可编程芯片(SOPC)设计思想与开发策略[J].现代电子技术.2002(11):1-4.
[8]潘松,黄继业.SOPC技术实用教程[M].北京:清华大学出版社,2005:6-9.
[9]杜惠敏,李宥谋,赵全良.基于Verilog的FPGA设计基础[M].西安:西安电子科技大学出版社,2006:18-20.
[10] RICARDO ZEBULUM, ADRIAN STOICA. Experiments on the Evolution of Digital to Analog Converters[J]. IEEE, 2001, 5(11): 2321-2331.
[11]褚振勇,翁木云.FPGA设计及应用[M].西安:西安电子科技大学出版社,2002:33-35.
[12]任爱峰,初秀琴,常存等.基于FPGA的嵌入式系统设计[M].成都:电子科技大学出版社,2004:15-18.
[13]王诚,吴继华,范丽珍等.Altera FPGA/CPLD设计(基础篇)[M].北京:人民邮电出版社,2005:2-10.
[14]刘达,龚建荣.可编程逻辑器件设计新思路[J].微电子技术,2003(3):23.
[15] YAO WANG, JORN OSTERMANN, YAQIN ZHANG. Video Processing andCommunications[M]. NJ Prentice Hall PTR, 2003: 95-96.
[16]吴继华,王诚.Altera FPGA/CPLD设计(高级篇)[M].人民邮电出版社,2005:123-125.
[17] Introduction to Quartus II, Ver.6.0, Altera, Jun.2006: 29-30.
[18]王道宪.CPLD/FPGA的可编程逻辑器件应用与开发[M].北京:国防工业出版社,2004:75-78.
[19] WOLF, WAYNE HENDRIX. FPGA-based system design[M]. Upper Saddle River, NJ Prentice Hall PTR, 2004: 11-17.
[20] Cyclone II Device Handbook(All Sections). Altera Corporation, Feb 2007: 34-35.
[21] DE2 Development and Education Board User Manual. Altera Corporation, 2005: 23-24.
[22]周恒,罗斯青.SOPC-基于FPGA的SOPC设计策略[J].山西电子技术,2003(1):6-9.
[23] KOPILOVIC I, SAUPE D, HAMZAOUI R. Progressive Fractal Coding Image Processing[C]. Proceedings 2001 International Conference, 2001, 10(1): 86-89.
[24]宋玉锋,周泓.程数字视频监控系统的设计与实现[J].计算机工程,2002(08):45-47.
[25] GONZALEZ R C, WOODS R E. Digital Image Processing[J]. Addision-Wesley, Reading, M.A, 2002: 125-155.
[26]何辅云,张海燕.电视原理与数字视频技术[M].合肥:合肥工业大学出版社,2003:30-34.
[27]裴昌幸,刘乃安,杜武林.电视原理与现代电视系统[M].西安:西安电子科技大学出版社,2006:34.
[28]俞斯乐.电视原理[M].北京:国防工业出版社,2006(6):157.
[29] Analog Device. ADV7181B DATA SHEET. 2003: 38-45, 59-60.
[30] R.S.PRODAN. Multidimensional Digital Signal Processing for Television Scan Conversion[J]. Philips 1. Res, Vol.41, No.6. 2003: 97-98.
[31] CHENG-HAN SUNG. Design and Implementation of A Scalable Fast Fourier Transform Core[J]. 0-7803-7363-4/02 IEEE, 2002: 16-19.
[32]张志刚.FPGA与SOPC设计教程-DE2实践[M].西安:西安电子科技大学出版社,2007:158-161.
[33] BOOTH, S.A. Digital TV in the United States[J]. Spectrum, IEEE, 2005(3/36):39-41.
[34]张亚平,贺占庄.基于FPGA的VGA显示模块设计[J].计算机技术与发展,2007(6):242-245.
[35] XESS Corporation. VGA Generator for the XSA Boards[J]. 2004-10-12.
[36] IC总线规范.广州周立功单片机发展有限公司.2005:35-46.
[37] SUNG-JEA, KOETAL. Digital Image Stabilizing Algorithms Based on Bit-Plane Matching[J]. IEEE Trans, on Consumer Electronics, 2004, 44(3): 617-622.
[38]路永坤.用Verilog HDL实现I2C总线功能[J].电子技术应用,2004,30(4):67-69.
[39]伞景辉,孙广富.SAA7111A中I2C总线控制器的FPGA实现[J].微处理机,2004(4):3-6.
[40]求是科技.单片机通信技术与工程实践[M].北京:人民邮电出版社,2005:251-272.
[41] UWE MEYER-BASES. Digital Signal Processing on FPGA[J]. University of Houston Libraries, 2003: 123-145.
[42]夏宇闻.Verilog数字系统设计教程[M].北京:北京航空航天大学出版社,2003:1-6.
[43] ENOCH HWANG. Build a VGA Monitor Controller[J]. CIRCUIT CELLAR, Issue 172, Nov 2004: 38-43.
[44]张文爱,张博,程永强.基于FPGA的高分辨率VGA显示控制器的设计[J].现代显示,2006(9):45-46.
[45]陈姚节,卢建华.基于FPGA的VGA显示接口的研究与设计[J].交通与计算机,2005(2):47-49.
[46]蔡肯,梁晓莹.VGA控制器IP核的FPGA实现[J].多媒体技术及其应用,2007:1691-1692.
[2]马喜廷,孟荣芳.IP网络摄像机[J].电视技术,2003(5):83-85.
[3]张志芳.网络视频监控系统发展概况研究[J].计算机应用研究,2005(6):9-10.
[4] H.Y.LEE, J.KIM. A New Algorithm for Interlaced to Progressive Scan Conversion Based on Directional Correlations and its IC Design[J]. IEEE Trans on Consumer Electronics, Vol. 40, pp. 119-129, May 2004.
[5] FREDERIC D, FABRICE M. Motion Estimation Techniques for Digital TV: A Review and a New Contribution[J]. Processdings of the IEEE, 2005, 83(6): 85-87.
[6]泽德曼,赵宏图.基于FPGA&CPLD的数字IC设计方法[M].北京:北京航空航天大学出版社,2004(5):15-17.
[7]刘达、龚建荣.系统级可编程芯片(SOPC)设计思想与开发策略[J].现代电子技术.2002(11):1-4.
[8]潘松,黄继业.SOPC技术实用教程[M].北京:清华大学出版社,2005:6-9.
[9]杜惠敏,李宥谋,赵全良.基于Verilog的FPGA设计基础[M].西安:西安电子科技大学出版社,2006:18-20.
[10] RICARDO ZEBULUM, ADRIAN STOICA. Experiments on the Evolution of Digital to Analog Converters[J]. IEEE, 2001, 5(11): 2321-2331.
[11]褚振勇,翁木云.FPGA设计及应用[M].西安:西安电子科技大学出版社,2002:33-35.
[12]任爱峰,初秀琴,常存等.基于FPGA的嵌入式系统设计[M].成都:电子科技大学出版社,2004:15-18.
[13]王诚,吴继华,范丽珍等.Altera FPGA/CPLD设计(基础篇)[M].北京:人民邮电出版社,2005:2-10.
[14]刘达,龚建荣.可编程逻辑器件设计新思路[J].微电子技术,2003(3):23.
[15] YAO WANG, JORN OSTERMANN, YAQIN ZHANG. Video Processing andCommunications[M]. NJ Prentice Hall PTR, 2003: 95-96.
[16]吴继华,王诚.Altera FPGA/CPLD设计(高级篇)[M].人民邮电出版社,2005:123-125.
[17] Introduction to Quartus II, Ver.6.0, Altera, Jun.2006: 29-30.
[18]王道宪.CPLD/FPGA的可编程逻辑器件应用与开发[M].北京:国防工业出版社,2004:75-78.
[19] WOLF, WAYNE HENDRIX. FPGA-based system design[M]. Upper Saddle River, NJ Prentice Hall PTR, 2004: 11-17.
[20] Cyclone II Device Handbook(All Sections). Altera Corporation, Feb 2007: 34-35.
[21] DE2 Development and Education Board User Manual. Altera Corporation, 2005: 23-24.
[22]周恒,罗斯青.SOPC-基于FPGA的SOPC设计策略[J].山西电子技术,2003(1):6-9.
[23] KOPILOVIC I, SAUPE D, HAMZAOUI R. Progressive Fractal Coding Image Processing[C]. Proceedings 2001 International Conference, 2001, 10(1): 86-89.
[24]宋玉锋,周泓.程数字视频监控系统的设计与实现[J].计算机工程,2002(08):45-47.
[25] GONZALEZ R C, WOODS R E. Digital Image Processing[J]. Addision-Wesley, Reading, M.A, 2002: 125-155.
[26]何辅云,张海燕.电视原理与数字视频技术[M].合肥:合肥工业大学出版社,2003:30-34.
[27]裴昌幸,刘乃安,杜武林.电视原理与现代电视系统[M].西安:西安电子科技大学出版社,2006:34.
[28]俞斯乐.电视原理[M].北京:国防工业出版社,2006(6):157.
[29] Analog Device. ADV7181B DATA SHEET. 2003: 38-45, 59-60.
[30] R.S.PRODAN. Multidimensional Digital Signal Processing for Television Scan Conversion[J]. Philips 1. Res, Vol.41, No.6. 2003: 97-98.
[31] CHENG-HAN SUNG. Design and Implementation of A Scalable Fast Fourier Transform Core[J]. 0-7803-7363-4/02 IEEE, 2002: 16-19.
[32]张志刚.FPGA与SOPC设计教程-DE2实践[M].西安:西安电子科技大学出版社,2007:158-161.
[33] BOOTH, S.A. Digital TV in the United States[J]. Spectrum, IEEE, 2005(3/36):39-41.
[34]张亚平,贺占庄.基于FPGA的VGA显示模块设计[J].计算机技术与发展,2007(6):242-245.
[35] XESS Corporation. VGA Generator for the XSA Boards[J]. 2004-10-12.
[36] IC总线规范.广州周立功单片机发展有限公司.2005:35-46.
[37] SUNG-JEA, KOETAL. Digital Image Stabilizing Algorithms Based on Bit-Plane Matching[J]. IEEE Trans, on Consumer Electronics, 2004, 44(3): 617-622.
[38]路永坤.用Verilog HDL实现I2C总线功能[J].电子技术应用,2004,30(4):67-69.
[39]伞景辉,孙广富.SAA7111A中I2C总线控制器的FPGA实现[J].微处理机,2004(4):3-6.
[40]求是科技.单片机通信技术与工程实践[M].北京:人民邮电出版社,2005:251-272.
[41] UWE MEYER-BASES. Digital Signal Processing on FPGA[J]. University of Houston Libraries, 2003: 123-145.
[42]夏宇闻.Verilog数字系统设计教程[M].北京:北京航空航天大学出版社,2003:1-6.
[43] ENOCH HWANG. Build a VGA Monitor Controller[J]. CIRCUIT CELLAR, Issue 172, Nov 2004: 38-43.
[44]张文爱,张博,程永强.基于FPGA的高分辨率VGA显示控制器的设计[J].现代显示,2006(9):45-46.
[45]陈姚节,卢建华.基于FPGA的VGA显示接口的研究与设计[J].交通与计算机,2005(2):47-49.
[46]蔡肯,梁晓莹.VGA控制器IP核的FPGA实现[J].多媒体技术及其应用,2007:1691-1692.