低功耗技术研究—体系结构和编译优化
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摘要
计算机系统的功耗问题是计算机技术进一步发展亟待解决的问题之一。功耗急剧增长提高了芯片的封装和制冷成本。高温环境下执行增加了芯片的失效率,导致计算机系统的可靠性下降。
嵌入式移动计算技术是芯片行业最活跃的领域,嵌入式的移动设备往往依靠电池供电,电池的供电时间是系统的重要参数之一。与半导体技术的发展速度相比电池技术的发展缓慢,未来的移动设备必须在有限能量供应下发挥更大的效能,对系统能量消耗有很高的要求。
信息行业的设备消耗了大量能量,并且能量消耗呈现逐年增长的趋势。大量的能量消耗要求系统采用有效的能量管理策略提高能量的使用效率。因此,不管是嵌入式移动设备还是高性能系统,都必须考虑功耗问题。
从底层的电路技术,到逻辑技术、体系结构技术和高层的软件技术,出现了各种方法用于降低计算机系统的能量消耗。本文重点研究用体系结构设计和编译器指导的方法减少计算机系统的能量消耗。体系结构是软件和硬件的接口,对于低层的低功耗硬件设计和上层的软件低功耗优化都有重要的影响,本文分析了传统体系结构的能量效率变化趋势,提出今后的体系结构低功耗设计的思路之一是采用并行处理技术。当前新的硬件技术—动态电压调节(DVS)和部件动态关闭(TOSU)—为软件低功耗优化提供了手段,本文的工作基于编译器的静态分析或者profile技术,获得应用对系统资源的使用特性,使用DVS或者TOSU技术减少计算机系统的能量消耗。具体说来,本文包括三部分的研究工作:首先研究了微处理器体系结构的能量有效性;然后研究了实时系统的能量有效性优化方法;最后研究了并行系统的能量有效性优化方法。本文的主要创新如下:
1、提出了微处理器的体系结构能量有效性模型,克服了传统的能量有效性模型受工艺参数和电压参数影响的问题,该模型能有效地评估体系结构设计对能量有效性的影响。通过对典型微处理器的分析,验证了该模型的合理性。通过该模型分析了体系结构设计的多种典型技术,得出了并行处理技术和部件使用局部化是提高能量有效性的主要方法。指导了本课题的研究。
2、提出了面向程序的剩余最差时间分析方法,克服了过去动态电压调节技术的研究结果不能紧密结合时间估计技术的问题,给出了动态电压调节算法实现的总体框架,建立了性能/功耗模拟环境RTLPower,嵌入式程序集的测试证明该算法最大能够节省50%的能量。
3、提出了等比例电压调节点的优化放置方法—OPOT和OPTO,OPOT给出了无开销情况下的最优调节点放置方法,并给出了证明,OPTO给出了存在开销情况下的调节点优化放置方法,嵌入式程序集的测试证明两种调节点优化放置方法有效的减少了能量消耗。
4、提出了确定执行模式的最优频率设置指导的贪婪电压调节方法和最高频率限制情况下确定执行模式的最优频率设置指导的贪婪电压调节方法,克服了过去电压调节方法不能有效利用松弛时间的问题,能够最佳地设置每阶段的频率,模拟实验结果验证了两种电压调节方法的有效性。
5、提出了编译器指导的DVS并行系统的能量和性能权衡技术,针对MPI消息传递应用使用编译器自动构造通信和计算区域,为这些区域分配最优的电压/频率,克服了过去的研究完全采用手工方法的问题,建立了性能/功耗的并行模拟环境MIPSpar,并行MPI程序集的测试证明该技术在性能损失不超过5%的情况下,能够节省20~40%的能量消耗。
6、提出了编译器指导的并行系统通信链路的动态关闭技术,编译器将并行程序划分为通信区间和计算区间,使用链路打开/关闭指令动态改变通信链路的状态,克服了基于网络链路利用率的预测方式不可避免地引入的链路打开/关闭开销,模拟实验结果表明在小于1%的网络延迟和性能损失下,减少了20~70%的互连网络能量消耗。
Power consumption has become an obstruction in the road to higher-performance computer systems. First of all, the continuing growth of power consumption has increased the packaging and cooling cost. In addition, the higher temperature accentuates a large number of failure mechanisms in integrated circuits (ICs) and causes frequent failure of computer systems.
Embedded systems for mobile computing are developing rapidly, and a crucial parameter of mobile systems is the continued time of energy supply. Although the performance in ICs has been increasing rapidly in recent years, battery techniques are developed slowly. So it is of significant importance for battery-powered mobile systems to use more effective low-power techniques.
The energy consumption by the facilities from IT industry has been steadily growing year by year and large quantities of energy consumption necessitate power management to improve energy efficiency. So it is very imperative not only for mobile systems but also for high-performance systems to develop effective low-power techniques.
Quantities of novel low-power techniques at different levels including circuit, logic, architecture and software levels, in order of increasing abstraction, have been proposed to reduce energy consumption. This thesis aims at reducing energy consumption by architecture design and compiler optimization. First of all, the architecture is the interface between software and hardware, and significantly affects low power hardware design and software-directed power management. So energy efficiency of microprocessor architecture is investigated, and parallel processing is analyzed as an energy-efficient architecture technique. Secondly, new hardware techniques such as dynamic voltage scaling (DVS) and turning off unused system units (TOSU) have come forward, and are widely used by the software-directed work in the thesis. In sum, the thesis consists of three parts: the first is to investigate energy efficiency of microprocessor architecture; the second is to present some methods of energy optimization in real-time systems; the last is to give some methods of energy optimization in parallel systems. The main contributions of the thesis are as follows:
1. A model on energy efficiency of microprocessor architecture is proposed. Since it eliminates the influence of technology and voltage, the model can be used to evaluate energy efficiency of different architecture designs. The analytical results of typical microprocessors show the model is a reasonable metric of energy efficiency. By model analyses of multiple architecture techniques, the results show that parallel processing and localizing the use of system units are primary solutions improving energy efficiency.
2. A dynamic voltage scaling method integrated with estimation of the reduced worst-case execution time is proposed in detail. Compared with the past work, dynamic voltage scaling and WCET (worst-case execution time) analysis combine to a united frame, and a simulation environment named RTLPower is the realization result. The simulation results from embedded applications show the new dynamic voltage scaling method can obtain energy reduction of up to 50% over no power management.
3. Two optimizing placement methods of dynamic voltage scaling points, OPOT and OPTO, are proposed. OPOT is declared as an optimal placement method without time overhead and is proved, OPTO is an optimizing placement method. The simulation results from embedded applications show two methods reduce energy consumption effectively.
4. Two real-time voltage adjustment schemes are proposed. One is a voltage adjustment scheme directed by the optimal frequency configuration of fixed execution pattern, and the other further considers the maximum frequency of system. Compared with the past voltage schemes, the new schemes can make use of the slack time more efficiently. The simulation results from synthetic applications show the new schemes can obtain the largest energy reduction.
5. Compiler-directed energy-time tradeoff on DVS-enabled parallel systems is proposed. Compared with the past work, the new method has used compiler techniques to automatically form communication regions and computation regions, and the optimal frequency and voltage are assigned to each region by solving a 0-1 integer-programming problem. A performance/power parallel simulation environment, MIPSpar, is established, and the simulation results from MPI benchmark applications show that the method can save 20~40% energy consumption with less than 5% performance degradation.
6. A technique of compiler-directed power-aware on/off network links is proposed. Compared with the past history-based work, the new technique has used compiler techniques to automatically divide MPI applications into communication intervals and computation intervals, and avoided time overhead of state switching. The simulation results from MPI applications show that the proposed compiler-directed method can reduce energy consumption of interconnection networks by 20~70%, at a loss of less than 1% network latency and performance degradation.
嵌入式移动计算技术是芯片行业最活跃的领域,嵌入式的移动设备往往依靠电池供电,电池的供电时间是系统的重要参数之一。与半导体技术的发展速度相比电池技术的发展缓慢,未来的移动设备必须在有限能量供应下发挥更大的效能,对系统能量消耗有很高的要求。
信息行业的设备消耗了大量能量,并且能量消耗呈现逐年增长的趋势。大量的能量消耗要求系统采用有效的能量管理策略提高能量的使用效率。因此,不管是嵌入式移动设备还是高性能系统,都必须考虑功耗问题。
从底层的电路技术,到逻辑技术、体系结构技术和高层的软件技术,出现了各种方法用于降低计算机系统的能量消耗。本文重点研究用体系结构设计和编译器指导的方法减少计算机系统的能量消耗。体系结构是软件和硬件的接口,对于低层的低功耗硬件设计和上层的软件低功耗优化都有重要的影响,本文分析了传统体系结构的能量效率变化趋势,提出今后的体系结构低功耗设计的思路之一是采用并行处理技术。当前新的硬件技术—动态电压调节(DVS)和部件动态关闭(TOSU)—为软件低功耗优化提供了手段,本文的工作基于编译器的静态分析或者profile技术,获得应用对系统资源的使用特性,使用DVS或者TOSU技术减少计算机系统的能量消耗。具体说来,本文包括三部分的研究工作:首先研究了微处理器体系结构的能量有效性;然后研究了实时系统的能量有效性优化方法;最后研究了并行系统的能量有效性优化方法。本文的主要创新如下:
1、提出了微处理器的体系结构能量有效性模型,克服了传统的能量有效性模型受工艺参数和电压参数影响的问题,该模型能有效地评估体系结构设计对能量有效性的影响。通过对典型微处理器的分析,验证了该模型的合理性。通过该模型分析了体系结构设计的多种典型技术,得出了并行处理技术和部件使用局部化是提高能量有效性的主要方法。指导了本课题的研究。
2、提出了面向程序的剩余最差时间分析方法,克服了过去动态电压调节技术的研究结果不能紧密结合时间估计技术的问题,给出了动态电压调节算法实现的总体框架,建立了性能/功耗模拟环境RTLPower,嵌入式程序集的测试证明该算法最大能够节省50%的能量。
3、提出了等比例电压调节点的优化放置方法—OPOT和OPTO,OPOT给出了无开销情况下的最优调节点放置方法,并给出了证明,OPTO给出了存在开销情况下的调节点优化放置方法,嵌入式程序集的测试证明两种调节点优化放置方法有效的减少了能量消耗。
4、提出了确定执行模式的最优频率设置指导的贪婪电压调节方法和最高频率限制情况下确定执行模式的最优频率设置指导的贪婪电压调节方法,克服了过去电压调节方法不能有效利用松弛时间的问题,能够最佳地设置每阶段的频率,模拟实验结果验证了两种电压调节方法的有效性。
5、提出了编译器指导的DVS并行系统的能量和性能权衡技术,针对MPI消息传递应用使用编译器自动构造通信和计算区域,为这些区域分配最优的电压/频率,克服了过去的研究完全采用手工方法的问题,建立了性能/功耗的并行模拟环境MIPSpar,并行MPI程序集的测试证明该技术在性能损失不超过5%的情况下,能够节省20~40%的能量消耗。
6、提出了编译器指导的并行系统通信链路的动态关闭技术,编译器将并行程序划分为通信区间和计算区间,使用链路打开/关闭指令动态改变通信链路的状态,克服了基于网络链路利用率的预测方式不可避免地引入的链路打开/关闭开销,模拟实验结果表明在小于1%的网络延迟和性能损失下,减少了20~70%的互连网络能量消耗。
Power consumption has become an obstruction in the road to higher-performance computer systems. First of all, the continuing growth of power consumption has increased the packaging and cooling cost. In addition, the higher temperature accentuates a large number of failure mechanisms in integrated circuits (ICs) and causes frequent failure of computer systems.
Embedded systems for mobile computing are developing rapidly, and a crucial parameter of mobile systems is the continued time of energy supply. Although the performance in ICs has been increasing rapidly in recent years, battery techniques are developed slowly. So it is of significant importance for battery-powered mobile systems to use more effective low-power techniques.
The energy consumption by the facilities from IT industry has been steadily growing year by year and large quantities of energy consumption necessitate power management to improve energy efficiency. So it is very imperative not only for mobile systems but also for high-performance systems to develop effective low-power techniques.
Quantities of novel low-power techniques at different levels including circuit, logic, architecture and software levels, in order of increasing abstraction, have been proposed to reduce energy consumption. This thesis aims at reducing energy consumption by architecture design and compiler optimization. First of all, the architecture is the interface between software and hardware, and significantly affects low power hardware design and software-directed power management. So energy efficiency of microprocessor architecture is investigated, and parallel processing is analyzed as an energy-efficient architecture technique. Secondly, new hardware techniques such as dynamic voltage scaling (DVS) and turning off unused system units (TOSU) have come forward, and are widely used by the software-directed work in the thesis. In sum, the thesis consists of three parts: the first is to investigate energy efficiency of microprocessor architecture; the second is to present some methods of energy optimization in real-time systems; the last is to give some methods of energy optimization in parallel systems. The main contributions of the thesis are as follows:
1. A model on energy efficiency of microprocessor architecture is proposed. Since it eliminates the influence of technology and voltage, the model can be used to evaluate energy efficiency of different architecture designs. The analytical results of typical microprocessors show the model is a reasonable metric of energy efficiency. By model analyses of multiple architecture techniques, the results show that parallel processing and localizing the use of system units are primary solutions improving energy efficiency.
2. A dynamic voltage scaling method integrated with estimation of the reduced worst-case execution time is proposed in detail. Compared with the past work, dynamic voltage scaling and WCET (worst-case execution time) analysis combine to a united frame, and a simulation environment named RTLPower is the realization result. The simulation results from embedded applications show the new dynamic voltage scaling method can obtain energy reduction of up to 50% over no power management.
3. Two optimizing placement methods of dynamic voltage scaling points, OPOT and OPTO, are proposed. OPOT is declared as an optimal placement method without time overhead and is proved, OPTO is an optimizing placement method. The simulation results from embedded applications show two methods reduce energy consumption effectively.
4. Two real-time voltage adjustment schemes are proposed. One is a voltage adjustment scheme directed by the optimal frequency configuration of fixed execution pattern, and the other further considers the maximum frequency of system. Compared with the past voltage schemes, the new schemes can make use of the slack time more efficiently. The simulation results from synthetic applications show the new schemes can obtain the largest energy reduction.
5. Compiler-directed energy-time tradeoff on DVS-enabled parallel systems is proposed. Compared with the past work, the new method has used compiler techniques to automatically form communication regions and computation regions, and the optimal frequency and voltage are assigned to each region by solving a 0-1 integer-programming problem. A performance/power parallel simulation environment, MIPSpar, is established, and the simulation results from MPI benchmark applications show that the method can save 20~40% energy consumption with less than 5% performance degradation.
6. A technique of compiler-directed power-aware on/off network links is proposed. Compared with the past history-based work, the new technique has used compiler techniques to automatically divide MPI applications into communication intervals and computation intervals, and avoided time overhead of state switching. The simulation results from MPI applications show that the proposed compiler-directed method can reduce energy consumption of interconnection networks by 20~70%, at a loss of less than 1% network latency and performance degradation.
引文
[1] 拉贝, 钱德拉卡山, 尼科利奇. 数字集成电路 - 设计透视(第2版). 北京: 清华大学出版社, 2004. 761
[2] Itrs . International Technology Roadmap for Semiconductors, 2005 Edition:Tech Report. ITRS, May 2006, download from http://public.itrs.net.
[3] Mudge T. Power: A First Class Design Constraint for Future Architectures. In Proc. of the 7th International Conference on High Performance Computing (HiPC 2000), 2000. Bangalore, India: Springer, 2000. 215～224
[4] 新闻观察. 英特尔承认遭遇芯片发热技术壁垒. 新浪科技, 2004年05月18日
[5] Hsu C., Feng W. A Power-Aware Run-Time System for High-Performance Computing. In Proc. of the ACM/IEEE SC'2005 Conference on High Performance Networking and Computing, March 2005. Seattle, WA, USA: IEEE CS, 2005
[6] Ge R., Feng X., Cameron K. W. Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters. In Proc. of the 2005 ACM/IEEE conference on Supercomputing, March 2005. Seattle, WA, USA: IEEE CS, 2005
[7] Kawamoto K., Koomey J. H. G., Dman B. N., et al. Electricity Used by Office Equipment and Network Equipment in the U.S.: Detailed Report and Appendices:Tech Report. Lawrence Berkeley National Lab, Berkeley CA, Feb, 2001. 50
[8] Lahiri K., Dey S., Panigrahi D., et al. Battery-Driven System Design: A New Frontier in Low Power Design. In Proc. of the ASPDAC 2002 / VLSI Design 2002, 2002. Bangalore, India: IEEE CS, 2002
[9] Feng X., Ge R., Cameron K. W. Power and Energy Profiling of Scientific Applications on Distributed Systems. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE Computer Society, 2005
[10] Lorch J. R. A Complete Picture of the Energy Consumption of a Portable Computer: Masters Thesis. Computer Science, University of California at Berkeley, December 1995
[11] Tiwari V., Singh D., Rajgopal S., et al. Reducing Power in High-performance Microprocessors. In Proc. of the 35th annual conference on Design automation, 1998. San Francisco, CA USA: ACM Press, New York, NY, USA, 1998. 732～737
[12] Gowan M. K., Biro L. L., Jackson D. B. Power Considerations in the Design of the Alpha 21264 Microprocessor. In Proc. of the 35th annual conference on Design automation, 1998. San Francisco, California, United States: ACM Press New York, NY, USA, 1998. 726～731
[13] Unsal O. S., Ashok R., Koren I., et al. Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors. ACM Transactions on Embedded Computing Systems (TECS), Special issue on power-aware embedded computing, 2003, 2(3): 373～392
[14] Psilogeorgopoulos M., Munteanu M., Chuang T., et al. Contemporary Techniques for Lower Power Circuit Design, PREST Deliverable D2.1:Tech Report. D2.1. The University of Sheffield, 1998.
[15] Borkar S. Low power design challenges for the decade (invited talk). In Proc. of the 2001 conference on Asia South Pacific design automation, 2001. Yokohama, Japan: ACM Press, New York, NY, USA, 2001. 293～296
[16] Chandrakasan A. P., Brodersen R. W. Minimizing power consumption in digital CMOS circuits. Proc. IEEE, 1995, 83: 498～523
[17] Thompson S., Packan P., Bohr M. MOS Scaling: Transistor Challenges for the 21st Century. Intel Technology Journal, 1998, Q3
[18] Jung S., Kim K., Kang S. Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages. In Proc. of the 39th conference on Design automation, 2002. New Orleans, Louisiana, USA: ACM Press, New York, NY, USA, 2002. 467～472
[19] Amelifard B., Fallah F., Pedram M. Low-Power Fanout Optimization Using Multiple Threshold Voltage Inverters. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM, 2005. 95～98
[20] Calhoun B. H., Chandrakasan A. Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits. In Proc. of International Symposium on Low Power Electronics and Design 2004, August 9-11, 2004. Newport Beach, California, USA: ACM, 2004. 90～95
[21] Donno M., Ivaldi A., Benini L., et al. Clock-Tree Power Optimization based on RTL Clock-Gating. In Proc. of the 40th conference on Design automation, June 2-6, 2003. Anaheim, California, USA: ACM Press, New York, NY, USA, 2003. 622～627
[22] Heydari P., Pedram M. Interconnect Energy Dissipation in High-Speed ULSI Circuits. In Proc. of ASP-DAC/VLSI Design 2002, Jan, 2002. Bangalore, India: IEEE, 2002. 132～140
[23] Kapur P., Chandra G., Saraswat K. C. Power Estimation in Global Interconnects and its Reduction Using a Novel Repeater Optimization Methodology. In Proc. of the 39th conference on Design automation, June, 2002. New Orleans, Louisiana, USA: ACM Press, New York, NY, USA, 2002. 461～466
[24] Wason V., Banerjee K. A Probabilistic Framework for Power-Optimal Repeater Insertion in Global Interconnects under Parameter Variations. In Proc. of the 2005 international symposium on Low power electronics and design, August 8-10, 2005. San Diego, California, USA: ACM Press, New York, NY, USA, 2005. 131～136
[25] Kim N. S., Austin T., Blaauw D., et al. Leakage Current: Moore's Law Meets Static Power. IEEE Computer, 2003, 36(12): 65～77
[26] Kim N. S., Blaauw D., Mudge T. Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. In Proc. of 2003 International Conference on Computer-Aided Design (ICCAD'03), November 11-13, 2003. San Jose, California, USA: IEEE Computer Society / ACM, 2003. 627～632
[27] Ananthan H., Kim C. H., Roy K. Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS. In Proc. of the 2004 international symposium onLow power electronics and design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, New York, NY, USA, 2004. 8～13
[28] Rao R. M., Burns J. L., Devgan A. Efficient Techniques for Gate Leakage Estimation. In Proc. of the 2003 international symposium on Low power electronics and design, August 25-27, 2003. Seoul, Korea: ACM Press, New York, NY, USA, 2003. 100～103
[29] Piguet C., Renaudin M., Omnes T. J. Special Session on Low-Power Systems on Chips (SOCs). In Proc. of Design, Automation, and Test in Europe (DATE '01), February 2004. Paris, France: IEEE Computer Society, 2001
[30] Powell M. D., Schuchman E., Vijaykumar T. N. Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. In Proc. of the 38th annual IEEE/ACM International Symposium on Microarchitecture, November 12-16, 2005. Barcelona, Spain: IEEE CS, 2005. 294～304
[31] Ku J. C., Ozdemir S., Memik G., et al. Thermal Management of On-Chip Caches Through Power Density Minimization. In Proc. of the 38th annual IEEE/ACM International Symposium on Microarchitecture, November 12-16, 2005. IEEE CS, 2005. 283～293
[32] Gandhi K. R., Mahapatra N. R. A Detailed Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. In Proc. of Second Annual Workshop on Duplicating, Deconstructing and Debunking, June 8, 2003. San Diego, California, 2003
[33] Tang W., Gupta R., Nicolau A. Power Savings in Embedded Processors through Decode Filter Cache. In Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March, 2002. Paris, France: IEEE CS, 2002. 443～448
[34] Zhang C., Yang J., Vahid F. Low Static-Power Frequent-Value Data Caches. In Proc. of 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Feb. 16-20, 2004. Paris, France: IEEE CS, 2004. 214～219
[35] Hu J. S., Vijaykrishnan N., Kim S., et al. Scheduling Reusable Instructions for Power Reduction. In Proc. of the conference on Design, automation and test in Europe - Volume 1, Feb. 16-20, 2004. Paris, France: IEEE CS, 2004. 148～155
[36] Yang J., Gupta R. Energy Efficient Frequent Value Data Cache Design. In Proc. of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 197～207
[37] Brooks D., Martonosi M. Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. In Proc. of the 5th International Symposium on High Performance Computer Architecture(HPCA'99), 9-12 January, 1999. Orlando, FL, USA: IEEE CS, 1999. 13
[38] Pokam G., Rochecouste O., Andr′eSeznec, et al. Speculative Software Management of Datapath-width for Energy Optimization. In Proc. of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, June 11-13, 2004. Washington, DC, USA: ACM Press, New York, NY, USA, 2004. 78～87
[39] Macii L. D. A. E. M. Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. In Proc. of 2002 Design,Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March, 2002. Paris, France: IEEE CS, 2002. 449～450
[40] Zhang Y., Gupta R. Enabling Partial Cache Line Prefetching Through Data Compression. In Proc. of 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October, 2003. Kaohsiung, Taiwan: IEEE CS, 2003. 277～285
[41] Ekman M., Stenstrom P. A Robust Main-Memory Compression Scheme. In Proc. of 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005. Madison, Wisconsin, USA: IEEE CS, 2005. 74～85
[42] Canal R., AntonioGonzález, Smith J. E. Very Low Power Pipelines using Significance Compression. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 10-13 December 2000. Monterey, California, USA: ACM Press, 2000. 181～190
[43] Suresh D. C., Agrawal B., Yang J., et al. Power Efficient Encoding Techniques for Off-chip Data. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30, 2003. San Jose, California, USA: ACM Press, 2003. 267～275
[44] Gupta J. R. C. Z. Frequent Value Encoding for Low Power Data Buses. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2004, 9(3): 354～384
[45] Cheng W., Pedram M. Low Power Techniques for Address Encoding and Memory Allocation. In Proc. of the 2001 conference on Asia South Pacific design automation, January 30, 2001. Yokohama, Japan: ACM Press, 2001. 245～250
[46] Zhang C., Vahid F. A Power-Configurable Bus for Embedded Systems. In Proc. of IEEE International Symposium on Circuits and Systems, May 2002. Scottsdale: IEEE CS, 2002. 809～812
[47] Basu K., Choudhary A., Pisharath J., et al. Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM Press, 2002. 345～355
[48] Li H., Bhunia S., Chen Y., et al. Deterministic Clock Gating for Microprocessor Power Reduction. In Proc. of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), February 8-12, 2003. Anaheim, California, USA: IEEE CS, 2003. 113
[49] Wu Q., Pedram M., Wu X. Clock-Gating and Its Application to Low Power Design of Sequential Circuits. IEEE Trans on Circuits and Systems I: Fundamental Theory and Applications, 2000, 47(3): 415～420
[50] Emnett F., Biegel M. Power Reduction Through RTL Clock Gating:Tech Report. SNUG. Automotive Integrated Electronics Corporation, 2000. 11
[51] Luo Y., Yu J., Yang J., et al. Low Power Network Processor Design Using Clock Gating. In Proc. of the 42nd Design Automation Conference, DAC 2005, June 13-17, 2005. Anaheim, California, USA: ACM Press, 2005. 712～715
[52] Macii A., Macii E., Poncino M. Improving the Efficiency of Memory Partitioning by Address Clustering. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003),, 3-7 March 2003.Munich, Germany: IEEE CS, 2003. 10018～10023
[53] Zyuban V. V. INHERENTLY LOWER-POWER HIGH-PERFORMANCE SUPERSCALAR ARCHITECTURES: Department of Computer Science and Engineering, Notre Dame, Indiana, March 2000
[54] Tseng J. H., KrsteAsanovi ′ c. Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. In Proc. of 30th International Symposium on Computer Architecture (ISCA-30), 9-11 June 2003. San Diego, CA: IEEE CS, 2003. 62～71
[55] Ashok R., Chheda S., Moritz C. A. Cool-Mem: Combining Statically Speculative Memory Accessing with Selective Address Translation for Energy Efficiency. In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002. San Jose, California: ACM Press, 2002. 133～143
[56] Kucuk G., Ghose K., Ponomarev D. V., et al. Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, August, 2001. Huntington Beach, California, USA: ACM Press, 2001. 237～242
[57] Delaluz V., Kandemir M., Vijaykrishnan N., et al. DRAM Energy Management Using Software and Hardware Directed Power Mode Control. In Proc. of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 20-24 January 2001. Nuevo Leone, Mexico: IEEE CS, 2001. 159～170
[58] Balasubramonian R., Dwarkadas S., Albonesi D. H. Reducing the Complexity of the Register File in Dynamic Superscalar Processors. In Proc. of the 34th Annual International Symposium on Microarchitecture, December 1-5, 2001. Austin, Texas, USA: ACM/IEEE, 2001. 237～248
[59] Park I., Powell M. D., Vijaykumar T. N. Reducing Register Ports for Higher Speed and Lower Energy. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 171～182
[60] Zhang C., Vahid F., Najjar W. A Highly Configurable Cache Architecture for Embedded Systems. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 136～146
[61] Wang H., Peh L., Malik S. Power-driven Design of Router Microarchitectures in On-chip Networks. In Proc. of the 36th Annual International Symposium on Microarchitecture, December 3-5, 2003. San Diego, CA, USA: ACM/IEEE, 2003. 105～116
[62] Pisharath J., Choudhary A., Kandemir M. Reducing Energy Consumption of Queries in Memory-Resident Database Systems. In Proc. of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 22 - 25, 2004. Washington DC, USA: ACM Press, 2004. 35～45
[63] Albonesi D. H. Selective Cache Ways: On-Demand Cache Resource Allocation. In Proc. of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 16-18 November, 1999. Haifa, Israel: ACM/IEEE, 1999. 248-
[64] Witchel E., KrsteAsanovi′c. The Span Cache: Software Controlled Tag Checks and Cache Line Size. In Proc. of Workshop on Complexity-Effective Design ,28th ISCA, July, 2001. Gotenborg, Sweeden: IEEE CS, 2001. 1～12
[65] Witchel E., Larsen S., Ananian C. S., et al. Direct Addressed Caches for Reduced Power Consumption. In Proc. of 34th Annual International Symposium on Microarchitecture ,MICRO-34, December 2001. Austin, Texas: ACM/IEEE, 2001. 124～133
[66] Albonesi D. H. Dynamic IPC/Clock Rate Optimization. In Proc. of the 25th annual international symposium on Computer architecture, 1998. Barcelona, Spain: IEEE CS, 1998. 282～292
[67] Ponomarev D., Kucuk G., Ghose K. DYNAMIC ALLOCATION OF DATAPATH RESOURCES FOR LOW POWER. In Proc. of Workshop on Complexity-Effective Design (WCED-01), held in conjunction with ISCA, June 2001. Goteborg, Sweden, 2001
[68] Dropshoy S., Buyuktosunogluz A., Balasubramoniany R., et al. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. In Proc. of 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002. Charlottesville, VA, USA: IEEE CS, 2002. 141
[69] Buyuktosunoglu A., Karkhanisy T., Albonesi D. H., et al. Energy Efficient Co-Adaptive Instruction Fetch and Issue. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 147～156
[70] Balasubramonian R., Albonesi D., Buyuktosunoglu A., et al. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 10-13 December 2000. Monterey, California, USA: ACM/IEEE, 2000. 245～257
[71] Hartenstein R. A Decade of Reconfigurable Computing: a Visionary Retrospective. In Proc. of the conference on Design, automation and test in Europe 2001, March 12-15, 2001. Munich, Germany: IEEE Press, 2001. 642～649
[72] Hauser J. R. Augmenting a Microprocessor with Reconfigurable Hardware: Ph.D Thesis. UNIVERSITY OF CALIFORNIA, BERKELEY, Fall 2000
[73] Sankaralingam K., Nagarajan R., Liu H., et al. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. In Proc. of the 30th Annual International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 422～433
[74] Mai K., Paaske T., Jayasena N., et al. Smart Memories: a modular reconfigurable architecture. In Proc. of the 27th annual international symposium on Computer architecture, June 2000. Vancouver, British Columbia, Canada: ACM Press, 2000. 161～171
[75] Schmit H., Whelihan D., Tsai A., et al. PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology. In Proc. of Custom Integrated Circuits Conference, 2002, May 12-15, 2002. Caribe Royale Resort Suites, Orlando, Florida, USA: IEEE Press, 2002. 63～66
[76] Taylor M. B., Lee W., Miller J., et al. Evaluation of the Raw Microprocessor:An Exposed-Wire-Delay Architecture for ILP and Streams. In Proc. of the 31st annual international symposium on Computer architecture (ISCA 2004), 19-23 June 2004. München, Germany: IEEE CS, 2004. 2～13
[77] Burd T. D., Pering T. A., Stratakos A. J., et al. A Dynamic Voltage Scaled Microprocessor System. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35(11): 1571～1580
[78] Hsu C. COMPILER-DIRECTED DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR CPU POWER AND ENERGY REDUCTION: Ph.D Thesis. New Brunswick Rutgers, The State University of New Jersey, October, 2003
[79] Fleischmann M. LongRun Power Management: Dynamic Power Management for Crusoe Processors:Tech Report. Transmeta Corporation, January 17, 2001.
[80] Paper I. W. Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor:Tech Report. Order Number: 301170-001. March 2004.
[81] Smith S. F. A MULTIPLE-CLOCK-DOMAIN BUS ARCHITECTURE USING ASYNCHRONOUS FIFOS AS ELASTIC ELEMENTS: Ph.D Thesis. College of Graduate Studies, University of Idaho, October 2003
[82] Semeraro G., Magklis G., Balasubramonian R., et al. Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In Proc. of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02), 2-6 February 2002. Boston, Massachusettes, USA: IEEE CS, 2002. 29～42
[83] Iyer A., Marculescu D. Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. In Proc. of 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002. Anchorage, AK, USA: IEEE CS, 2002. 158
[84] Oliver J., Rao R., Sultana P., et al. Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. In Proc. of 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004. Munich, Germany: IEEE CS, 2004. 150～161
[85] Magklis G., Scott M. L., Semeraro G., et al. Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 14～25
[86] Sasaki H., Kondo M., Nakamura H. Dynamic Instruction Cascading on GALS Microprocessors. In Proc. of Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, September 21-23, 2005. Leuven, Belgium: Springer, 2005. 30～39
[87] Semeraro G. P. Multiple Clock Domain Microarchitecture Design and Analysis: Ph.D Thesis. University of Rochester,
[88] Choi K., Soma R., Pedram M. Dynamic Voltage and Frequency Scaling based on Workload Decomposition. In Proc. of the 2004 international symposium on Low power electronics and design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, 2004. 174～179
[89] Kumar R., Farkas K. I., Jouppi N. P., et al. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In Proc. of the 36th International Symposium on Microarchitecture (MICRO-362003), December 3-5, 2003. San Diego, CA, USA: ACM/IEEE, 2003. 81～92
[90] Lin Y., Lee H., Woh M., et al. SODA: A Low-power Architecture For Software Radio. In Proc. of The 33rd Annual International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006. Boston, MA USA: ACM Press, 2006
[91] Weglarz E. F., Saluja K. K., Lipasti M. H. Minimizing Energy Consumption for High-Performance Processing. In Proc. of the 2002 conference on Asia South Pacific design automation/VLSI Design, 7-11 January 2002. Bangalore, India: IEEE CS, 2002. 199～206
[92] Kandemir M., Zhang W., Karakoy M. Runtime Code Parallelization for On-Chip Multiprocessors. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003. Munich, Germany: IEEE CS, 2003. 10510～10515
[93] Wall D. W. Limits of Instruction-Level Parallelism. In Proc. of Forth International Conference on Architectural Support for Programming Languages and Operating Systems, April 8-11, 1991. Santa Clara, California: ACM Press, 1991. 176～188
[94] 易会战, 杨学军. 嵌入式应用中指令级并行的动态特性. In Proc. of 2005中国计算机大会(CNCC'2005), 2005, 10. 武汉, 中国, 2005
[95] 易会战, 陈娟. 多核微处理器体系结构、编程模型和编译技术:技术报告. 国防科技大学软件所编译组, 2005年8月.
[96] Tendler J., Dodson J., Fields J. J. S., et al. POWER4 system microarchitecture. IBM Journal of Research and Development, 2002, 46(1): 5～25
[97] Eggers S. J., Emer J. S., Levy H. M., et al. SIMULTANEOUS MULTITHREADING: A Platform for Next-Generation Processors. IEEE Micro, 1997, 17(5): 12～19
[98] Sohi G. S., Roth A. Speculative Multithreaded Processors. IEEE Computer, 2001, 34(4): 66～73
[99] Asanovic K. Vector Processors (Appendix G). In: Computer Architecture: A Quantitative Approach, Third Edition. : Morgan Kaufman, 2002
[100] Kozyrakis C. E., Perissakis S., Patterson D., et al. Scalable Processors in the Billion-Transistor Era: IRAM. IEEE Computer, 1997, 30(9): 75～78
[101] Kozyrakis C. D. P. Overcoming the Limitations of Conventional Vector Processors. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 399～409
[102] Krashinsky R., Batten C., Hampton M., et al. The Vector-Thread Architecture. In Proc. of the 31st annual international symposium on Computer architecture (ISCA 2004), June 19-23, 2004. München, Germany: IEEE CS, 2004. 52
[103] Ahn J. H., Dally W. J., Khailany B., et al. Evaluating the Imagine Stream Architecture. In Proc. of the 31st Annual International Symposium on Computer Architecture, 19-23 June 2004. Munich, Germany: IEEE CS, 2004. 14～25
[104] Halter J. P., Najm F. N. A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits. In Proc. of IEEE Custom Integrated CircuitsConference, 1997. , 1997. 475～478
[105] Johnson M. C., Somasekhar D., Roy K. Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS. In Proc. of the 36th ACM/IEEE conference on Design automation, 1999. New Orleans, Louisiana, United States: ACM Press, 1999. 442～445
[106] Abdollahi A., Fallah F., Pedram M. Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. In Proc. of the 2002 international symposium on Low power electronics and design, 2002. Monterey, California, USA: ACM Press, 2002. 213～218
[107] Kuroda T., Fujita T., Mita S., et al. A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme. In Proc. of 4th International Workshop on Advanced LSI's, July 18-20, 1996. Korea, 1996. 150～158
[108] Dropsho S., Kursun V., Albonesi D. H., et al. Managing Static Leakage Energy in Microprocessor Functional Units. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 321～332
[109] Li L., Kadayif I., Tsai Y., et al. Leakage Energy Management in Cache Hierarchies. In Proc. of 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002. Charlottesville, VA, USA: IEEE CS, 2002. 131～140
[110] Hu Z., Buyuktosunoglu A., Srinivasan V., et al. Microarchitectural Techniques for Power Gating of Execution Units. In Proc. of the 2004 International Symposium on Low Power Electronics and Design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, 2004. 32～37
[111] Yang S., Powell M. D., Falsafi B., et al. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In Proc. of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 20-24 January 2001. Nuevo Leone, Mexico: IEEE CS, 2001. 147～158
[112] KrisztiánFlautner, Kim N. S., Martin S., et al. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In Proc. of 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002. Anchorage, AK, USA: IEEE CS, 2002. 148～157
[113] Kim N. S., KrisztiánFlautner, Blaauw D., et al. Drowsy Instruction: Caches Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 219～230
[114] Kim N. S., Flautner K., Blaauw D., et al. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12(2): 167～184
[115] Duarte D., Tsai Y., Vijaykrishnan N., et al. Evaluating Run-Time Techniques for Leakage Power Reduction. In Proc. of ASP-DAC/VLSI Design 2002, 7-11 January 2002. Bangalore, India: IEEE online, 2002. 31～38
[116] Vahdat A., Lebeck A., Ellis C. S. Every Joule is Precious: The Case for Revisiting Operating System Design for Energy Efficiency. In Proc. of the ACM SIGOPS European Workshop, September 17-20, 2000. Kolding, Denmark: ACM Press, 2000. 31～36
[117] Lorch J. R. Operating Systems Techniques for Reducing Processor Energy Consumption: PH.D Thesis. UNIVERSITY of CALIFORNIA, BERKELEY, Fall 2001
[118] Papathanasion A. E. On the Power Consumption of Computing Systems:Tech Report. Area Paper. University of Rochester, Rochester, NY, May 2001.
[119] Lu Y., Chung E., Simunic T., et al. Quantitative Comparison of Power Management Algorithms. In Proc. of Design Automation and Test In Europe 2000, 2000. Paris, France: ACM Press, 2000. 20～26
[120] Chedid W., Yu C. Survey on Power Management Techniques for Energy Efficient Computer Systems:Tech Report. Mobile Computing Research Lab, Cleveland State University, 2002. 1～18
[121] Benini L., Bogliolo A., Micheli G. de. A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8(3)
[122] Gurumurthi S., Sivasubramaniam A., Kandemir M., et al. DRPM: Dynamic Speed Control for Power Management in Server Class Disks. In Proc. of the 30th annual international symposium on Computer architecture, 2003. San Diego, California: ACM Press, 2003. 169～181
[123] Gurumurthi S., Zhang J., Sivasubramaniam A., et al. Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads. In Proc. of 2003 IEEE International Symposium on Performance Analysis of Systems and Software, March 6-8, 2003. Austin, Texas; USA: IEEE CS, 2003. 123～132
[124] Yu Y., Prasanna V. K. Energy-Balanced Task Allocation for Collaborative Processing in Networked Embedded Systems. In Proc. of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 11-13, 2003. San Diego, California, USA: ACM Press, 2003. 265～274
[125] Wang G., Irwin M. J., Berman P., et al. Optimizing Sensor Movement Planning for Energy Efficiency. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 215～220
[126] Dick R. P., Lakshminarayana G., Raghunathan A., et al. Power Analysis of Embedded Operating Systems. In Proc. of the 37th conference on Design automation, 2000. Los Angeles, California, United States: ACM Press, 2000. 312～315
[127] Chen G., Vijaykrishnan N., Kandemir M., et al. Tracking Object Life Cycle for Leakage Energy Optimization. In Proc. of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, October 1-3, 2003. Newport Beach, CA, USA: ACM, 2003. 213～218
[128] Zhong L., Jha N. K. Graphical User Interface Energy Characterization for Handheld Computers. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30- November 1, 2003. San Jose, California, USA: ACM Press, 2003. 232～242
[129] Zeng H., Ellis C. S., Lebeck A. R., et al. ECOSystem: Managing Energy as a First Class Operating System Resource. In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 5-9, 2002. San Jose, California: ACM Press, 2002. 123～132
[130] Zedlewski J., Sobti S., Garg N., et al. Modeling Hard-Disk Power Consumption. In Proc. of the FAST '03 Conference on File and Storage Technologies, March 31 - April 2, 2003. San Francisco, California, USA: USENIX, 2003
[131] Lu Y., Benini L., Micheli G. de. Low-Power Task Scheduling for Multiple Devices. In Proc. of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA: ACM Press, 2000. 39～43
[132] Marchal P., JoséIgnacioGómez, Pinuel L., et al. SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003. Munich, Germany: IEEE CS, 2003. 10516～10523
[133] Pouwelse J., Langendoen K., Sips H. Energy Priority Scheduling for Variable Voltage Processors. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, 2001. Huntington Beach, California, USA: ACM Press, 2001. 28～33
[134] Weiser W., Welch B., Demers A., et al. Scheduling for Reduced CPU Energy. In Proc. of the First USENIX Symposium on Operating Systems Design and Implementation (OSDI), November 14-17, 1994. Monterey, California: ACM Press, 1994. 13～23
[135] Weissel A., Bellosa F. Process Cruise Control Event-Driven Clock Scaling for Dynamic Power Management. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Grenoble, France, 2002. 238～246
[136] Lu Z., Hein J., Humphrey M., et al. Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Greenoble, France: ACM Press, 2002. 156～163
[137] Varma A., Ganesh B., Sen M., et al. A Control-Theoretic Approach to Dynamic Voltage Scheduling. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30 - November 1, 2003. San Jose, California, USA: ACM, 2003. 255～266
[138] Yan L., Zhong L., Jha N. K. User-perceived Latency Driven Voltage Scaling for Interactive Applications. In Proc. of the 42nd Design Automation Conference, DAC 2005, June 13-17, 2005. San Diego, CA, USA: ACM Press, 2005. 624～627
[139] Yang P., Wong C., Marchal P., et al. Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs. IEEE Design & Test of Computers, 2001, 18(5): 46～58
[140] Schmitz M. T., Al-hashimi B. M., Eles P. Energy-Efficient Mapping andScheduling for DVS Enabled Distributed Embedded Systems. In Proc. of 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 514～521
[141] Hewlett-packard , Intel , Microsoft , et al. Advanced Configuration and Power Interface Specification, Revision 3.0a:Tech Report. December 30, 2005.
[142] Amd . AMD PowerNow! Technology:Tech Report. AMD Corporation, 2002.
[143] Amd . Cool 'n' Quiet? Technology Installation Guide for AMD Athlon? 64 Processor Based Systems. NA Rev. 0.04:Tech Report. AMD Corporation, June 2004.
[144] Shin D., Kim J. Dynamic Voltage Scaling of Periodic and Aperiodic Tasks in Priority-Driven Systems. In Proc. of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, January 27-30, 2004. Yokohama, Japan: IEEE CS, 2004. 653～658
[145] Baynes K., Collins C., Fiterman E., et al. The Performance and Energy Consumption of Three Embedded Real-Time Operating Systems. In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 16-17, 2001. Atlanta, Georgia, USA: ACM Press, 2001. 203～210
[146] Jejurikar R., Gupta R. Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Greenoble, France: ACM Press, 2002. 164～169
[147] Aydin H., Melhem R., Mosse D., et al. Power-Aware Scheduling for Periodic Real-Time Tasks. IEEE TRANSACTIONS ON COMPUTERS, 2004, 53(5)
[148] Baynes K., Collins C., Fiterman E., et al. The Performance and Energy Consumption of Embedded Real-Time Operating Systems. IEEE TRANSACTIONS ON COMPUTERS, 2003, 52(11)
[149] Jejurikar R., Gupta R. Procrastination Scheduling in Fixed Priority Real-Time Systems. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 57～66
[150] Im C., Ha S. Dynamic Voltage Scaling for Real-Time Multi-task Scheduling Using Buffers. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 88～94
[151] Swaminathan V., Chakrabarty K. Investigating the Effect of Voltage-Switching on Low-Energy Task Scheduling in Hard Real-Time Systems. In Proc. of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001. Yokohama, Japan: ACM Press, 2001. 251
[152] Shin D., Kim W., Jeon J., et al. SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms. In Proc. of Power-Aware Computer Systems, Second International Workshop, PACS 2002, February 2, 2002. Cambridge, MA, USA: Springer, 2002. 141～156
[153] Aydin H., Yang Q. Energy-Aware Partitioning for Multiprocessor Real-Time Systems. In Proc. of 17th International Parallel and Distributed ProcessingSymposium (IPDPS 2003), 22-26 April 2003. Nice, France: IEEE CS, 2003. 113
[154] Zhu D. ENERGY AND RELIABILITY MANAGEMENT IN PARALLEL REAL-TIME SYSTEMS: Ph.D Thesis. University of Pittsburgh, 2004
[155] Mishra R., Rastogi N., Zhu D., et al. Energy Aware Scheduling for Distributed Real-Time Systems. In Proc. of 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003. Nice, France: IEEE CS, 2003. 21
[156] Langen P. de, Juurlink B. Leakage-Aware Multiprocessor Scheduling for Low Power. In Proc. of the 20th International Parallel and Distributed Processing Symposium, April 2006. Rhodos, Greece: IEEE CS, 2006. 1～8
[157] Shin D., Kim J. Power-Aware Scheduling of Conditional Task Graphs in Real-Time Multiprocessor Systems. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 408～413
[158] Chase J. S., Doyle R. P. Balance of Power: Energy Management for Server Clusters. In Proc. of the 8th Workshop on Hot Topics in Operating Systems (HotOS), May 20-23, 2001. Schloss Elmau, Germany: IEEE CS, 2001
[159] Pinheiro E., Bianchini R., Carrera E. V., et al. Dynamic cluster reconfiguration for power and performance. In: Compilers and operating systems for low power. : Kluwer Academic Publishers, 2003. 75～93
[160] Chase J. S., Anderson D. C., Thakar P. N., et al. Managing Energy and Server Resources in Hosting Centers. In Proc. of the eighteenth ACM symposium on Operating systems principles, 2001. Banff, Alberta, Canada: ACM Press, 2001. 103～116
[161] Bianchini R. Research Directions in Power and Energy Conservation for Clusters : Tech Report. DCS-TR-466. Department of Computer Science, Rutgers University, November 2001.
[162] Pinheiro E., Bianchini R. Energy Conservation Techniques for Disk Array-Based Servers. In Proc. of the 18th Annual International Conference on Supercomputing, ICS 2004, June 26 - July 01, 2004. Saint Malo, France: ACM Press, 2004. 68～78
[163] Heath T., Diniz B., Carrera E. V. Energy Conservation in Heterogeneous Server Clusters. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 186～195
[164] Pinheiro E., Bianchini R., Dubnicki C. Exploiting Redundancy to Conserve Energy in Storage Systems. In Proc. of the Joint International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), June 26-30, 2006. Saint Malo, France: ACM Press, 2006
[165] Elnozahy E. N. (., Kistler M., Rajamony R. Energy-Efficient Server Clusters. In Proc. of 2nd Workshop on Power-Aware Computing Systems, February 2002. Cambridge, MA, USA: Springer Verlag, 2002
[166] Lefurgy C., Rajamani K., Rawson F., et al. Energy Management for Commercial Servers. IEEE Computer, 2003, 36(12): 39～48
[167] Bianchini R., Rajamony R. Power and Energy Management for Server Systems. IEEE Computer, 2004, 37(11): 68～74
[168] Xu R., Zhu D., Rusu C., et al. Energy-Efficient Policies for Embedded Clusters. In Proc. of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), June 15-17, 2005. Chicago, Illinois, USA: ACM Press, 2005. 1～10
[169] Tsui C. C. A. M. D. Low Power Architecture Design and Compilation Techniques for High-Performance Processors. In Proc. of CompCon'94 Digest of Technical Papers, February 1994. , 1994. 489～498
[170] Tiwari V., Malik S., Wolfe A. Power Analysis of Embedded Software: A First Step towards Software Power Minimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, 2(4): 437～445
[171] Tiwari V., Malik S., Wolfe A. Compilation Techniques for Low Energy: An Overview. In Proc. of IEEE Symposium of Low Power Electronics, Oct. 1994. : IEEE CS, 1994. 38～39
[172] Lee M. T., Tiwari V., Malik S., et al. Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software. Fujitsu Scientific and Technical Journal, 1995, 31(3): 215～229
[173] Tiwari V., Malik S., Wolfe A., et al. Instruction Level Power Analysis and Optimization of Software. Journal of VLSI Signal Processing, 1996, 13(2/3): 223～238
[174] Toburen M., Conte T. M., Reilly M. Instruction Scheduling for Low Power Dissipation in High Performance Microprocessors. In Proc. of the Power-Driven Microarchitecture Workshop, 1998, June 1998. Barcelona, Spain, 1998
[175] Chang J., Pedram M. Register Allocation and Binding for Low Power. In Proc. of the 32nd ACM/IEEE conference on Design automation, June 1995. San Francisco, CA: ACM Press, 1995. 29～35
[176] Mehta H., Owens R. M., Irwin M. J., et al. Techniques for Low Energy Software. In Proc. of the 1997 International Symposium on Low Power Electronics and Design, August 18-20, 1997. Monterey, California, USA: ACM Press, 1997. 72～75
[177] gebotys C. H. Low Energy Memory and Register Allocation Using Network Flow. In Proc. of the 34st Conference on Design Automation, June 9-13, 1997. Anaheim, California, USA: ACM Press, 1997. 435～440
[178] Zhang Y., Hu X., Chen D. Z. Global Register Allocation for Minimizing Energy Consumption. In Proc. of the 1999 International Symposium on Low Power Electronics and Design, 1999, August 16-17, 1999. San Diego, California, USA: ACM, 1999. 100～102
[179] Steinke S., RüdigerSchwarz, Wehmeyer L., et al. Low power code generation for a RISC processor by register pipelining:Tech Report. No. 754. University of Dortmund, Dept. of CS XII, 2001, 2001.
[180] Anand R., Jacome M. F., Veciana G. de. Heuristic Tradeoffs Between Latency and Energy Consumption in Register Assignment. In Proc. of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, May 2000. San Diego, California, USA: ACM Press, 2000. 115～119
[181] Valluri M., John L. Is Compiling for Performance = = Compiling for Power? In Proc. of the 5th Annual Workshop on Interaction between Compilers andComputer Architectures INTERACT-5, Jan. 2001. Monterey, Mexico, 2001
[182] Kandemir M. T., Vijaykrishnan N., Irwin M. J., et al. Influence of Compiler Optimizations on System Power. In Proc. of the 37th Conference on Design Automation, June 2000. Los Angeles, CA, USA: ACM Press, 2000. 304～307
[183] Yang H., Gao G. R., Marquez A., et al. Power and Energy Impact by Loop Transformation. In Proc. of Workshop on Compilers and Operating Systems for Low Power (COLP01), Sept 2001. Barcelona, SPAIN, 2000
[184] Seng J. S., Tullsen D. M. The Effect of Compiler Optimization on Pentium 4 Power Consumption. In Proc. of the Seventh Workshop on Interaction between Compilers and Computer Architectures, Feb. 2003. Anaheim, CA, USA: IEEE CS, 2003. 51～56
[185] LakshmiNChakrapani;PinarKorkmaz, Iii V. J. M., Palem K. V., et al. The Emerging Power Crisis in Embedded Processors: What can a(poor) Compiler do? In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 2001. Atlanta, Georgia, USA: ACM Press, 2001. 176～180
[186] Kandemir M. T., Vijaykrishnan N., Irwin M. J., et al. Towards Energy-Aware Iteration Space Tiling. In Proc. of Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, June 18, 2000. Vancouver, BC, Canada: Springer, 2000. 211～215
[187] Kim H. S., Irwin M. J., Vijaykrishnan N., et al. Effect of Compiler Optimizations on Memory Energy. In Proc. of IEEE Workshop on Signal Processing Systems, October 2000. : IEEE CS, 2000. 663--672
[188] Zambreno J., Kandemir M. T., Choudhary A. N. Enhancing Compiler Techniques for Memory Energy Optimizations. In Proc. of Embedded Software, Second International Conference, EMSOFT 2002, October 7-9, 2002. Grenoble, France: Springer, 2002. 364～381
[189] Guo Y., Chheda S., Koren I., et al. Energy-Aware Data Prefetching for General-Purpose Programs. In Proc. of Power-Aware Computer Systems(PACS'04), Micro-37, December 5th, 2004. Portland, OR: Springer, 2004
[190] Zhu Y., Magklis G., Scott M. L., et al. The Energy Impact of Aggressive Loop Fusion. In Proc. of 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004. Antibes Juan-les-Pins, France: IEEE CS, 2004. 153～164
[191] Mosse D., Aydin H., Childers B., et al. Compiler-Assisted Dynamic Power-Aware Scheduling for Real-Time Applications. In Proc. of Workshop on Compilers and Operating Systems for Low-Power (COLP 2000), Oct. 2000. Philadelphia, PA, 2000
[192] Lee S., Sakurai T. Run-Time Voltage Hopping for Low-Power Real-Time Systems. In Proc. of the 37th Conference on Design Automation, June 5-9, 2000. Los Angeles, CA, USA: ACM Press, 2000. 806～809
[193] Shin D., Kim J., Lee S. Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications. IEEE Design & Test of Computers, 2001a, 18(2): 20～30
[194] Shin D., Kim J., Lee S. Low-Energy Intra-Task Voltage Scheduling UsingStatic Timing Analysis. In Proc. of the 38th Design Automation Conference, DAC 2001, June 18-22, 2001. Las Vegas, NV, USA: ACM Press, 2001b. 438～443
[195] Saputra H., Kandemir M. T., Vijaykrishnan N., et al. Energy-Conscious Compilation Based on Voltage Scaling. In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), June 2002. Berlin, Germany: ACM Press, 2002. 2～11
[196] Gruian F. Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS Processors. In Proc. of the International Symposium on Low-Power Electronics and Design ISLPED'01, Aug. 2001. Huntington Beach, CA: ACM Press, 2001. 46～51
[197] Azevedo A., Issenin I., Cornea R. R. G., et al. Profile-based Dynamic Voltage Scheduling Using Program Checkpoints. In Proc. of 2002 Design,Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 168～175
[198] Shin D., Kim J. A Profile-Based Energy-Efficient Intra-Task Voltage Scheduling Algorithm for Hard Real-Time Applications. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, August 2001. Huntington Beach, California, USA: ACM Press, 2001. 271～274
[199] Aboughazaleh N., DanielMossé, Childers B. R., et al. Collaborative Operating System and Compiler Power Management for Real-Time Applications. In Proc. of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), May 27-30, 2003. Toronto, Canada: IEEE CS, 2003. 133
[200] Aboughazaleh N., Childers B. R., DanielMossé, et al. Energy management for real-time embedded applications with compiler support. In Proc. of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 2003. San Diego, CA: ACM Press, 2003. 284～293
[201] Gheorghita S. V., Basten T., Corporaal H. Intra-task Scenario-aware Voltage Scheduling. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24-27, 2005. San Francisco, California, USA: ACM Press, 2005. 177～184
[202] Liu C., Sivasubramaniam A., Kandemir M., et al. Exploiting Barriers to Optimize Power Consumption of CMPs. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[203] Xie F., Martonosi M., Malik S. Compile-Time Dynamic Voltage Scaling Settings: Opportunities and Limits. In Proc. of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, June 9-11, 2003. San Diego, California, USA: ACM Press, 2003. 49～62
[204] Hsu C., Kremer U. The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction. In Proc. of ACM SIGPLAN 2003 conference on Programming language design and implementation, June 2003. San Diego, California, USA: ACM Press, 2003. 38～48
[205] Huang M., Renau J., Torrellas J. Profile-Based Energy Reduction for High-Performance Processors. In Proc. of Fourth Workshop on FeedbackDirected and Dynamic Optimization (FDDO), 2001, December 2, 2001. Austin Texas, 2001
[206] Huang M. C., Renau J., Torrellas J. Positional Adaptation of Processors: Application to Energy Reduction. In Proc. of 30th Annual International Symposium on Computer Architecture (ISCA), 2003, June 2003. San Diego, California: IEEE CS, 2003. 110～121
[207] Ghiasi S., Casmira J., Grunwald D. IPC Matching Mechanisms Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption. In Proc. of 2000 Workshop on Complexity Effective Design, in conjunction with the 27th International Symposium on Computer Architecture (ISCA 27), June 10, 2000. Vancouver, B.C., 2000
[208] Rele S., Pande S., Onder S., et al. Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. In Proc. of International Conference on Compiler Construction (CC), 2002, April 2002. Grenoble, France: Springer Verlag, 2002. 261～275
[209] Zhang W., Kandemir M. T., Vijaykrishnan N., et al. Compiler Support for Reducing Leakage Energy Consumption. In Proc. of 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003. Munich, Germany: IEEE CS, 2003. 11146～11147
[210] Zhang W., Vijaykrishnan N., Kandemir M. T., et al. Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction. In Proc. of The 34th Annual International Symposium on Microarchitecture (MICRO-34), December 1-5, 2001. Austin, Texas, USA: ACM/IEEE, 2001. 102～113
[211] Kim H. S., Vijaykrishnan N., Kandemir M. T., et al. Adapting Instruction Level Parallelism for Optimizing Leakage in VLIW Architectures. In Proc. of Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 11-13, 2003. San Diego, California, USA: ACM Press, 2003. 275～283
[212] Unsal O. S., Koren I., Krishna C. M., et al. Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling. ACM Computer Architecture Letters, 2002, 1-
[213] Azevedo A., Issenin I., Cornea R., et al. Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project. In Proc. of the Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01), Jan 2001. : IEEE CS, 2001
[214] JoséLAyala, Veidenbaum A. V., MarisaLuisaLópez-vallejo. Power-Aware Compilation for Register File Energy Reduction. International Journal of Parallel Programming, 2003, 31(6): 451～467
[215] Bellas N., Hajj I., Polychronopoulos C. D., et al. Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(3): 317～326
[216] Kim S. W., Eigenmann R. Compiler Techniques for Energy Saving in Instruction Caches of Speculative Parallel Microarchitectures. In Proc. of the 2000 International Conference on Parallel Processing, 21-24 August 2000. Toronto, Canada: IEEE CS, 2000. 77-
[217] Chen G., Kandemir M. T., Vijaykrishnan N., et al. Adaptive Garbage Collection for Battery-Operated Environments. In Proc. of The 2nd USENIXJava Virtual Machine Research and Technology Symposium (JVM'02), August 1-2, 2002. San Francisco, CA, USA: USENIX, 2002. 1～12
[218] Zhang W., Hu J. S., Degalahal V., et al. Compiler-Directed Instruction Cache Leakage Optimization. In Proc. of the 35th Annual International Symposium on Microarchitecture (MICRO-35), November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 208～218
[219] Hu J. S., Kandemir M. T., Vijaykrishnan N., et al. Compiler-Directed Cache Polymorphism. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), June 19-21, 2002. Berlin , Germany: ACM Press, 2002. 165～174
[220] Zhang W., Karakoy M., Kandemir M. T., et al. A Compiler Approach for Reducing Data Cache Energy. In Proc. of 17th Annual ACM International Conference on Supercomputing (ICS'03), June 23-26, 2003. San Francisco, CA, USA: ACM Press, 2003. 76～85
[221] Zhang W. Compiler-Directed Data Cache Leakage Reduction. In Proc. of IEEE Computer Society Symposium on VLSI (ISVLSI04), 19-20 February 2004. Lafayette, LA, USA: IEEE CS, 2004. 305～306
[222] Hu J. S., Nadgir A., Vijaykrishnan N., et al. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 402～407
[223] Delaluz V., Kandemir M. T., Vijaykrishnan N., et al. Energy-Oriented Compiler Optimizations for Partitioned Memory Architectures. In Proc. of International Conference on Compilers, Architectures, and Synthesis for Embedded Systems CASES'00, November 2000. San Jose, CA: ACM Press, 2000. 138～147
[224] Kandemir M. T., Sezer U., Delaluz V. Improving Memory Energy Using Access Pattern Classification. In Proc. of the International Conference on Computer Aided Design (ICCAD'01), November 4-8, 2001. San Jose, CA, USA: ACM Press, 2001. 201～206
[225] Delaluz V., Kandemir M. T., Vijaykrishnan N., et al. Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. In Proc. of ASP-DAC/VLSI Design 2002, 7-11 January 2002. Bangalore, India: IEEE CS, 2002. 288-
[226] Luz V. de La, Kandemir M. T., Kolcu I. Automatic data migration for reducing energy consumption in multi-bank memory systems. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 213～218
[227] Palem K. V., Rabbah R. M., Mooney V. J., et al. space optimization of embedded memory systems via data remapping. In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), 19-21 June 2002. Berlin, Germany: ACM Press, 2002. 28～37
[228] Kim H. S., Vijaykrishnan N., Kandemir M. T., et al. Estimating Influence of Data Layout Optimizations on SDRAM Energy Consumption. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, August25-27, 2003. Seoul, Korea: ACM Press, 2003. 40～43
[229] Cooper K. D., Xu L. Memory Redundancy Elimination to Improve Application Energy Efficiency. In Proc. of Languages and Compilers for Parallel Computing, 16th International Workshop, LCPC 2003, October 2-4, 2003. College Station, TX, USA: Springer, 2003. 288～305
[230] Yang H. Power-Aware Compilation Techniques for High Performance Processors: Ph.D Thesis. University of Delaware, 2004
[231] Papathanasiou A. E., Scott M. L. Energy Efficient Prefetching and Caching. In Proc. of the USENIX 2004 Annual Technical Conference (USENIX'04), June 27-July 2, 2004. Boston Marriott Copley Place, Boston, MA, USA: USENIX, 2004. 255～268
[232] Heath T., Pinheiro E., Hom J., et al. Code Transformations for Energy-Efficient Device Management. IEEE Transactions on Computers, 2004, 53(8): 974～987
[233] Hom J., Kremer U. Inter-program Compilation for Disk Energy Reduction. In Proc. of Workshop on Power-Aware Computer Systems (PACS'03), December 2003. San Diego, CA: Springer, 2003. 1～14
[234] Son S. W., Chen G., Kandemir M. A Compiler-Guided Approach for Reducing Disk Power Consumption by Exploiting Disk Access Locality. In Proc. of the International Symposium on Code Generation and Optimization, 2006, March 26-29, 2006. Manhattan, New York, NY: IEEE CS, 2006. 256～268
[235] Son S. W., Kandemir M. T., Choudhary A. N. Software-Directed Disk Power Management for Scientific Applications. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[236] Kandemir M. T., Son S. W., Chen G. An evaluation of code and data optimizations in the context of disk power reduction. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 209～214
[237] Son S. W., Chen G., Kandemir M. T. Power-aware code scheduling for clusters of active disks. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 293～298
[238] Son S. W., Chen G., Kandemir M. T., et al. Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 174～185
[239] Hom J., Kremer U. Energy Management of Virtual Memory on Diskless Devices. In Proc. of the Workshop on Compilers and Operating Systems(COLP'01), September 2001. Barcelona, Spain: Kluwer Academic Publishers, 2001. 95～113
[240] Chen G., Chen G., Kandemir M. T., et al. Compiler-Based Code Partitioning for Intelligent Embedded Disk Processing. In Proc. of Languages and Compilers for Parallel Computing, 16th International Workshop, LCPC 2003, October 2-4, 2003. College Station, TX, USA: Springer, 2003. 451～465
[241] Kremer U., Hicks J., Rehg J. M. Compiler-Directed Remote Task Execution for Power Management. In Proc. of Workshop on Compilers and OperatingSystems for Low Power (COLP'00), October 2000. Philadelphia, Pennsylvania, USA: IEEE CS, 2000
[242] Li Z., Wang C., Xu R. Computation offloading to save energy on handheld devices: a partition scheme. In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 16-17, 2001. Atlanta, Georgia, USA: ACM Press, 2001. 238～246
[243] Palm J., Lee H., Diwan A., et al. When to use a compilation service? In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), 19-21 June 2002. Berlin, Germany: ACM Press, 2002. 194～203
[244] Olsen C. M., Morrow L. A. Multi-processor Computer System Having Low Power Consumption. In Proc. of Power-Aware Computer Systems, Second International Workshop, PACS 2002, February 2, 2002. Cambridge, MA, USA: Springer, 2002. 53～67
[245] Kadayif I., Kandemir M. T., Karakoy M. An Energy Saving Strategy Based on Adaptive Loop Parallelization. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 195～200
[246] Freeh V. W., Pan F., Kappiah N., et al. Exploring the Energy-Time Tradeoff in MPI Programs on a Power-Scalable Cluster. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[247] Pan F., Freeh V. W., Smith D. M. Exploring the Energy-Time Tradeoff in High-Performance Computing. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[248] Freeh V. W., Lowenthal D. K. Using Multiple Energy Gears in MPI Programs on a Power-Scalable Cluster. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 164～173
[249] Springer R., Lowenthal D. K., Rountree B., et al. Minimizing Execution Time in MPI Programs on an Energy-Constrained, Power-Scalable Cluster. In Proc. of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 2006, March 29-31, 2006. New York, USA: ACM Press, 2006. 230～238
[250] Kappiah N., Freeh V. W., Lowenthal D. K. Just In Time Dynamic Voltage Scaling: Exploiting Inter-Node Slack to Save Energy in MPI Programs. In Proc. of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing (SC'05), November 12-18, 2005. Seattle, WA, USA: IEEE CS, 2005. 33
[251] Unnikrishnan P., Chen G., Kandemir M. T., et al. Dynamic compilation for energy adaptation. In Proc. of the 2002 IEEE/ACM International Conference on Computer-aided Design, November 10-14, 2002. San Jose, California, USA: ACM Press, 2002. 158～163
[252] Son S. W., Chen G., Kandemir M., et al. Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications. In Proc. of the 18thWorkshop on Languages and Compilers for Parallel Computing (LCPC'05), October 2005. Hawthorne, New York: Springer, 2005
[253] Wu Q., Reddi V. J., Wu Y., et al. A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. In Proc. of 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005. Barcelona, Spain: IEEE CS, 2005. 271～282
[254] Landman P. E. High-Level Power Estimation. In Proc. of the 1996 International Symposium on Low Power Electronics and Design, August 12-14, 1996. Monterey, California, USA: IEEE CS, 1996. 29～35
[255] Kim N. S., Austin T., Mudge T., et al. Challenges for Architectural Level Power Modeling. In: Power aware computing. Norwell, MA, USA: Kluwer Academic Publishers, 2002. 317～337
[256] Cai G., Lim C. H. Architectural level power/performance optimization and dynamic power estimation. In Proc. of CoolChips Tutorial colocated with MICRO32, November 16-18, 1999. Haifa, Israel, 1999
[257] Dhodapkar A., Lim C., Cai G., et al. TEM2P2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator. In Proc. of the First International Workshop on Power-Aware Computer Systems, 2000, Cambridge, MA: Springer-Verlag, 2000. 112～125
[258] Liao W., He L. Power Modeling and Reduction of VLIW Processors. In Proc. of Workshop on Compilers and Operating Systems for Low Power(COLP'01) , PACT'01, September 9th, 2001. Barcelona, Spain, 2001
[259] Vijaykrishnan N., Kandemir M. T., Irwin M. J., et al. Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower. In Proc. of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, June 10-14, 2000. Vancouver, BC, Canada: IEEE CS, 2000. 95～106
[260] Brooks D., Tiwari V., Martonosi M. Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In Proc. of 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000. Vancouver, BC, Canada: IEEE CS, 2000. 83～94
[261] Ponomarev D., Kucuk G., Ghose K. AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. In Proc. of 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 124～131
[262] Project T. S. P. M. Sim-Panalyzer2.0_Reference Manual : Tech Report. University of Michigan, the University of Colorado, 2004.
[263] Shivakumar P., Jouppi N. P. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model:Tech Report. WRL-2001-2. DEC Corporation, 2001.
[264] Zhang Y., Parikh D., Sankaranarayanan K., et al. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects:Tech Report. CS-2003-05. Department of Computer Science, University of Virginia, 2003.
[265] Skadron K., Stan M. R., Huang W., et al. Temperature-Aware Microarchitecture. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 2～13
[266] Wang H., Zhu X., Peh L., et al. Orion: A Power-Performance Simulator forInterconnection Networks. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 294～305
[267] Gurumurthi S., Sivasubramaniam A., Irwin M. J., et al. Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. In Proc. of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2-6 February 2002. Boston, Massachusettes, USA: IEEE CS, 2002. 141～150
[268] Chen J., Dubois M., Stenstrm P. Integrating Complete-System and User-level Performance/Power Simulators: The SimWattch Approach. In Proc. of 2003 IEEE International Symposium on Performance Analysis of Systems and Software(ISPASS-2003), March 6-8, 2003. Austin, Texas, USA: IEEE CS, 2003. 1～10
[269] Contreras G., Martonosi M., Peng J., et al. XTREM: A Power Simulator for the Intel XScaler Core. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 115～125
[270] 王永文. 高性能微处理器体系结构级功耗估算与优化技术研究: 博士论文. 国防科学技术大学研究生院, 二○○四年十月
[271] Minh D. Q., Bengtsson L., Larsson-edefors P. DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. In Proc. of The 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), February 10-13, 2003. Innsbruck, Austria: IASTED/ACTA Press, 2003. 767～772
[272] Kirkpatrick M. G., Freeh V. W., Kogge P. M., et al. Exploiting Morphable Microarchitectures for Saving Energy:Tech Report. 0109. Department of Computer Science and Engineering, University of Notre Dame, August 22, 2001.
[273] Asanovic K. Energy-Exposed Instruction Set Architectures. In Proc. of Work in Progress Session, HPCA-6, January 2000. Toulouse, France, 2000
[274] Horowitz M., Indermaur T., Gonzalez R. Low-power digital design. In Proc. of the IEEE Symposium on Low Power Electronics, October 1994. , 1994. 8～11
[275] Gonzalez R., Horowitz M. Energy dissipation In general purpose microprocessors. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31(9)
[276] Martin A. J. Towards an energy complexity of computation. Information Processing Letters, 2001, 77(2-4): 181～187
[277] Campbell M. Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. In Proc. of Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, June 1998. Montreal, Canada: Springer, 1998. 261
[278] Hartstein A., Puzak T. R. Optimum Power/Performance Pipeline Depth. In Proc. of the 36th International Symposium on Microarchitecture (MICRO-36 2003), December 3-5, 2003. San Diego, CA, USA: IEEE CS, 2003. 117～128
[279] Srinivasan V., Brooks D., Gschwind M., et al. Optimizing Pipelines for Power and Performance. In Proc. of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey:IEEE CS, 2002. 333～344
[280] Heo S., Asanovic K. Power-Optimal Pipelining in Deep Submicron Technology. In Proc. of the 2004 International Symposium on Low Power Electronics and Design, August 9–11, 2004. Newport Beach, CA: ACM Press, 2004. 218～223
[281] Posti M. A., Greene D. A., Tyson G. S., et al. The Limits of Instruction Level Parallelism in SPEC95 Applications. Special issue on Interact-3 workshop, ACM SIGARCH Computer Architecture News, 1999, 27(1): 31～34
[282] Espasa R., Valero M. Exploiting instruction-level and data-level parallelism. IEEE MICRO (Special Issue on Computing with a Billion Transistors), 1997, 17(5): 20～27
[283] Tian X. Exploiting thread-level and instruction-level parallelism for Hyper-Threading technology. Intel Developer Update Magazine, 2003,: 1
[284] Adiga N. R., GeorgeAlmási, Almasi G. S., et al. An Overview of the BlueGene/L Supercomputer. In Proc. of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA: ACM Press, 2002. 1～22
[285] Warren M. S., Weigle E. H., Feng W. High-Density Computing: A 240-Processor Beowulf in one Cubic Meter. In Proc. of the 2002 ACM/IEEE conference on Supercomputing, November 16-22, 2002. Baltimore, Maryland, USA: ACM Press, 2002. 1～11
[286] Geer D. Industry Trends: Chip Makers Turn to Multicore Processors. IEEE Computer, 2005, 38(5): 11～13
[287] Krewell K. Best Servers of 2004: Where Multicore is the Norm:Tech Report. Microprocessor Report (Online), Jan 18, 2005.
[288] Kapasi U. J., Rixner S., Dally W. J., et al. Programmable Stream Processors. IEEE Computer, 2003, 36(8): 54～62
[289] Kozyrakis C. Scalable Vector Media-processors for Embedded Systems: Ph.D Thesis. University of California at Berkeley, Spring 2002
[290] Hwang K., Xu Z., Arakawa M. Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing. IEEE Transaction on Parallel and Distributed Systems, 1996, 7(5): 522～536
[291] Bailey D. H., Barszcz E., Barton J. T., et al. The NAS parallel benchmarks - summary and preliminary results. In Proc. of Supercomputing '91, November 18-22, 1991. Albuquerque, NM, USA: IEEE CS, 1991. 158～165
[292] Swaminathan V., Chakrabarty K., Iyengar S. S. Dynamic I/O power management for hard real-time systems. In Proc. of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, 2001. Copenhagen, Denmark: ACM Press, 2001. 237～242
[293] Benini L., Micheli G. de. System-level power optimization: techniques and tools. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2000, 5(2): 115～192
[294] Hsu C., Kremer U. Compiler-Directed dynamic voltage scaling based on program regions:Tech Report. DCSTR-461. Rutgers University, November 2001. 1～9
[295] Casmira J., Grunwald D. Dynamic instruction scheduling slack. In Proc. of the 2000 KoolChips Workshop, Held in Conjunction with MICRO-00, 10-13December 2000. Monterey, California, USA, 2000. 1～7
[296] Hu J., Marculescu R. Energy- and Performance-Aware Mapping for Regular NoC Architectures. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24(4): 551～562
[297] burd T. D., brodersen R. W. Design Issues for Dynamic Voltage Scaling. In Proc. of the 2000 international symposium on low power electronics and design, July 25-27, 2000. Rapallo, Italy: ACM Press, 2000. 9～14
[298] Puschner P., Burns A. A Review of Worst-Case Execution-Time Analysis (Editorial). Journal of Real-Time Systems, 1999, 18(2/3): 115～128
[299] Mueller F. Static Cache Simulation and its Applications: Ph.D Thesis. Dept. of Computer Science, Florida State University, July 12, 1994
[300] Colin A., Puaut I. Worst Case Execution Time Analysis for a Processor with Branch Prediction. Real-Time System, 2000, 18(2/3): 249～274
[301] 刘喆. 基于WCET分析的低功耗技术研究: 硕士论文. 国防科学技术大学研究生院, 二○○五年十一月
[302] Zhu D., Melhem R., Childers B. R. Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multiprocessor Real-Time Systems. IEEE Transactions on Parallel and Distributed Systems, 2003, 14(7): 686～700
[303] Snu . SNU Real-Time Benchmarks:Seoul National University, 2004 Get from http://archi.snu.ac.kr/realtime/benchmark/.
[304] Shin D., Kim J. Look-ahead Intra-Task Voltage Scheduling Using Data Flow Information. In Proc. of the International SOC Design Conference (ISOCC'04), October 25-26. Seoul, Korea, 2004. 148～151
[305] Aboughazaleh N., Mosse D., Childers B., et al. Toward the placement of power management points in real-time applications. In: Compilers and Operating Systems for Low Power. : Kluwer Academic Publishers, 2002. 1～17
[306] Ball T., Larus J. R. Using paths to measure, explain, and enhance program behavior. IEEE Computer, 2000, 33(7): 57～65
[307] Stallman R. M. Using the GNU Compiler Collection, GCC Version 4.0.2:GCC Developer Community, 2005.
[308] Zhu D., Mosse D., Melhem R. Power Aware Scheduling for AND/OR Graphs in Real-Time Systems. IEEE Trans. On Parallel and Distributed Systems, 2004, 15(9): 849～864
[309] Ishihara T., Yasuura H. Voltage Scheduling Problem for Dynamically Variable Voltage Processors. In Proc. of the 1998 international symposium on Low power electronics and design, 1998. Monterey, California, USA: ACM Press, New York, NY, 1998. 197～202
[310] Wakabayashi M., Amano H. Environment for Multiprocessor Simulator Development. In Proc. of Fifth International Symposium on Parallel Architectures, Algorithms, and Networks, Dec 2000. Dallas/Richardson, TX, USA: IEEE CS, 2000. 64～71
[311] Radhakrishnan R., Pankratz J. Introducing DDR2 Memory in Eighth-Generation Dell PowerEdge Servers for Improved Performance:Dell Power Solutions, October 2004.
[312] Inc V. InfiniBand: The Next Step in High Performance Computing:Voltaire Inc,February 2003.
[313] Thakur R., Rabenseifner R., Gropp W. Optimization of Collective Communication Operations in MPICH. International Journal of High Performance Computing Applications, 2005, 19(2): 119～128
[314] Miller S. Implementing Optimized Collective Communication Routines on the IBM BlueGene/L Supercomputer:Tech Report. CS425. Iowa State University, Spring 2005.
[315] Kielmann T., Hofman R. F. H., Bal H. E., et al. MagPIe: MPI's Collective Communication Operations for Clustered Wide Area Systems. In Proc. of the 1999 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'99), 4-6 May 1999. Atlanta, Georgia: ACM Press, 1999. 131～140
[316] Thies W., Karczmarek M., Amarasinghe S. P. StreamIt: A Language for Streaming Applications. In Proc. of Compiler Construction, 11th International Conference, CC 2002, April 8-12, 2002. Grenoble, France: Springer, 2002. 179～196
[317] Saavedra-barrera R. H. Machine Characterization and Benchmark Performance Prediction:Tech Report. UCB/CSD-88-437. University of California, Berkeley, June 30, 1988.
[318] Bailey D. H., Barszcz E., Barton J. T., et al. The NAS Parallel Benchmarks. International Journal of Supercomputer Applications and High Performance Computing, 1991, 5(3): 63～73
[319] Mukherjee S. S., Bannon P., Lang S., et al. The Alpha 21364 network architecture. IEEE Micro, 2002, 22(1): 26～35
[320] Steinmacher-burow B. The Blue Gene/L Supercomputer:[presentation]. IBM Boblingen, DESYHamburg, Feb 21, 2005.
[321] Svensson C., Caputa P. High-bandwidth low-latency global interconnect. VLSI Circuits and Systems, Proceedings of the SPIE, 2003, 5117: 126～134
[322] Chen X., Peh L., Wei G., et al. Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. In Proc. of 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005. San Francisco, CA, USA: IEEE CS, 2005. 120～131
[323] Ye T. T., Micheli G. de, Benini L. Analysis of power consumption on switch fabrics in network routers. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 524～529
[324] Kim E. J., Link G. M., Yum K. H., et al. A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Transactions on Computers, 2005, 54(6): 660～671
[325] Kim E. J., Yum K. H., Link G. M., et al. Energy optimization techniques in cluster interconnects. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, 2003, August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 459～464
[326] Shang L., Peh L., Jha N. K. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In Proc. of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), February8-12, 2003. Anaheim, California, USA: IEEE CS, 2003. 91～102
[327] Shin D., Kim J. Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links. In Proc. of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, September 8-10, 2004. Stockholm, Sweden: ACM Press, 2004. 170～175
[328] Soteriou V., Eisley N., Peh L. Software-directed power-aware interconnection networks. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24-27, 2005. San Francisco, California, USA: ACM Press, 2005. 274～285
[329] Soteriou V., Peh L. Design-Space Exploration of Power-Aware On/Off Interconnection Networks. In Proc. of 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004. San Jose, CA, USA: IEEE CS, 2004. 510～517
[330] Chen G., Li F., Kandemir M. T. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2006, January 11-13, 2006. Charleston, South Carolina, USA: ACM Press, 2006. 194～205
[331] Li F., Chen G., Kandemir M., et al. Compiler-Directed Proactive Power Management for Networks. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24–27, 2005. San Francisco, California, USA: ACM Press, 2005. 137～146
[332] Jurczyk M. Interconnection Networks for Parallel Computers. In: Webster J. G., ed. Wiley Encyclopedia of Electrical and Electronics Engineering. New York: John Wiley & Sons, Inc., 1999. 555～564
[333] Ni L. M., Mckinley P. K. A Survey of Wormhole Routing Techniques in Direct Networks. IEEE Computer, 1993, 26(2): 62～76
[334] JoséDuato. A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks. IEEE Transactions on Parallel and Distributed Systems, 1995, 6(10): 1055～1067
[335] Puente V., Jos é AGregorio, Ram ó nBeivide, et al. On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 2003, 14(5): 487～501
[336] Kim J., Horowitz M. A. Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In Proc. of International Solid-State Circuits Conference, 2002, Feb. 2002. San Francisco, CA: IEEE CS, 2002. 216～480
[337] Wei G., Kim J., Liu D., et al. A variable-frequency parallel I/O interface with adaptive power-supply regulation. Journal of Solid-State Circuits, 2000, 35(11): 1600–1610
[338] Duarte D. E., Vijaykrishnan N., Irwin M. J. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10(6): 844～855
[339] 阿霍, 塞西, 厄尔曼. 编译原理技术与工具. 北京: 人民邮电出版社, 2002.1～796
[340] Peh L. FLOW CONTROL AND MICRO-ARCHITECTURAL MECHANISMS FOR EXTENDING THE PERFORMANCE OF INTERCONNECTION NETWORKS: Ph.D Thesis. STANFORD UNIVERSITY, August 2001
[2] Itrs . International Technology Roadmap for Semiconductors, 2005 Edition:Tech Report. ITRS, May 2006, download from http://public.itrs.net.
[3] Mudge T. Power: A First Class Design Constraint for Future Architectures. In Proc. of the 7th International Conference on High Performance Computing (HiPC 2000), 2000. Bangalore, India: Springer, 2000. 215～224
[4] 新闻观察. 英特尔承认遭遇芯片发热技术壁垒. 新浪科技, 2004年05月18日
[5] Hsu C., Feng W. A Power-Aware Run-Time System for High-Performance Computing. In Proc. of the ACM/IEEE SC'2005 Conference on High Performance Networking and Computing, March 2005. Seattle, WA, USA: IEEE CS, 2005
[6] Ge R., Feng X., Cameron K. W. Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters. In Proc. of the 2005 ACM/IEEE conference on Supercomputing, March 2005. Seattle, WA, USA: IEEE CS, 2005
[7] Kawamoto K., Koomey J. H. G., Dman B. N., et al. Electricity Used by Office Equipment and Network Equipment in the U.S.: Detailed Report and Appendices:Tech Report. Lawrence Berkeley National Lab, Berkeley CA, Feb, 2001. 50
[8] Lahiri K., Dey S., Panigrahi D., et al. Battery-Driven System Design: A New Frontier in Low Power Design. In Proc. of the ASPDAC 2002 / VLSI Design 2002, 2002. Bangalore, India: IEEE CS, 2002
[9] Feng X., Ge R., Cameron K. W. Power and Energy Profiling of Scientific Applications on Distributed Systems. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE Computer Society, 2005
[10] Lorch J. R. A Complete Picture of the Energy Consumption of a Portable Computer: Masters Thesis. Computer Science, University of California at Berkeley, December 1995
[11] Tiwari V., Singh D., Rajgopal S., et al. Reducing Power in High-performance Microprocessors. In Proc. of the 35th annual conference on Design automation, 1998. San Francisco, CA USA: ACM Press, New York, NY, USA, 1998. 732～737
[12] Gowan M. K., Biro L. L., Jackson D. B. Power Considerations in the Design of the Alpha 21264 Microprocessor. In Proc. of the 35th annual conference on Design automation, 1998. San Francisco, California, United States: ACM Press New York, NY, USA, 1998. 726～731
[13] Unsal O. S., Ashok R., Koren I., et al. Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors. ACM Transactions on Embedded Computing Systems (TECS), Special issue on power-aware embedded computing, 2003, 2(3): 373～392
[14] Psilogeorgopoulos M., Munteanu M., Chuang T., et al. Contemporary Techniques for Lower Power Circuit Design, PREST Deliverable D2.1:Tech Report. D2.1. The University of Sheffield, 1998.
[15] Borkar S. Low power design challenges for the decade (invited talk). In Proc. of the 2001 conference on Asia South Pacific design automation, 2001. Yokohama, Japan: ACM Press, New York, NY, USA, 2001. 293～296
[16] Chandrakasan A. P., Brodersen R. W. Minimizing power consumption in digital CMOS circuits. Proc. IEEE, 1995, 83: 498～523
[17] Thompson S., Packan P., Bohr M. MOS Scaling: Transistor Challenges for the 21st Century. Intel Technology Journal, 1998, Q3
[18] Jung S., Kim K., Kang S. Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages. In Proc. of the 39th conference on Design automation, 2002. New Orleans, Louisiana, USA: ACM Press, New York, NY, USA, 2002. 467～472
[19] Amelifard B., Fallah F., Pedram M. Low-Power Fanout Optimization Using Multiple Threshold Voltage Inverters. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM, 2005. 95～98
[20] Calhoun B. H., Chandrakasan A. Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits. In Proc. of International Symposium on Low Power Electronics and Design 2004, August 9-11, 2004. Newport Beach, California, USA: ACM, 2004. 90～95
[21] Donno M., Ivaldi A., Benini L., et al. Clock-Tree Power Optimization based on RTL Clock-Gating. In Proc. of the 40th conference on Design automation, June 2-6, 2003. Anaheim, California, USA: ACM Press, New York, NY, USA, 2003. 622～627
[22] Heydari P., Pedram M. Interconnect Energy Dissipation in High-Speed ULSI Circuits. In Proc. of ASP-DAC/VLSI Design 2002, Jan, 2002. Bangalore, India: IEEE, 2002. 132～140
[23] Kapur P., Chandra G., Saraswat K. C. Power Estimation in Global Interconnects and its Reduction Using a Novel Repeater Optimization Methodology. In Proc. of the 39th conference on Design automation, June, 2002. New Orleans, Louisiana, USA: ACM Press, New York, NY, USA, 2002. 461～466
[24] Wason V., Banerjee K. A Probabilistic Framework for Power-Optimal Repeater Insertion in Global Interconnects under Parameter Variations. In Proc. of the 2005 international symposium on Low power electronics and design, August 8-10, 2005. San Diego, California, USA: ACM Press, New York, NY, USA, 2005. 131～136
[25] Kim N. S., Austin T., Blaauw D., et al. Leakage Current: Moore's Law Meets Static Power. IEEE Computer, 2003, 36(12): 65～77
[26] Kim N. S., Blaauw D., Mudge T. Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. In Proc. of 2003 International Conference on Computer-Aided Design (ICCAD'03), November 11-13, 2003. San Jose, California, USA: IEEE Computer Society / ACM, 2003. 627～632
[27] Ananthan H., Kim C. H., Roy K. Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS. In Proc. of the 2004 international symposium onLow power electronics and design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, New York, NY, USA, 2004. 8～13
[28] Rao R. M., Burns J. L., Devgan A. Efficient Techniques for Gate Leakage Estimation. In Proc. of the 2003 international symposium on Low power electronics and design, August 25-27, 2003. Seoul, Korea: ACM Press, New York, NY, USA, 2003. 100～103
[29] Piguet C., Renaudin M., Omnes T. J. Special Session on Low-Power Systems on Chips (SOCs). In Proc. of Design, Automation, and Test in Europe (DATE '01), February 2004. Paris, France: IEEE Computer Society, 2001
[30] Powell M. D., Schuchman E., Vijaykumar T. N. Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. In Proc. of the 38th annual IEEE/ACM International Symposium on Microarchitecture, November 12-16, 2005. Barcelona, Spain: IEEE CS, 2005. 294～304
[31] Ku J. C., Ozdemir S., Memik G., et al. Thermal Management of On-Chip Caches Through Power Density Minimization. In Proc. of the 38th annual IEEE/ACM International Symposium on Microarchitecture, November 12-16, 2005. IEEE CS, 2005. 283～293
[32] Gandhi K. R., Mahapatra N. R. A Detailed Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. In Proc. of Second Annual Workshop on Duplicating, Deconstructing and Debunking, June 8, 2003. San Diego, California, 2003
[33] Tang W., Gupta R., Nicolau A. Power Savings in Embedded Processors through Decode Filter Cache. In Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March, 2002. Paris, France: IEEE CS, 2002. 443～448
[34] Zhang C., Yang J., Vahid F. Low Static-Power Frequent-Value Data Caches. In Proc. of 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Feb. 16-20, 2004. Paris, France: IEEE CS, 2004. 214～219
[35] Hu J. S., Vijaykrishnan N., Kim S., et al. Scheduling Reusable Instructions for Power Reduction. In Proc. of the conference on Design, automation and test in Europe - Volume 1, Feb. 16-20, 2004. Paris, France: IEEE CS, 2004. 148～155
[36] Yang J., Gupta R. Energy Efficient Frequent Value Data Cache Design. In Proc. of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 197～207
[37] Brooks D., Martonosi M. Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. In Proc. of the 5th International Symposium on High Performance Computer Architecture(HPCA'99), 9-12 January, 1999. Orlando, FL, USA: IEEE CS, 1999. 13
[38] Pokam G., Rochecouste O., Andr′eSeznec, et al. Speculative Software Management of Datapath-width for Energy Optimization. In Proc. of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, June 11-13, 2004. Washington, DC, USA: ACM Press, New York, NY, USA, 2004. 78～87
[39] Macii L. D. A. E. M. Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. In Proc. of 2002 Design,Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March, 2002. Paris, France: IEEE CS, 2002. 449～450
[40] Zhang Y., Gupta R. Enabling Partial Cache Line Prefetching Through Data Compression. In Proc. of 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October, 2003. Kaohsiung, Taiwan: IEEE CS, 2003. 277～285
[41] Ekman M., Stenstrom P. A Robust Main-Memory Compression Scheme. In Proc. of 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005. Madison, Wisconsin, USA: IEEE CS, 2005. 74～85
[42] Canal R., AntonioGonzález, Smith J. E. Very Low Power Pipelines using Significance Compression. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 10-13 December 2000. Monterey, California, USA: ACM Press, 2000. 181～190
[43] Suresh D. C., Agrawal B., Yang J., et al. Power Efficient Encoding Techniques for Off-chip Data. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30, 2003. San Jose, California, USA: ACM Press, 2003. 267～275
[44] Gupta J. R. C. Z. Frequent Value Encoding for Low Power Data Buses. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2004, 9(3): 354～384
[45] Cheng W., Pedram M. Low Power Techniques for Address Encoding and Memory Allocation. In Proc. of the 2001 conference on Asia South Pacific design automation, January 30, 2001. Yokohama, Japan: ACM Press, 2001. 245～250
[46] Zhang C., Vahid F. A Power-Configurable Bus for Embedded Systems. In Proc. of IEEE International Symposium on Circuits and Systems, May 2002. Scottsdale: IEEE CS, 2002. 809～812
[47] Basu K., Choudhary A., Pisharath J., et al. Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM Press, 2002. 345～355
[48] Li H., Bhunia S., Chen Y., et al. Deterministic Clock Gating for Microprocessor Power Reduction. In Proc. of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), February 8-12, 2003. Anaheim, California, USA: IEEE CS, 2003. 113
[49] Wu Q., Pedram M., Wu X. Clock-Gating and Its Application to Low Power Design of Sequential Circuits. IEEE Trans on Circuits and Systems I: Fundamental Theory and Applications, 2000, 47(3): 415～420
[50] Emnett F., Biegel M. Power Reduction Through RTL Clock Gating:Tech Report. SNUG. Automotive Integrated Electronics Corporation, 2000. 11
[51] Luo Y., Yu J., Yang J., et al. Low Power Network Processor Design Using Clock Gating. In Proc. of the 42nd Design Automation Conference, DAC 2005, June 13-17, 2005. Anaheim, California, USA: ACM Press, 2005. 712～715
[52] Macii A., Macii E., Poncino M. Improving the Efficiency of Memory Partitioning by Address Clustering. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003),, 3-7 March 2003.Munich, Germany: IEEE CS, 2003. 10018～10023
[53] Zyuban V. V. INHERENTLY LOWER-POWER HIGH-PERFORMANCE SUPERSCALAR ARCHITECTURES: Department of Computer Science and Engineering, Notre Dame, Indiana, March 2000
[54] Tseng J. H., KrsteAsanovi ′ c. Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. In Proc. of 30th International Symposium on Computer Architecture (ISCA-30), 9-11 June 2003. San Diego, CA: IEEE CS, 2003. 62～71
[55] Ashok R., Chheda S., Moritz C. A. Cool-Mem: Combining Statically Speculative Memory Accessing with Selective Address Translation for Energy Efficiency. In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002. San Jose, California: ACM Press, 2002. 133～143
[56] Kucuk G., Ghose K., Ponomarev D. V., et al. Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, August, 2001. Huntington Beach, California, USA: ACM Press, 2001. 237～242
[57] Delaluz V., Kandemir M., Vijaykrishnan N., et al. DRAM Energy Management Using Software and Hardware Directed Power Mode Control. In Proc. of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 20-24 January 2001. Nuevo Leone, Mexico: IEEE CS, 2001. 159～170
[58] Balasubramonian R., Dwarkadas S., Albonesi D. H. Reducing the Complexity of the Register File in Dynamic Superscalar Processors. In Proc. of the 34th Annual International Symposium on Microarchitecture, December 1-5, 2001. Austin, Texas, USA: ACM/IEEE, 2001. 237～248
[59] Park I., Powell M. D., Vijaykumar T. N. Reducing Register Ports for Higher Speed and Lower Energy. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 171～182
[60] Zhang C., Vahid F., Najjar W. A Highly Configurable Cache Architecture for Embedded Systems. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 136～146
[61] Wang H., Peh L., Malik S. Power-driven Design of Router Microarchitectures in On-chip Networks. In Proc. of the 36th Annual International Symposium on Microarchitecture, December 3-5, 2003. San Diego, CA, USA: ACM/IEEE, 2003. 105～116
[62] Pisharath J., Choudhary A., Kandemir M. Reducing Energy Consumption of Queries in Memory-Resident Database Systems. In Proc. of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 22 - 25, 2004. Washington DC, USA: ACM Press, 2004. 35～45
[63] Albonesi D. H. Selective Cache Ways: On-Demand Cache Resource Allocation. In Proc. of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 16-18 November, 1999. Haifa, Israel: ACM/IEEE, 1999. 248-
[64] Witchel E., KrsteAsanovi′c. The Span Cache: Software Controlled Tag Checks and Cache Line Size. In Proc. of Workshop on Complexity-Effective Design ,28th ISCA, July, 2001. Gotenborg, Sweeden: IEEE CS, 2001. 1～12
[65] Witchel E., Larsen S., Ananian C. S., et al. Direct Addressed Caches for Reduced Power Consumption. In Proc. of 34th Annual International Symposium on Microarchitecture ,MICRO-34, December 2001. Austin, Texas: ACM/IEEE, 2001. 124～133
[66] Albonesi D. H. Dynamic IPC/Clock Rate Optimization. In Proc. of the 25th annual international symposium on Computer architecture, 1998. Barcelona, Spain: IEEE CS, 1998. 282～292
[67] Ponomarev D., Kucuk G., Ghose K. DYNAMIC ALLOCATION OF DATAPATH RESOURCES FOR LOW POWER. In Proc. of Workshop on Complexity-Effective Design (WCED-01), held in conjunction with ISCA, June 2001. Goteborg, Sweden, 2001
[68] Dropshoy S., Buyuktosunogluz A., Balasubramoniany R., et al. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. In Proc. of 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002. Charlottesville, VA, USA: IEEE CS, 2002. 141
[69] Buyuktosunoglu A., Karkhanisy T., Albonesi D. H., et al. Energy Efficient Co-Adaptive Instruction Fetch and Issue. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 147～156
[70] Balasubramonian R., Albonesi D., Buyuktosunoglu A., et al. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 10-13 December 2000. Monterey, California, USA: ACM/IEEE, 2000. 245～257
[71] Hartenstein R. A Decade of Reconfigurable Computing: a Visionary Retrospective. In Proc. of the conference on Design, automation and test in Europe 2001, March 12-15, 2001. Munich, Germany: IEEE Press, 2001. 642～649
[72] Hauser J. R. Augmenting a Microprocessor with Reconfigurable Hardware: Ph.D Thesis. UNIVERSITY OF CALIFORNIA, BERKELEY, Fall 2000
[73] Sankaralingam K., Nagarajan R., Liu H., et al. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. In Proc. of the 30th Annual International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 422～433
[74] Mai K., Paaske T., Jayasena N., et al. Smart Memories: a modular reconfigurable architecture. In Proc. of the 27th annual international symposium on Computer architecture, June 2000. Vancouver, British Columbia, Canada: ACM Press, 2000. 161～171
[75] Schmit H., Whelihan D., Tsai A., et al. PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology. In Proc. of Custom Integrated Circuits Conference, 2002, May 12-15, 2002. Caribe Royale Resort Suites, Orlando, Florida, USA: IEEE Press, 2002. 63～66
[76] Taylor M. B., Lee W., Miller J., et al. Evaluation of the Raw Microprocessor:An Exposed-Wire-Delay Architecture for ILP and Streams. In Proc. of the 31st annual international symposium on Computer architecture (ISCA 2004), 19-23 June 2004. München, Germany: IEEE CS, 2004. 2～13
[77] Burd T. D., Pering T. A., Stratakos A. J., et al. A Dynamic Voltage Scaled Microprocessor System. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35(11): 1571～1580
[78] Hsu C. COMPILER-DIRECTED DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR CPU POWER AND ENERGY REDUCTION: Ph.D Thesis. New Brunswick Rutgers, The State University of New Jersey, October, 2003
[79] Fleischmann M. LongRun Power Management: Dynamic Power Management for Crusoe Processors:Tech Report. Transmeta Corporation, January 17, 2001.
[80] Paper I. W. Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor:Tech Report. Order Number: 301170-001. March 2004.
[81] Smith S. F. A MULTIPLE-CLOCK-DOMAIN BUS ARCHITECTURE USING ASYNCHRONOUS FIFOS AS ELASTIC ELEMENTS: Ph.D Thesis. College of Graduate Studies, University of Idaho, October 2003
[82] Semeraro G., Magklis G., Balasubramonian R., et al. Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In Proc. of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02), 2-6 February 2002. Boston, Massachusettes, USA: IEEE CS, 2002. 29～42
[83] Iyer A., Marculescu D. Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. In Proc. of 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002. Anchorage, AK, USA: IEEE CS, 2002. 158
[84] Oliver J., Rao R., Sultana P., et al. Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. In Proc. of 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004. Munich, Germany: IEEE CS, 2004. 150～161
[85] Magklis G., Scott M. L., Semeraro G., et al. Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 14～25
[86] Sasaki H., Kondo M., Nakamura H. Dynamic Instruction Cascading on GALS Microprocessors. In Proc. of Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, September 21-23, 2005. Leuven, Belgium: Springer, 2005. 30～39
[87] Semeraro G. P. Multiple Clock Domain Microarchitecture Design and Analysis: Ph.D Thesis. University of Rochester,
[88] Choi K., Soma R., Pedram M. Dynamic Voltage and Frequency Scaling based on Workload Decomposition. In Proc. of the 2004 international symposium on Low power electronics and design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, 2004. 174～179
[89] Kumar R., Farkas K. I., Jouppi N. P., et al. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In Proc. of the 36th International Symposium on Microarchitecture (MICRO-362003), December 3-5, 2003. San Diego, CA, USA: ACM/IEEE, 2003. 81～92
[90] Lin Y., Lee H., Woh M., et al. SODA: A Low-power Architecture For Software Radio. In Proc. of The 33rd Annual International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006. Boston, MA USA: ACM Press, 2006
[91] Weglarz E. F., Saluja K. K., Lipasti M. H. Minimizing Energy Consumption for High-Performance Processing. In Proc. of the 2002 conference on Asia South Pacific design automation/VLSI Design, 7-11 January 2002. Bangalore, India: IEEE CS, 2002. 199～206
[92] Kandemir M., Zhang W., Karakoy M. Runtime Code Parallelization for On-Chip Multiprocessors. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003. Munich, Germany: IEEE CS, 2003. 10510～10515
[93] Wall D. W. Limits of Instruction-Level Parallelism. In Proc. of Forth International Conference on Architectural Support for Programming Languages and Operating Systems, April 8-11, 1991. Santa Clara, California: ACM Press, 1991. 176～188
[94] 易会战, 杨学军. 嵌入式应用中指令级并行的动态特性. In Proc. of 2005中国计算机大会(CNCC'2005), 2005, 10. 武汉, 中国, 2005
[95] 易会战, 陈娟. 多核微处理器体系结构、编程模型和编译技术:技术报告. 国防科技大学软件所编译组, 2005年8月.
[96] Tendler J., Dodson J., Fields J. J. S., et al. POWER4 system microarchitecture. IBM Journal of Research and Development, 2002, 46(1): 5～25
[97] Eggers S. J., Emer J. S., Levy H. M., et al. SIMULTANEOUS MULTITHREADING: A Platform for Next-Generation Processors. IEEE Micro, 1997, 17(5): 12～19
[98] Sohi G. S., Roth A. Speculative Multithreaded Processors. IEEE Computer, 2001, 34(4): 66～73
[99] Asanovic K. Vector Processors (Appendix G). In: Computer Architecture: A Quantitative Approach, Third Edition. : Morgan Kaufman, 2002
[100] Kozyrakis C. E., Perissakis S., Patterson D., et al. Scalable Processors in the Billion-Transistor Era: IRAM. IEEE Computer, 1997, 30(9): 75～78
[101] Kozyrakis C. D. P. Overcoming the Limitations of Conventional Vector Processors. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 399～409
[102] Krashinsky R., Batten C., Hampton M., et al. The Vector-Thread Architecture. In Proc. of the 31st annual international symposium on Computer architecture (ISCA 2004), June 19-23, 2004. München, Germany: IEEE CS, 2004. 52
[103] Ahn J. H., Dally W. J., Khailany B., et al. Evaluating the Imagine Stream Architecture. In Proc. of the 31st Annual International Symposium on Computer Architecture, 19-23 June 2004. Munich, Germany: IEEE CS, 2004. 14～25
[104] Halter J. P., Najm F. N. A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits. In Proc. of IEEE Custom Integrated CircuitsConference, 1997. , 1997. 475～478
[105] Johnson M. C., Somasekhar D., Roy K. Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS. In Proc. of the 36th ACM/IEEE conference on Design automation, 1999. New Orleans, Louisiana, United States: ACM Press, 1999. 442～445
[106] Abdollahi A., Fallah F., Pedram M. Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. In Proc. of the 2002 international symposium on Low power electronics and design, 2002. Monterey, California, USA: ACM Press, 2002. 213～218
[107] Kuroda T., Fujita T., Mita S., et al. A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme. In Proc. of 4th International Workshop on Advanced LSI's, July 18-20, 1996. Korea, 1996. 150～158
[108] Dropsho S., Kursun V., Albonesi D. H., et al. Managing Static Leakage Energy in Microprocessor Functional Units. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 321～332
[109] Li L., Kadayif I., Tsai Y., et al. Leakage Energy Management in Cache Hierarchies. In Proc. of 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002. Charlottesville, VA, USA: IEEE CS, 2002. 131～140
[110] Hu Z., Buyuktosunoglu A., Srinivasan V., et al. Microarchitectural Techniques for Power Gating of Execution Units. In Proc. of the 2004 International Symposium on Low Power Electronics and Design, August 9-11, 2004. Newport Beach, California, USA: ACM Press, 2004. 32～37
[111] Yang S., Powell M. D., Falsafi B., et al. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In Proc. of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 20-24 January 2001. Nuevo Leone, Mexico: IEEE CS, 2001. 147～158
[112] KrisztiánFlautner, Kim N. S., Martin S., et al. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In Proc. of 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002. Anchorage, AK, USA: IEEE CS, 2002. 148～157
[113] Kim N. S., KrisztiánFlautner, Blaauw D., et al. Drowsy Instruction: Caches Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 219～230
[114] Kim N. S., Flautner K., Blaauw D., et al. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12(2): 167～184
[115] Duarte D., Tsai Y., Vijaykrishnan N., et al. Evaluating Run-Time Techniques for Leakage Power Reduction. In Proc. of ASP-DAC/VLSI Design 2002, 7-11 January 2002. Bangalore, India: IEEE online, 2002. 31～38
[116] Vahdat A., Lebeck A., Ellis C. S. Every Joule is Precious: The Case for Revisiting Operating System Design for Energy Efficiency. In Proc. of the ACM SIGOPS European Workshop, September 17-20, 2000. Kolding, Denmark: ACM Press, 2000. 31～36
[117] Lorch J. R. Operating Systems Techniques for Reducing Processor Energy Consumption: PH.D Thesis. UNIVERSITY of CALIFORNIA, BERKELEY, Fall 2001
[118] Papathanasion A. E. On the Power Consumption of Computing Systems:Tech Report. Area Paper. University of Rochester, Rochester, NY, May 2001.
[119] Lu Y., Chung E., Simunic T., et al. Quantitative Comparison of Power Management Algorithms. In Proc. of Design Automation and Test In Europe 2000, 2000. Paris, France: ACM Press, 2000. 20～26
[120] Chedid W., Yu C. Survey on Power Management Techniques for Energy Efficient Computer Systems:Tech Report. Mobile Computing Research Lab, Cleveland State University, 2002. 1～18
[121] Benini L., Bogliolo A., Micheli G. de. A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8(3)
[122] Gurumurthi S., Sivasubramaniam A., Kandemir M., et al. DRPM: Dynamic Speed Control for Power Management in Server Class Disks. In Proc. of the 30th annual international symposium on Computer architecture, 2003. San Diego, California: ACM Press, 2003. 169～181
[123] Gurumurthi S., Zhang J., Sivasubramaniam A., et al. Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads. In Proc. of 2003 IEEE International Symposium on Performance Analysis of Systems and Software, March 6-8, 2003. Austin, Texas; USA: IEEE CS, 2003. 123～132
[124] Yu Y., Prasanna V. K. Energy-Balanced Task Allocation for Collaborative Processing in Networked Embedded Systems. In Proc. of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 11-13, 2003. San Diego, California, USA: ACM Press, 2003. 265～274
[125] Wang G., Irwin M. J., Berman P., et al. Optimizing Sensor Movement Planning for Energy Efficiency. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 215～220
[126] Dick R. P., Lakshminarayana G., Raghunathan A., et al. Power Analysis of Embedded Operating Systems. In Proc. of the 37th conference on Design automation, 2000. Los Angeles, California, United States: ACM Press, 2000. 312～315
[127] Chen G., Vijaykrishnan N., Kandemir M., et al. Tracking Object Life Cycle for Leakage Energy Optimization. In Proc. of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, October 1-3, 2003. Newport Beach, CA, USA: ACM, 2003. 213～218
[128] Zhong L., Jha N. K. Graphical User Interface Energy Characterization for Handheld Computers. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30- November 1, 2003. San Jose, California, USA: ACM Press, 2003. 232～242
[129] Zeng H., Ellis C. S., Lebeck A. R., et al. ECOSystem: Managing Energy as a First Class Operating System Resource. In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 5-9, 2002. San Jose, California: ACM Press, 2002. 123～132
[130] Zedlewski J., Sobti S., Garg N., et al. Modeling Hard-Disk Power Consumption. In Proc. of the FAST '03 Conference on File and Storage Technologies, March 31 - April 2, 2003. San Francisco, California, USA: USENIX, 2003
[131] Lu Y., Benini L., Micheli G. de. Low-Power Task Scheduling for Multiple Devices. In Proc. of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA: ACM Press, 2000. 39～43
[132] Marchal P., JoséIgnacioGómez, Pinuel L., et al. SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. In Proc. of 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003. Munich, Germany: IEEE CS, 2003. 10516～10523
[133] Pouwelse J., Langendoen K., Sips H. Energy Priority Scheduling for Variable Voltage Processors. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, 2001. Huntington Beach, California, USA: ACM Press, 2001. 28～33
[134] Weiser W., Welch B., Demers A., et al. Scheduling for Reduced CPU Energy. In Proc. of the First USENIX Symposium on Operating Systems Design and Implementation (OSDI), November 14-17, 1994. Monterey, California: ACM Press, 1994. 13～23
[135] Weissel A., Bellosa F. Process Cruise Control Event-Driven Clock Scaling for Dynamic Power Management. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Grenoble, France, 2002. 238～246
[136] Lu Z., Hein J., Humphrey M., et al. Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Greenoble, France: ACM Press, 2002. 156～163
[137] Varma A., Ganesh B., Sen M., et al. A Control-Theoretic Approach to Dynamic Voltage Scheduling. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, October 30 - November 1, 2003. San Jose, California, USA: ACM, 2003. 255～266
[138] Yan L., Zhong L., Jha N. K. User-perceived Latency Driven Voltage Scaling for Interactive Applications. In Proc. of the 42nd Design Automation Conference, DAC 2005, June 13-17, 2005. San Diego, CA, USA: ACM Press, 2005. 624～627
[139] Yang P., Wong C., Marchal P., et al. Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs. IEEE Design & Test of Computers, 2001, 18(5): 46～58
[140] Schmitz M. T., Al-hashimi B. M., Eles P. Energy-Efficient Mapping andScheduling for DVS Enabled Distributed Embedded Systems. In Proc. of 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 514～521
[141] Hewlett-packard , Intel , Microsoft , et al. Advanced Configuration and Power Interface Specification, Revision 3.0a:Tech Report. December 30, 2005.
[142] Amd . AMD PowerNow! Technology:Tech Report. AMD Corporation, 2002.
[143] Amd . Cool 'n' Quiet? Technology Installation Guide for AMD Athlon? 64 Processor Based Systems. NA Rev. 0.04:Tech Report. AMD Corporation, June 2004.
[144] Shin D., Kim J. Dynamic Voltage Scaling of Periodic and Aperiodic Tasks in Priority-Driven Systems. In Proc. of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, January 27-30, 2004. Yokohama, Japan: IEEE CS, 2004. 653～658
[145] Baynes K., Collins C., Fiterman E., et al. The Performance and Energy Consumption of Three Embedded Real-Time Operating Systems. In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 16-17, 2001. Atlanta, Georgia, USA: ACM Press, 2001. 203～210
[146] Jejurikar R., Gupta R. Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, October 8-11, 2002. Greenoble, France: ACM Press, 2002. 164～169
[147] Aydin H., Melhem R., Mosse D., et al. Power-Aware Scheduling for Periodic Real-Time Tasks. IEEE TRANSACTIONS ON COMPUTERS, 2004, 53(5)
[148] Baynes K., Collins C., Fiterman E., et al. The Performance and Energy Consumption of Embedded Real-Time Operating Systems. IEEE TRANSACTIONS ON COMPUTERS, 2003, 52(11)
[149] Jejurikar R., Gupta R. Procrastination Scheduling in Fixed Priority Real-Time Systems. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 57～66
[150] Im C., Ha S. Dynamic Voltage Scaling for Real-Time Multi-task Scheduling Using Buffers. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 88～94
[151] Swaminathan V., Chakrabarty K. Investigating the Effect of Voltage-Switching on Low-Energy Task Scheduling in Hard Real-Time Systems. In Proc. of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001. Yokohama, Japan: ACM Press, 2001. 251
[152] Shin D., Kim W., Jeon J., et al. SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms. In Proc. of Power-Aware Computer Systems, Second International Workshop, PACS 2002, February 2, 2002. Cambridge, MA, USA: Springer, 2002. 141～156
[153] Aydin H., Yang Q. Energy-Aware Partitioning for Multiprocessor Real-Time Systems. In Proc. of 17th International Parallel and Distributed ProcessingSymposium (IPDPS 2003), 22-26 April 2003. Nice, France: IEEE CS, 2003. 113
[154] Zhu D. ENERGY AND RELIABILITY MANAGEMENT IN PARALLEL REAL-TIME SYSTEMS: Ph.D Thesis. University of Pittsburgh, 2004
[155] Mishra R., Rastogi N., Zhu D., et al. Energy Aware Scheduling for Distributed Real-Time Systems. In Proc. of 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003. Nice, France: IEEE CS, 2003. 21
[156] Langen P. de, Juurlink B. Leakage-Aware Multiprocessor Scheduling for Low Power. In Proc. of the 20th International Parallel and Distributed Processing Symposium, April 2006. Rhodos, Greece: IEEE CS, 2006. 1～8
[157] Shin D., Kim J. Power-Aware Scheduling of Conditional Task Graphs in Real-Time Multiprocessor Systems. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 408～413
[158] Chase J. S., Doyle R. P. Balance of Power: Energy Management for Server Clusters. In Proc. of the 8th Workshop on Hot Topics in Operating Systems (HotOS), May 20-23, 2001. Schloss Elmau, Germany: IEEE CS, 2001
[159] Pinheiro E., Bianchini R., Carrera E. V., et al. Dynamic cluster reconfiguration for power and performance. In: Compilers and operating systems for low power. : Kluwer Academic Publishers, 2003. 75～93
[160] Chase J. S., Anderson D. C., Thakar P. N., et al. Managing Energy and Server Resources in Hosting Centers. In Proc. of the eighteenth ACM symposium on Operating systems principles, 2001. Banff, Alberta, Canada: ACM Press, 2001. 103～116
[161] Bianchini R. Research Directions in Power and Energy Conservation for Clusters : Tech Report. DCS-TR-466. Department of Computer Science, Rutgers University, November 2001.
[162] Pinheiro E., Bianchini R. Energy Conservation Techniques for Disk Array-Based Servers. In Proc. of the 18th Annual International Conference on Supercomputing, ICS 2004, June 26 - July 01, 2004. Saint Malo, France: ACM Press, 2004. 68～78
[163] Heath T., Diniz B., Carrera E. V. Energy Conservation in Heterogeneous Server Clusters. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 186～195
[164] Pinheiro E., Bianchini R., Dubnicki C. Exploiting Redundancy to Conserve Energy in Storage Systems. In Proc. of the Joint International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), June 26-30, 2006. Saint Malo, France: ACM Press, 2006
[165] Elnozahy E. N. (., Kistler M., Rajamony R. Energy-Efficient Server Clusters. In Proc. of 2nd Workshop on Power-Aware Computing Systems, February 2002. Cambridge, MA, USA: Springer Verlag, 2002
[166] Lefurgy C., Rajamani K., Rawson F., et al. Energy Management for Commercial Servers. IEEE Computer, 2003, 36(12): 39～48
[167] Bianchini R., Rajamony R. Power and Energy Management for Server Systems. IEEE Computer, 2004, 37(11): 68～74
[168] Xu R., Zhu D., Rusu C., et al. Energy-Efficient Policies for Embedded Clusters. In Proc. of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), June 15-17, 2005. Chicago, Illinois, USA: ACM Press, 2005. 1～10
[169] Tsui C. C. A. M. D. Low Power Architecture Design and Compilation Techniques for High-Performance Processors. In Proc. of CompCon'94 Digest of Technical Papers, February 1994. , 1994. 489～498
[170] Tiwari V., Malik S., Wolfe A. Power Analysis of Embedded Software: A First Step towards Software Power Minimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, 2(4): 437～445
[171] Tiwari V., Malik S., Wolfe A. Compilation Techniques for Low Energy: An Overview. In Proc. of IEEE Symposium of Low Power Electronics, Oct. 1994. : IEEE CS, 1994. 38～39
[172] Lee M. T., Tiwari V., Malik S., et al. Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software. Fujitsu Scientific and Technical Journal, 1995, 31(3): 215～229
[173] Tiwari V., Malik S., Wolfe A., et al. Instruction Level Power Analysis and Optimization of Software. Journal of VLSI Signal Processing, 1996, 13(2/3): 223～238
[174] Toburen M., Conte T. M., Reilly M. Instruction Scheduling for Low Power Dissipation in High Performance Microprocessors. In Proc. of the Power-Driven Microarchitecture Workshop, 1998, June 1998. Barcelona, Spain, 1998
[175] Chang J., Pedram M. Register Allocation and Binding for Low Power. In Proc. of the 32nd ACM/IEEE conference on Design automation, June 1995. San Francisco, CA: ACM Press, 1995. 29～35
[176] Mehta H., Owens R. M., Irwin M. J., et al. Techniques for Low Energy Software. In Proc. of the 1997 International Symposium on Low Power Electronics and Design, August 18-20, 1997. Monterey, California, USA: ACM Press, 1997. 72～75
[177] gebotys C. H. Low Energy Memory and Register Allocation Using Network Flow. In Proc. of the 34st Conference on Design Automation, June 9-13, 1997. Anaheim, California, USA: ACM Press, 1997. 435～440
[178] Zhang Y., Hu X., Chen D. Z. Global Register Allocation for Minimizing Energy Consumption. In Proc. of the 1999 International Symposium on Low Power Electronics and Design, 1999, August 16-17, 1999. San Diego, California, USA: ACM, 1999. 100～102
[179] Steinke S., RüdigerSchwarz, Wehmeyer L., et al. Low power code generation for a RISC processor by register pipelining:Tech Report. No. 754. University of Dortmund, Dept. of CS XII, 2001, 2001.
[180] Anand R., Jacome M. F., Veciana G. de. Heuristic Tradeoffs Between Latency and Energy Consumption in Register Assignment. In Proc. of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, May 2000. San Diego, California, USA: ACM Press, 2000. 115～119
[181] Valluri M., John L. Is Compiling for Performance = = Compiling for Power? In Proc. of the 5th Annual Workshop on Interaction between Compilers andComputer Architectures INTERACT-5, Jan. 2001. Monterey, Mexico, 2001
[182] Kandemir M. T., Vijaykrishnan N., Irwin M. J., et al. Influence of Compiler Optimizations on System Power. In Proc. of the 37th Conference on Design Automation, June 2000. Los Angeles, CA, USA: ACM Press, 2000. 304～307
[183] Yang H., Gao G. R., Marquez A., et al. Power and Energy Impact by Loop Transformation. In Proc. of Workshop on Compilers and Operating Systems for Low Power (COLP01), Sept 2001. Barcelona, SPAIN, 2000
[184] Seng J. S., Tullsen D. M. The Effect of Compiler Optimization on Pentium 4 Power Consumption. In Proc. of the Seventh Workshop on Interaction between Compilers and Computer Architectures, Feb. 2003. Anaheim, CA, USA: IEEE CS, 2003. 51～56
[185] LakshmiNChakrapani;PinarKorkmaz, Iii V. J. M., Palem K. V., et al. The Emerging Power Crisis in Embedded Processors: What can a(poor) Compiler do? In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 2001. Atlanta, Georgia, USA: ACM Press, 2001. 176～180
[186] Kandemir M. T., Vijaykrishnan N., Irwin M. J., et al. Towards Energy-Aware Iteration Space Tiling. In Proc. of Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, June 18, 2000. Vancouver, BC, Canada: Springer, 2000. 211～215
[187] Kim H. S., Irwin M. J., Vijaykrishnan N., et al. Effect of Compiler Optimizations on Memory Energy. In Proc. of IEEE Workshop on Signal Processing Systems, October 2000. : IEEE CS, 2000. 663--672
[188] Zambreno J., Kandemir M. T., Choudhary A. N. Enhancing Compiler Techniques for Memory Energy Optimizations. In Proc. of Embedded Software, Second International Conference, EMSOFT 2002, October 7-9, 2002. Grenoble, France: Springer, 2002. 364～381
[189] Guo Y., Chheda S., Koren I., et al. Energy-Aware Data Prefetching for General-Purpose Programs. In Proc. of Power-Aware Computer Systems(PACS'04), Micro-37, December 5th, 2004. Portland, OR: Springer, 2004
[190] Zhu Y., Magklis G., Scott M. L., et al. The Energy Impact of Aggressive Loop Fusion. In Proc. of 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004. Antibes Juan-les-Pins, France: IEEE CS, 2004. 153～164
[191] Mosse D., Aydin H., Childers B., et al. Compiler-Assisted Dynamic Power-Aware Scheduling for Real-Time Applications. In Proc. of Workshop on Compilers and Operating Systems for Low-Power (COLP 2000), Oct. 2000. Philadelphia, PA, 2000
[192] Lee S., Sakurai T. Run-Time Voltage Hopping for Low-Power Real-Time Systems. In Proc. of the 37th Conference on Design Automation, June 5-9, 2000. Los Angeles, CA, USA: ACM Press, 2000. 806～809
[193] Shin D., Kim J., Lee S. Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications. IEEE Design & Test of Computers, 2001a, 18(2): 20～30
[194] Shin D., Kim J., Lee S. Low-Energy Intra-Task Voltage Scheduling UsingStatic Timing Analysis. In Proc. of the 38th Design Automation Conference, DAC 2001, June 18-22, 2001. Las Vegas, NV, USA: ACM Press, 2001b. 438～443
[195] Saputra H., Kandemir M. T., Vijaykrishnan N., et al. Energy-Conscious Compilation Based on Voltage Scaling. In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), June 2002. Berlin, Germany: ACM Press, 2002. 2～11
[196] Gruian F. Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS Processors. In Proc. of the International Symposium on Low-Power Electronics and Design ISLPED'01, Aug. 2001. Huntington Beach, CA: ACM Press, 2001. 46～51
[197] Azevedo A., Issenin I., Cornea R. R. G., et al. Profile-based Dynamic Voltage Scheduling Using Program Checkpoints. In Proc. of 2002 Design,Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 168～175
[198] Shin D., Kim J. A Profile-Based Energy-Efficient Intra-Task Voltage Scheduling Algorithm for Hard Real-Time Applications. In Proc. of the 2001 International Symposium on Low Power Electronics and Design, August 2001. Huntington Beach, California, USA: ACM Press, 2001. 271～274
[199] Aboughazaleh N., DanielMossé, Childers B. R., et al. Collaborative Operating System and Compiler Power Management for Real-Time Applications. In Proc. of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), May 27-30, 2003. Toronto, Canada: IEEE CS, 2003. 133
[200] Aboughazaleh N., Childers B. R., DanielMossé, et al. Energy management for real-time embedded applications with compiler support. In Proc. of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 2003. San Diego, CA: ACM Press, 2003. 284～293
[201] Gheorghita S. V., Basten T., Corporaal H. Intra-task Scenario-aware Voltage Scheduling. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24-27, 2005. San Francisco, California, USA: ACM Press, 2005. 177～184
[202] Liu C., Sivasubramaniam A., Kandemir M., et al. Exploiting Barriers to Optimize Power Consumption of CMPs. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[203] Xie F., Martonosi M., Malik S. Compile-Time Dynamic Voltage Scaling Settings: Opportunities and Limits. In Proc. of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, June 9-11, 2003. San Diego, California, USA: ACM Press, 2003. 49～62
[204] Hsu C., Kremer U. The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction. In Proc. of ACM SIGPLAN 2003 conference on Programming language design and implementation, June 2003. San Diego, California, USA: ACM Press, 2003. 38～48
[205] Huang M., Renau J., Torrellas J. Profile-Based Energy Reduction for High-Performance Processors. In Proc. of Fourth Workshop on FeedbackDirected and Dynamic Optimization (FDDO), 2001, December 2, 2001. Austin Texas, 2001
[206] Huang M. C., Renau J., Torrellas J. Positional Adaptation of Processors: Application to Energy Reduction. In Proc. of 30th Annual International Symposium on Computer Architecture (ISCA), 2003, June 2003. San Diego, California: IEEE CS, 2003. 110～121
[207] Ghiasi S., Casmira J., Grunwald D. IPC Matching Mechanisms Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption. In Proc. of 2000 Workshop on Complexity Effective Design, in conjunction with the 27th International Symposium on Computer Architecture (ISCA 27), June 10, 2000. Vancouver, B.C., 2000
[208] Rele S., Pande S., Onder S., et al. Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. In Proc. of International Conference on Compiler Construction (CC), 2002, April 2002. Grenoble, France: Springer Verlag, 2002. 261～275
[209] Zhang W., Kandemir M. T., Vijaykrishnan N., et al. Compiler Support for Reducing Leakage Energy Consumption. In Proc. of 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003. Munich, Germany: IEEE CS, 2003. 11146～11147
[210] Zhang W., Vijaykrishnan N., Kandemir M. T., et al. Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction. In Proc. of The 34th Annual International Symposium on Microarchitecture (MICRO-34), December 1-5, 2001. Austin, Texas, USA: ACM/IEEE, 2001. 102～113
[211] Kim H. S., Vijaykrishnan N., Kandemir M. T., et al. Adapting Instruction Level Parallelism for Optimizing Leakage in VLIW Architectures. In Proc. of Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), June 11-13, 2003. San Diego, California, USA: ACM Press, 2003. 275～283
[212] Unsal O. S., Koren I., Krishna C. M., et al. Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling. ACM Computer Architecture Letters, 2002, 1-
[213] Azevedo A., Issenin I., Cornea R., et al. Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project. In Proc. of the Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01), Jan 2001. : IEEE CS, 2001
[214] JoséLAyala, Veidenbaum A. V., MarisaLuisaLópez-vallejo. Power-Aware Compilation for Register File Energy Reduction. International Journal of Parallel Programming, 2003, 31(6): 451～467
[215] Bellas N., Hajj I., Polychronopoulos C. D., et al. Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(3): 317～326
[216] Kim S. W., Eigenmann R. Compiler Techniques for Energy Saving in Instruction Caches of Speculative Parallel Microarchitectures. In Proc. of the 2000 International Conference on Parallel Processing, 21-24 August 2000. Toronto, Canada: IEEE CS, 2000. 77-
[217] Chen G., Kandemir M. T., Vijaykrishnan N., et al. Adaptive Garbage Collection for Battery-Operated Environments. In Proc. of The 2nd USENIXJava Virtual Machine Research and Technology Symposium (JVM'02), August 1-2, 2002. San Francisco, CA, USA: USENIX, 2002. 1～12
[218] Zhang W., Hu J. S., Degalahal V., et al. Compiler-Directed Instruction Cache Leakage Optimization. In Proc. of the 35th Annual International Symposium on Microarchitecture (MICRO-35), November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 208～218
[219] Hu J. S., Kandemir M. T., Vijaykrishnan N., et al. Compiler-Directed Cache Polymorphism. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), June 19-21, 2002. Berlin , Germany: ACM Press, 2002. 165～174
[220] Zhang W., Karakoy M., Kandemir M. T., et al. A Compiler Approach for Reducing Data Cache Energy. In Proc. of 17th Annual ACM International Conference on Supercomputing (ICS'03), June 23-26, 2003. San Francisco, CA, USA: ACM Press, 2003. 76～85
[221] Zhang W. Compiler-Directed Data Cache Leakage Reduction. In Proc. of IEEE Computer Society Symposium on VLSI (ISVLSI04), 19-20 February 2004. Lafayette, LA, USA: IEEE CS, 2004. 305～306
[222] Hu J. S., Nadgir A., Vijaykrishnan N., et al. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 402～407
[223] Delaluz V., Kandemir M. T., Vijaykrishnan N., et al. Energy-Oriented Compiler Optimizations for Partitioned Memory Architectures. In Proc. of International Conference on Compilers, Architectures, and Synthesis for Embedded Systems CASES'00, November 2000. San Jose, CA: ACM Press, 2000. 138～147
[224] Kandemir M. T., Sezer U., Delaluz V. Improving Memory Energy Using Access Pattern Classification. In Proc. of the International Conference on Computer Aided Design (ICCAD'01), November 4-8, 2001. San Jose, CA, USA: ACM Press, 2001. 201～206
[225] Delaluz V., Kandemir M. T., Vijaykrishnan N., et al. Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. In Proc. of ASP-DAC/VLSI Design 2002, 7-11 January 2002. Bangalore, India: IEEE CS, 2002. 288-
[226] Luz V. de La, Kandemir M. T., Kolcu I. Automatic data migration for reducing energy consumption in multi-bank memory systems. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 213～218
[227] Palem K. V., Rabbah R. M., Mooney V. J., et al. space optimization of embedded memory systems via data remapping. In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), 19-21 June 2002. Berlin, Germany: ACM Press, 2002. 28～37
[228] Kim H. S., Vijaykrishnan N., Kandemir M. T., et al. Estimating Influence of Data Layout Optimizations on SDRAM Energy Consumption. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, August25-27, 2003. Seoul, Korea: ACM Press, 2003. 40～43
[229] Cooper K. D., Xu L. Memory Redundancy Elimination to Improve Application Energy Efficiency. In Proc. of Languages and Compilers for Parallel Computing, 16th International Workshop, LCPC 2003, October 2-4, 2003. College Station, TX, USA: Springer, 2003. 288～305
[230] Yang H. Power-Aware Compilation Techniques for High Performance Processors: Ph.D Thesis. University of Delaware, 2004
[231] Papathanasiou A. E., Scott M. L. Energy Efficient Prefetching and Caching. In Proc. of the USENIX 2004 Annual Technical Conference (USENIX'04), June 27-July 2, 2004. Boston Marriott Copley Place, Boston, MA, USA: USENIX, 2004. 255～268
[232] Heath T., Pinheiro E., Hom J., et al. Code Transformations for Energy-Efficient Device Management. IEEE Transactions on Computers, 2004, 53(8): 974～987
[233] Hom J., Kremer U. Inter-program Compilation for Disk Energy Reduction. In Proc. of Workshop on Power-Aware Computer Systems (PACS'03), December 2003. San Diego, CA: Springer, 2003. 1～14
[234] Son S. W., Chen G., Kandemir M. A Compiler-Guided Approach for Reducing Disk Power Consumption by Exploiting Disk Access Locality. In Proc. of the International Symposium on Code Generation and Optimization, 2006, March 26-29, 2006. Manhattan, New York, NY: IEEE CS, 2006. 256～268
[235] Son S. W., Kandemir M. T., Choudhary A. N. Software-Directed Disk Power Management for Scientific Applications. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[236] Kandemir M. T., Son S. W., Chen G. An evaluation of code and data optimizations in the context of disk power reduction. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 209～214
[237] Son S. W., Chen G., Kandemir M. T. Power-aware code scheduling for clusters of active disks. In Proc. of the 2005 International Symposium on Low Power Electronics and Design, August 8-10, 2005. San Diego, California, USA: ACM Press, 2005. 293～298
[238] Son S. W., Chen G., Kandemir M. T., et al. Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 174～185
[239] Hom J., Kremer U. Energy Management of Virtual Memory on Diskless Devices. In Proc. of the Workshop on Compilers and Operating Systems(COLP'01), September 2001. Barcelona, Spain: Kluwer Academic Publishers, 2001. 95～113
[240] Chen G., Chen G., Kandemir M. T., et al. Compiler-Based Code Partitioning for Intelligent Embedded Disk Processing. In Proc. of Languages and Compilers for Parallel Computing, 16th International Workshop, LCPC 2003, October 2-4, 2003. College Station, TX, USA: Springer, 2003. 451～465
[241] Kremer U., Hicks J., Rehg J. M. Compiler-Directed Remote Task Execution for Power Management. In Proc. of Workshop on Compilers and OperatingSystems for Low Power (COLP'00), October 2000. Philadelphia, Pennsylvania, USA: IEEE CS, 2000
[242] Li Z., Wang C., Xu R. Computation offloading to save energy on handheld devices: a partition scheme. In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), November 16-17, 2001. Atlanta, Georgia, USA: ACM Press, 2001. 238～246
[243] Palm J., Lee H., Diwan A., et al. When to use a compilation service? In Proc. of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), 19-21 June 2002. Berlin, Germany: ACM Press, 2002. 194～203
[244] Olsen C. M., Morrow L. A. Multi-processor Computer System Having Low Power Consumption. In Proc. of Power-Aware Computer Systems, Second International Workshop, PACS 2002, February 2, 2002. Cambridge, MA, USA: Springer, 2002. 53～67
[245] Kadayif I., Kandemir M. T., Karakoy M. An Energy Saving Strategy Based on Adaptive Loop Parallelization. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 195～200
[246] Freeh V. W., Pan F., Kappiah N., et al. Exploring the Energy-Time Tradeoff in MPI Programs on a Power-Scalable Cluster. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[247] Pan F., Freeh V. W., Smith D. M. Exploring the Energy-Time Tradeoff in High-Performance Computing. In Proc. of 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 4-8 April 2005. Denver, CA, USA: IEEE CS, 2005
[248] Freeh V. W., Lowenthal D. K. Using Multiple Energy Gears in MPI Programs on a Power-Scalable Cluster. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2005, June 15-17, 2005. Chicago, IL, USA: ACM Press, 2005. 164～173
[249] Springer R., Lowenthal D. K., Rountree B., et al. Minimizing Execution Time in MPI Programs on an Energy-Constrained, Power-Scalable Cluster. In Proc. of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 2006, March 29-31, 2006. New York, USA: ACM Press, 2006. 230～238
[250] Kappiah N., Freeh V. W., Lowenthal D. K. Just In Time Dynamic Voltage Scaling: Exploiting Inter-Node Slack to Save Energy in MPI Programs. In Proc. of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing (SC'05), November 12-18, 2005. Seattle, WA, USA: IEEE CS, 2005. 33
[251] Unnikrishnan P., Chen G., Kandemir M. T., et al. Dynamic compilation for energy adaptation. In Proc. of the 2002 IEEE/ACM International Conference on Computer-aided Design, November 10-14, 2002. San Jose, California, USA: ACM Press, 2002. 158～163
[252] Son S. W., Chen G., Kandemir M., et al. Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications. In Proc. of the 18thWorkshop on Languages and Compilers for Parallel Computing (LCPC'05), October 2005. Hawthorne, New York: Springer, 2005
[253] Wu Q., Reddi V. J., Wu Y., et al. A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. In Proc. of 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005. Barcelona, Spain: IEEE CS, 2005. 271～282
[254] Landman P. E. High-Level Power Estimation. In Proc. of the 1996 International Symposium on Low Power Electronics and Design, August 12-14, 1996. Monterey, California, USA: IEEE CS, 1996. 29～35
[255] Kim N. S., Austin T., Mudge T., et al. Challenges for Architectural Level Power Modeling. In: Power aware computing. Norwell, MA, USA: Kluwer Academic Publishers, 2002. 317～337
[256] Cai G., Lim C. H. Architectural level power/performance optimization and dynamic power estimation. In Proc. of CoolChips Tutorial colocated with MICRO32, November 16-18, 1999. Haifa, Israel, 1999
[257] Dhodapkar A., Lim C., Cai G., et al. TEM2P2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator. In Proc. of the First International Workshop on Power-Aware Computer Systems, 2000, Cambridge, MA: Springer-Verlag, 2000. 112～125
[258] Liao W., He L. Power Modeling and Reduction of VLIW Processors. In Proc. of Workshop on Compilers and Operating Systems for Low Power(COLP'01) , PACT'01, September 9th, 2001. Barcelona, Spain, 2001
[259] Vijaykrishnan N., Kandemir M. T., Irwin M. J., et al. Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower. In Proc. of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, June 10-14, 2000. Vancouver, BC, Canada: IEEE CS, 2000. 95～106
[260] Brooks D., Tiwari V., Martonosi M. Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In Proc. of 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000. Vancouver, BC, Canada: IEEE CS, 2000. 83～94
[261] Ponomarev D., Kucuk G., Ghose K. AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. In Proc. of 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002. Paris, France: IEEE CS, 2002. 124～131
[262] Project T. S. P. M. Sim-Panalyzer2.0_Reference Manual : Tech Report. University of Michigan, the University of Colorado, 2004.
[263] Shivakumar P., Jouppi N. P. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model:Tech Report. WRL-2001-2. DEC Corporation, 2001.
[264] Zhang Y., Parikh D., Sankaranarayanan K., et al. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects:Tech Report. CS-2003-05. Department of Computer Science, University of Virginia, 2003.
[265] Skadron K., Stan M. R., Huang W., et al. Temperature-Aware Microarchitecture. In Proc. of 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003. San Diego, California, USA: IEEE CS, 2003. 2～13
[266] Wang H., Zhu X., Peh L., et al. Orion: A Power-Performance Simulator forInterconnection Networks. In Proc. of the 35th Annual International Symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey: ACM/IEEE, 2002. 294～305
[267] Gurumurthi S., Sivasubramaniam A., Irwin M. J., et al. Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. In Proc. of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2-6 February 2002. Boston, Massachusettes, USA: IEEE CS, 2002. 141～150
[268] Chen J., Dubois M., Stenstrm P. Integrating Complete-System and User-level Performance/Power Simulators: The SimWattch Approach. In Proc. of 2003 IEEE International Symposium on Performance Analysis of Systems and Software(ISPASS-2003), March 6-8, 2003. Austin, Texas, USA: IEEE CS, 2003. 1～10
[269] Contreras G., Martonosi M., Peng J., et al. XTREM: A Power Simulator for the Intel XScaler Core. In Proc. of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), June 11-13, 2004. Washington, DC, USA: ACM Press, 2004. 115～125
[270] 王永文. 高性能微处理器体系结构级功耗估算与优化技术研究: 博士论文. 国防科学技术大学研究生院, 二○○四年十月
[271] Minh D. Q., Bengtsson L., Larsson-edefors P. DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. In Proc. of The 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), February 10-13, 2003. Innsbruck, Austria: IASTED/ACTA Press, 2003. 767～772
[272] Kirkpatrick M. G., Freeh V. W., Kogge P. M., et al. Exploiting Morphable Microarchitectures for Saving Energy:Tech Report. 0109. Department of Computer Science and Engineering, University of Notre Dame, August 22, 2001.
[273] Asanovic K. Energy-Exposed Instruction Set Architectures. In Proc. of Work in Progress Session, HPCA-6, January 2000. Toulouse, France, 2000
[274] Horowitz M., Indermaur T., Gonzalez R. Low-power digital design. In Proc. of the IEEE Symposium on Low Power Electronics, October 1994. , 1994. 8～11
[275] Gonzalez R., Horowitz M. Energy dissipation In general purpose microprocessors. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31(9)
[276] Martin A. J. Towards an energy complexity of computation. Information Processing Letters, 2001, 77(2-4): 181～187
[277] Campbell M. Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. In Proc. of Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, June 1998. Montreal, Canada: Springer, 1998. 261
[278] Hartstein A., Puzak T. R. Optimum Power/Performance Pipeline Depth. In Proc. of the 36th International Symposium on Microarchitecture (MICRO-36 2003), December 3-5, 2003. San Diego, CA, USA: IEEE CS, 2003. 117～128
[279] Srinivasan V., Brooks D., Gschwind M., et al. Optimizing Pipelines for Power and Performance. In Proc. of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002. Istanbul, Turkey:IEEE CS, 2002. 333～344
[280] Heo S., Asanovic K. Power-Optimal Pipelining in Deep Submicron Technology. In Proc. of the 2004 International Symposium on Low Power Electronics and Design, August 9–11, 2004. Newport Beach, CA: ACM Press, 2004. 218～223
[281] Posti M. A., Greene D. A., Tyson G. S., et al. The Limits of Instruction Level Parallelism in SPEC95 Applications. Special issue on Interact-3 workshop, ACM SIGARCH Computer Architecture News, 1999, 27(1): 31～34
[282] Espasa R., Valero M. Exploiting instruction-level and data-level parallelism. IEEE MICRO (Special Issue on Computing with a Billion Transistors), 1997, 17(5): 20～27
[283] Tian X. Exploiting thread-level and instruction-level parallelism for Hyper-Threading technology. Intel Developer Update Magazine, 2003,: 1
[284] Adiga N. R., GeorgeAlmási, Almasi G. S., et al. An Overview of the BlueGene/L Supercomputer. In Proc. of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA: ACM Press, 2002. 1～22
[285] Warren M. S., Weigle E. H., Feng W. High-Density Computing: A 240-Processor Beowulf in one Cubic Meter. In Proc. of the 2002 ACM/IEEE conference on Supercomputing, November 16-22, 2002. Baltimore, Maryland, USA: ACM Press, 2002. 1～11
[286] Geer D. Industry Trends: Chip Makers Turn to Multicore Processors. IEEE Computer, 2005, 38(5): 11～13
[287] Krewell K. Best Servers of 2004: Where Multicore is the Norm:Tech Report. Microprocessor Report (Online), Jan 18, 2005.
[288] Kapasi U. J., Rixner S., Dally W. J., et al. Programmable Stream Processors. IEEE Computer, 2003, 36(8): 54～62
[289] Kozyrakis C. Scalable Vector Media-processors for Embedded Systems: Ph.D Thesis. University of California at Berkeley, Spring 2002
[290] Hwang K., Xu Z., Arakawa M. Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing. IEEE Transaction on Parallel and Distributed Systems, 1996, 7(5): 522～536
[291] Bailey D. H., Barszcz E., Barton J. T., et al. The NAS parallel benchmarks - summary and preliminary results. In Proc. of Supercomputing '91, November 18-22, 1991. Albuquerque, NM, USA: IEEE CS, 1991. 158～165
[292] Swaminathan V., Chakrabarty K., Iyengar S. S. Dynamic I/O power management for hard real-time systems. In Proc. of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, 2001. Copenhagen, Denmark: ACM Press, 2001. 237～242
[293] Benini L., Micheli G. de. System-level power optimization: techniques and tools. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2000, 5(2): 115～192
[294] Hsu C., Kremer U. Compiler-Directed dynamic voltage scaling based on program regions:Tech Report. DCSTR-461. Rutgers University, November 2001. 1～9
[295] Casmira J., Grunwald D. Dynamic instruction scheduling slack. In Proc. of the 2000 KoolChips Workshop, Held in Conjunction with MICRO-00, 10-13December 2000. Monterey, California, USA, 2000. 1～7
[296] Hu J., Marculescu R. Energy- and Performance-Aware Mapping for Regular NoC Architectures. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24(4): 551～562
[297] burd T. D., brodersen R. W. Design Issues for Dynamic Voltage Scaling. In Proc. of the 2000 international symposium on low power electronics and design, July 25-27, 2000. Rapallo, Italy: ACM Press, 2000. 9～14
[298] Puschner P., Burns A. A Review of Worst-Case Execution-Time Analysis (Editorial). Journal of Real-Time Systems, 1999, 18(2/3): 115～128
[299] Mueller F. Static Cache Simulation and its Applications: Ph.D Thesis. Dept. of Computer Science, Florida State University, July 12, 1994
[300] Colin A., Puaut I. Worst Case Execution Time Analysis for a Processor with Branch Prediction. Real-Time System, 2000, 18(2/3): 249～274
[301] 刘喆. 基于WCET分析的低功耗技术研究: 硕士论文. 国防科学技术大学研究生院, 二○○五年十一月
[302] Zhu D., Melhem R., Childers B. R. Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multiprocessor Real-Time Systems. IEEE Transactions on Parallel and Distributed Systems, 2003, 14(7): 686～700
[303] Snu . SNU Real-Time Benchmarks:Seoul National University, 2004 Get from http://archi.snu.ac.kr/realtime/benchmark/.
[304] Shin D., Kim J. Look-ahead Intra-Task Voltage Scheduling Using Data Flow Information. In Proc. of the International SOC Design Conference (ISOCC'04), October 25-26. Seoul, Korea, 2004. 148～151
[305] Aboughazaleh N., Mosse D., Childers B., et al. Toward the placement of power management points in real-time applications. In: Compilers and Operating Systems for Low Power. : Kluwer Academic Publishers, 2002. 1～17
[306] Ball T., Larus J. R. Using paths to measure, explain, and enhance program behavior. IEEE Computer, 2000, 33(7): 57～65
[307] Stallman R. M. Using the GNU Compiler Collection, GCC Version 4.0.2:GCC Developer Community, 2005.
[308] Zhu D., Mosse D., Melhem R. Power Aware Scheduling for AND/OR Graphs in Real-Time Systems. IEEE Trans. On Parallel and Distributed Systems, 2004, 15(9): 849～864
[309] Ishihara T., Yasuura H. Voltage Scheduling Problem for Dynamically Variable Voltage Processors. In Proc. of the 1998 international symposium on Low power electronics and design, 1998. Monterey, California, USA: ACM Press, New York, NY, 1998. 197～202
[310] Wakabayashi M., Amano H. Environment for Multiprocessor Simulator Development. In Proc. of Fifth International Symposium on Parallel Architectures, Algorithms, and Networks, Dec 2000. Dallas/Richardson, TX, USA: IEEE CS, 2000. 64～71
[311] Radhakrishnan R., Pankratz J. Introducing DDR2 Memory in Eighth-Generation Dell PowerEdge Servers for Improved Performance:Dell Power Solutions, October 2004.
[312] Inc V. InfiniBand: The Next Step in High Performance Computing:Voltaire Inc,February 2003.
[313] Thakur R., Rabenseifner R., Gropp W. Optimization of Collective Communication Operations in MPICH. International Journal of High Performance Computing Applications, 2005, 19(2): 119～128
[314] Miller S. Implementing Optimized Collective Communication Routines on the IBM BlueGene/L Supercomputer:Tech Report. CS425. Iowa State University, Spring 2005.
[315] Kielmann T., Hofman R. F. H., Bal H. E., et al. MagPIe: MPI's Collective Communication Operations for Clustered Wide Area Systems. In Proc. of the 1999 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'99), 4-6 May 1999. Atlanta, Georgia: ACM Press, 1999. 131～140
[316] Thies W., Karczmarek M., Amarasinghe S. P. StreamIt: A Language for Streaming Applications. In Proc. of Compiler Construction, 11th International Conference, CC 2002, April 8-12, 2002. Grenoble, France: Springer, 2002. 179～196
[317] Saavedra-barrera R. H. Machine Characterization and Benchmark Performance Prediction:Tech Report. UCB/CSD-88-437. University of California, Berkeley, June 30, 1988.
[318] Bailey D. H., Barszcz E., Barton J. T., et al. The NAS Parallel Benchmarks. International Journal of Supercomputer Applications and High Performance Computing, 1991, 5(3): 63～73
[319] Mukherjee S. S., Bannon P., Lang S., et al. The Alpha 21364 network architecture. IEEE Micro, 2002, 22(1): 26～35
[320] Steinmacher-burow B. The Blue Gene/L Supercomputer:[presentation]. IBM Boblingen, DESYHamburg, Feb 21, 2005.
[321] Svensson C., Caputa P. High-bandwidth low-latency global interconnect. VLSI Circuits and Systems, Proceedings of the SPIE, 2003, 5117: 126～134
[322] Chen X., Peh L., Wei G., et al. Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. In Proc. of 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005. San Francisco, CA, USA: IEEE CS, 2005. 120～131
[323] Ye T. T., Micheli G. de, Benini L. Analysis of power consumption on switch fabrics in network routers. In Proc. of the 39th Design Automation Conference, DAC 2002, June 10-14, 2002. New Orleans, LA, USA: ACM Press, 2002. 524～529
[324] Kim E. J., Link G. M., Yum K. H., et al. A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Transactions on Computers, 2005, 54(6): 660～671
[325] Kim E. J., Yum K. H., Link G. M., et al. Energy optimization techniques in cluster interconnects. In Proc. of the 2003 International Symposium on Low Power Electronics and Design, 2003, August 25-27, 2003. Seoul, Korea: ACM Press, 2003. 459～464
[326] Shang L., Peh L., Jha N. K. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In Proc. of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), February8-12, 2003. Anaheim, California, USA: IEEE CS, 2003. 91～102
[327] Shin D., Kim J. Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links. In Proc. of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, September 8-10, 2004. Stockholm, Sweden: ACM Press, 2004. 170～175
[328] Soteriou V., Eisley N., Peh L. Software-directed power-aware interconnection networks. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24-27, 2005. San Francisco, California, USA: ACM Press, 2005. 274～285
[329] Soteriou V., Peh L. Design-Space Exploration of Power-Aware On/Off Interconnection Networks. In Proc. of 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004. San Jose, CA, USA: IEEE CS, 2004. 510～517
[330] Chen G., Li F., Kandemir M. T. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2006, January 11-13, 2006. Charleston, South Carolina, USA: ACM Press, 2006. 194～205
[331] Li F., Chen G., Kandemir M., et al. Compiler-Directed Proactive Power Management for Networks. In Proc. of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, September 24–27, 2005. San Francisco, California, USA: ACM Press, 2005. 137～146
[332] Jurczyk M. Interconnection Networks for Parallel Computers. In: Webster J. G., ed. Wiley Encyclopedia of Electrical and Electronics Engineering. New York: John Wiley & Sons, Inc., 1999. 555～564
[333] Ni L. M., Mckinley P. K. A Survey of Wormhole Routing Techniques in Direct Networks. IEEE Computer, 1993, 26(2): 62～76
[334] JoséDuato. A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks. IEEE Transactions on Parallel and Distributed Systems, 1995, 6(10): 1055～1067
[335] Puente V., Jos é AGregorio, Ram ó nBeivide, et al. On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 2003, 14(5): 487～501
[336] Kim J., Horowitz M. A. Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In Proc. of International Solid-State Circuits Conference, 2002, Feb. 2002. San Francisco, CA: IEEE CS, 2002. 216～480
[337] Wei G., Kim J., Liu D., et al. A variable-frequency parallel I/O interface with adaptive power-supply regulation. Journal of Solid-State Circuits, 2000, 35(11): 1600–1610
[338] Duarte D. E., Vijaykrishnan N., Irwin M. J. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10(6): 844～855
[339] 阿霍, 塞西, 厄尔曼. 编译原理技术与工具. 北京: 人民邮电出版社, 2002.1～796
[340] Peh L. FLOW CONTROL AND MICRO-ARCHITECTURAL MECHANISMS FOR EXTENDING THE PERFORMANCE OF INTERCONNECTION NETWORKS: Ph.D Thesis. STANFORD UNIVERSITY, August 2001