单片开关电源管理集成电路设计
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摘要
单片式开关电源管理集成电路是国际最新技术进展，它具有高集成度、高性价比、最简外围电路、最佳性能指标、能构成高效率电源等优点，得到了广泛应用。本文目的为设计一种采用PWM工作方式的单片式高频开关电源管理集成电路。该电路最大输出功率10W，工作频率100KHz，内部集成耐压700V的功率LDMOS，并具有过热、过流保护功能，配以简单的外部元件即能构成完整的开关电源。
本论文完成了电路设计、功率器件设计、工艺设计和部分版图。整体电路的模拟表明电路完成了设计功能，达到设计指标；功率器件耐压满足要求，给出了满足导通电阻要求的版图设计尺寸；采用与传统外延工艺相区别的单晶衬底工艺来实现该电路。
在电路设计中，作者首先阐述了PWM工作方式的基本原理，给出理论依据；然后根据功能需要进行了电路的总体结构设计，结合使用条件说明工作过程，再对电路的工作频率、过热保护、抗EMI措施等进行了详细分析，完成了每个具体功能电路和整体电路的设计，最后进行了与外电路联合仿真，得到符合设计要求的结果。
对一种单晶型横向高压器件进行研究，它以深结扩散的N阱作漂移区，应用双RESURF技术等多种终端结构提高LDMOS的耐压，降低导通电阻。经过数值分析方法对耐压和导通电阻的关系进行分析仿真，得到了耐压720V导通电阻77.8Ω·cm的LDMOS管结构参数。
在工艺设计中，采用新型BiCMOS工艺在单晶衬底上实现了低压控制电路和功率器件的集成，省略了外延工序和对通隔离。文中给出了简明工艺流程和版图设计规则考虑，完成了功率器件和部分低压电路的版图。
Single-chip switching power supply management Integrated Circuit (1C) is the latest evolve in the world, it has the virtues of high integration level, most cost effective, lowest component count switcher solution, high performance, forming high efficiency power supply and so on. It has widely application over the world. The object of this paper is to design such a single chip 1C working at high frequency with pulse width modulation (PWM) mode. A lateral double-diffusion MOS with breakdown voltage exceeds 700V is integrated on chip, the maximum output power is about 10W, working frequency is fixed at 100KHz. It has functions to protect itself against over temperature and over current. Cooperating with simple periphery component, a full switch power supply is formed.
Circuit designing, key device designing, process designing and part of layout has been finished. Simulation of the whole circuit indicates that the 1C has achieved our expectation including function and parameter target; the key device satisfies breakdown voltage, and the layout design of the LDMOS is given; a process different from conventional epitaxial one is taken to fabricate the power management 1C, it manufacture devices and circuits on a single crystal substrate.
During circuit designing, the basic theory of pulse width modulation (PWM) mode is given first. Then the general structure of the 1C is designed based on it's function requirement. Combined with it's work condition, the working course is showed, some key parameters is analyzed in detail such as working frequency, over temperature protection, the way how to low EMI and so on. Every sub-circuit is designed and simulated by author. At last, combined with periphery component, the circuit is simulated, and the result meets the original requirement.
An LDMOS is researched as key device, it is fabricated through a single crystal process instead of conventional epitaxial process. The drift region of LDMOS is formed by n-type impurity deep diffusion. Multi termination technology is applied to improve the breakdown voltage, and decrease Ron, that includes RESURF. The
H
structure parameter of LDMOS is obtain through numeric simulation, whose breakdown voltage is 720V and Ron equals 77.8 & -cm.
In order to realize the switching power supply management Integrated Circuit, a novel BiCMOS process is introduced, and the conventional epitaxial procedure is abandoned. In this process, low voltage circuit and high voltage power device is integrated on a single crystal substrate. The simplified process flow and layout design rule is given. The author accomplished the layout of LDMOS and part of other low voltage circuit.
本论文完成了电路设计、功率器件设计、工艺设计和部分版图。整体电路的模拟表明电路完成了设计功能，达到设计指标；功率器件耐压满足要求，给出了满足导通电阻要求的版图设计尺寸；采用与传统外延工艺相区别的单晶衬底工艺来实现该电路。
在电路设计中，作者首先阐述了PWM工作方式的基本原理，给出理论依据；然后根据功能需要进行了电路的总体结构设计，结合使用条件说明工作过程，再对电路的工作频率、过热保护、抗EMI措施等进行了详细分析，完成了每个具体功能电路和整体电路的设计，最后进行了与外电路联合仿真，得到符合设计要求的结果。
对一种单晶型横向高压器件进行研究，它以深结扩散的N阱作漂移区，应用双RESURF技术等多种终端结构提高LDMOS的耐压，降低导通电阻。经过数值分析方法对耐压和导通电阻的关系进行分析仿真，得到了耐压720V导通电阻77.8Ω·cm的LDMOS管结构参数。
在工艺设计中，采用新型BiCMOS工艺在单晶衬底上实现了低压控制电路和功率器件的集成，省略了外延工序和对通隔离。文中给出了简明工艺流程和版图设计规则考虑，完成了功率器件和部分低压电路的版图。
Single-chip switching power supply management Integrated Circuit (1C) is the latest evolve in the world, it has the virtues of high integration level, most cost effective, lowest component count switcher solution, high performance, forming high efficiency power supply and so on. It has widely application over the world. The object of this paper is to design such a single chip 1C working at high frequency with pulse width modulation (PWM) mode. A lateral double-diffusion MOS with breakdown voltage exceeds 700V is integrated on chip, the maximum output power is about 10W, working frequency is fixed at 100KHz. It has functions to protect itself against over temperature and over current. Cooperating with simple periphery component, a full switch power supply is formed.
Circuit designing, key device designing, process designing and part of layout has been finished. Simulation of the whole circuit indicates that the 1C has achieved our expectation including function and parameter target; the key device satisfies breakdown voltage, and the layout design of the LDMOS is given; a process different from conventional epitaxial one is taken to fabricate the power management 1C, it manufacture devices and circuits on a single crystal substrate.
During circuit designing, the basic theory of pulse width modulation (PWM) mode is given first. Then the general structure of the 1C is designed based on it's function requirement. Combined with it's work condition, the working course is showed, some key parameters is analyzed in detail such as working frequency, over temperature protection, the way how to low EMI and so on. Every sub-circuit is designed and simulated by author. At last, combined with periphery component, the circuit is simulated, and the result meets the original requirement.
An LDMOS is researched as key device, it is fabricated through a single crystal process instead of conventional epitaxial process. The drift region of LDMOS is formed by n-type impurity deep diffusion. Multi termination technology is applied to improve the breakdown voltage, and decrease Ron, that includes RESURF. The
H
structure parameter of LDMOS is obtain through numeric simulation, whose breakdown voltage is 720V and Ron equals 77.8 & -cm.
In order to realize the switching power supply management Integrated Circuit, a novel BiCMOS process is introduced, and the conventional epitaxial procedure is abandoned. In this process, low voltage circuit and high voltage power device is integrated on a single crystal substrate. The simplified process flow and layout design rule is given. The author accomplished the layout of LDMOS and part of other low voltage circuit.
引文
[1]陈星弼．功率MOSFET和高压集成电路．南京：东南大学出版社1990
[2]沙占友．新型单片开关电源的设计与应用．北京：电子工业出版社2001
[3]蔡宣三，龚绍文．高频功率电子学(直流-直流变换部分)．北京：科学出版社1993
[4]Gaboriault, M.T. The global market for power supply and power management integrated circuits Applied Power Electronics Conference and Exposition, 1999. APEC '99. Fourteenth Annual, Volume: 1, 1999 Page(s): 43-48 vol. 1
[5]Yue-Chung Wong; On-Cheong Mak; Ioinovici. A. Development of boost converter based on switched-capacitor circuits, Computer, Communication, Control and Power Engineering. Proceedings. TENCON'93., 1993 IEEE Region 10 Conference on Part: 50000, 1993 Page(s): 522-525 vol.5
[6]张波，陈星弼，李肇基，“JTE结的二维电场分析”，半导体学报，Vol．14，No．10，pp．626-631，1993
[7]张开华．半导体集成电路．成都：电子科技大学出版社1995
[8]杨健．功率集成电路中的高压横向MOS晶体管：[博士学位论文]．成都：电子科技大学1999
[9]杨泓．50MHz 8-bit二步式A／D转换器：[硕士学位论文]．成都：电子科技大学2001
[10]李鸿雁．三相高压MOS栅驱动集成电路：[硕士学位论文]．成都：电子科技大学2001
[11]Power integrated公司．产品手册．Power integrated公司2000
[12]T. R Chow, D. N. Pattanayak, B. J. Baliga and M. S. Alder,"Latching in lateral insulated gate bipolar transistor", IEDM Tech. Dig., pp. 774-777, 1987
[13]A.L. Robinson, D. N. Pattanayak, M. S. Adler, et al.,"Lateral insulated gate transistors with improved latching characteristics", IEEE Electron Device Letters, Vol. 7, No. 2, pp.61-63, 1986
[14]J. A. Appels and H. M. J. Vaes,"High-voltage thin layer devices", IEDM Tech. Dig., pp. 238-241, 1979
[15]A. W. Ludikhuize,"High-voltge DMOS and PMOS in analog IC's", IEDM Tech. Dig., pp.81-84, 1982
[16]Z. J. Li, X. B. Chen et. al. Calculation of electric field profile of high voltage devices with Junction termination extension. Proc. ICSICT, Oct, P.462. 1989
[17]Mike F. Chang, George Pifer, Hamza Yilmaz, et al.,"Lateral HVIC with 1200-V bipolar and field-effect devices", IEEE Tran. Electron Devices, Vol. ED-33, pp. 1992-2001, 1986
[18] Jose G. Mena and C. A. T. Salama, "High-voltage multiple-resistivity drift-region LDMOS", Solid-State Electronics, Vol. 29, No. 6, pp. 647-656, 1986
[19] Z. Parpia, C. Andre ang T.Salama, "Optimization of the breakdown voltage in RESURF LDMOSTs", in Proc. Symp. on High Voltage and Smart Power IC's, pp. 23-31, 1989
[21] E. M. Sankara Narayanan, G. Amaratunga and W. L. Milne, "A study of the RESURF principle for thin epitaxial layer high voltage integrated circuits", Proc. of ISPSD, pp. 172-175, 1992
[22] K.Board and M. Darwish, "LDMOS transistors with implanted and deposited surface layers", IEE Proceedings, Vol. 132, Pt. 1, No.4, Augest, 1985
[23] G. Charitat, M. A. Bouanane and P. Rossel, "A new junction termination technique for power devices: RESURF LDMOS with SIPOS layers", Proc. of ISPSD, pp. 213-216,1992
[24] T. Sakai, K. C. So, Z. Shen and T. P. Chow, "Modeling and characterization of SIPOS passivated, high voltage, N-and P-channel lateral RSURF type DMOSFETs", Proc. of ISPSD, pp. 288-292, 1992
[25] D. Jaume, G. Charitat, J. M. Reynes and P. Rossel, "High-voltage planar devices using field plate and semi-resistive layers", IEEE Iran. Electron Devices, Vol. ED-38, No.7, pp. 1681-1684, 1991
[26] X. B. Chen, B. Zhang and Z. J. Li, "Theory of optimum design of reverse-biased p-n junctions using resistive field plates and variation lateral doping", Solid-State Electronics, Vol. 35, No. 9, pp. 1365-1370, 1992
[27] Serag E.D. Habib."The ALDMOST:A New Power MOS Transistor",IEEE Tran. ED Lett. Vol.8 No.6 pp257-259,1987
[28] A. Nezar and C. A. T. Salama, "Breakdown voltage in LDMOS transistors using internal field rings", IEEE Tran. Electron Devices, Vol. ED-38, No. 7, pp. 1676-1680, 1991
[29] J. S. Ajit, Dan Kinzer and Niraj Ranjan, "1200V high-side lateral MOSFET in junction-isolatedpower IC technology using two field-reduction layers", Proc. of ISPSD, pp. 230-2235, 1993
[30] J. A. Appels, M. G. Collet, P. A. H. Hart, et al., "Thin layer high-voltage devices (resurf devices)", Philips Journal of Research Vol. 35, No. 1, pp. 1-13, 1980
[31] X. B. Chen, P. A. Mawby, C. A. T. Salama, M. S. Towers, J. Zeng and K. Board, "Lateral high-village devices using an optimized variational lateral doping", Int. J. Electronics, Vol. 80, No. 3, pp. 449-459,1996
[32] H. M. J. Vaes and J. A. Apples, "High voltage, high current lateral devices", IEDM Tech. Dig., pp. 87-90,1980
[33] H. Yilmaz, "Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions", IEEE Tran. Electron Devices, Vol. 38, pp. 1666-1675, 1991
[2]沙占友．新型单片开关电源的设计与应用．北京：电子工业出版社2001
[3]蔡宣三，龚绍文．高频功率电子学(直流-直流变换部分)．北京：科学出版社1993
[4]Gaboriault, M.T. The global market for power supply and power management integrated circuits Applied Power Electronics Conference and Exposition, 1999. APEC '99. Fourteenth Annual, Volume: 1, 1999 Page(s): 43-48 vol. 1
[5]Yue-Chung Wong; On-Cheong Mak; Ioinovici. A. Development of boost converter based on switched-capacitor circuits, Computer, Communication, Control and Power Engineering. Proceedings. TENCON'93., 1993 IEEE Region 10 Conference on Part: 50000, 1993 Page(s): 522-525 vol.5
[6]张波，陈星弼，李肇基，“JTE结的二维电场分析”，半导体学报，Vol．14，No．10，pp．626-631，1993
[7]张开华．半导体集成电路．成都：电子科技大学出版社1995
[8]杨健．功率集成电路中的高压横向MOS晶体管：[博士学位论文]．成都：电子科技大学1999
[9]杨泓．50MHz 8-bit二步式A／D转换器：[硕士学位论文]．成都：电子科技大学2001
[10]李鸿雁．三相高压MOS栅驱动集成电路：[硕士学位论文]．成都：电子科技大学2001
[11]Power integrated公司．产品手册．Power integrated公司2000
[12]T. R Chow, D. N. Pattanayak, B. J. Baliga and M. S. Alder,"Latching in lateral insulated gate bipolar transistor", IEDM Tech. Dig., pp. 774-777, 1987
[13]A.L. Robinson, D. N. Pattanayak, M. S. Adler, et al.,"Lateral insulated gate transistors with improved latching characteristics", IEEE Electron Device Letters, Vol. 7, No. 2, pp.61-63, 1986
[14]J. A. Appels and H. M. J. Vaes,"High-voltage thin layer devices", IEDM Tech. Dig., pp. 238-241, 1979
[15]A. W. Ludikhuize,"High-voltge DMOS and PMOS in analog IC's", IEDM Tech. Dig., pp.81-84, 1982
[16]Z. J. Li, X. B. Chen et. al. Calculation of electric field profile of high voltage devices with Junction termination extension. Proc. ICSICT, Oct, P.462. 1989
[17]Mike F. Chang, George Pifer, Hamza Yilmaz, et al.,"Lateral HVIC with 1200-V bipolar and field-effect devices", IEEE Tran. Electron Devices, Vol. ED-33, pp. 1992-2001, 1986
[18] Jose G. Mena and C. A. T. Salama, "High-voltage multiple-resistivity drift-region LDMOS", Solid-State Electronics, Vol. 29, No. 6, pp. 647-656, 1986
[19] Z. Parpia, C. Andre ang T.Salama, "Optimization of the breakdown voltage in RESURF LDMOSTs", in Proc. Symp. on High Voltage and Smart Power IC's, pp. 23-31, 1989
[21] E. M. Sankara Narayanan, G. Amaratunga and W. L. Milne, "A study of the RESURF principle for thin epitaxial layer high voltage integrated circuits", Proc. of ISPSD, pp. 172-175, 1992
[22] K.Board and M. Darwish, "LDMOS transistors with implanted and deposited surface layers", IEE Proceedings, Vol. 132, Pt. 1, No.4, Augest, 1985
[23] G. Charitat, M. A. Bouanane and P. Rossel, "A new junction termination technique for power devices: RESURF LDMOS with SIPOS layers", Proc. of ISPSD, pp. 213-216,1992
[24] T. Sakai, K. C. So, Z. Shen and T. P. Chow, "Modeling and characterization of SIPOS passivated, high voltage, N-and P-channel lateral RSURF type DMOSFETs", Proc. of ISPSD, pp. 288-292, 1992
[25] D. Jaume, G. Charitat, J. M. Reynes and P. Rossel, "High-voltage planar devices using field plate and semi-resistive layers", IEEE Iran. Electron Devices, Vol. ED-38, No.7, pp. 1681-1684, 1991
[26] X. B. Chen, B. Zhang and Z. J. Li, "Theory of optimum design of reverse-biased p-n junctions using resistive field plates and variation lateral doping", Solid-State Electronics, Vol. 35, No. 9, pp. 1365-1370, 1992
[27] Serag E.D. Habib."The ALDMOST:A New Power MOS Transistor",IEEE Tran. ED Lett. Vol.8 No.6 pp257-259,1987
[28] A. Nezar and C. A. T. Salama, "Breakdown voltage in LDMOS transistors using internal field rings", IEEE Tran. Electron Devices, Vol. ED-38, No. 7, pp. 1676-1680, 1991
[29] J. S. Ajit, Dan Kinzer and Niraj Ranjan, "1200V high-side lateral MOSFET in junction-isolatedpower IC technology using two field-reduction layers", Proc. of ISPSD, pp. 230-2235, 1993
[30] J. A. Appels, M. G. Collet, P. A. H. Hart, et al., "Thin layer high-voltage devices (resurf devices)", Philips Journal of Research Vol. 35, No. 1, pp. 1-13, 1980
[31] X. B. Chen, P. A. Mawby, C. A. T. Salama, M. S. Towers, J. Zeng and K. Board, "Lateral high-village devices using an optimized variational lateral doping", Int. J. Electronics, Vol. 80, No. 3, pp. 449-459,1996
[32] H. M. J. Vaes and J. A. Apples, "High voltage, high current lateral devices", IEDM Tech. Dig., pp. 87-90,1980
[33] H. Yilmaz, "Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions", IEEE Tran. Electron Devices, Vol. 38, pp. 1666-1675, 1991