RISC微控制器的设计与标准化
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摘要
本论文主要介绍了8位精简指令集计算机微控制器(RISC MCU)的设计实现与标准化。该课题来源于十五国防预研项目“SoC在新一代战斗机的应用”。
本课题的主要研究内容为设计一款与Microchip的PICl6CXXX系列微控制器的指令系统完全兼容的，有自主知识产权的标准8位RISC MCU IP软核。
论文主要内容包括以下几方面：
1．根据功能需求以及对PIC16CXXX指令系统的详细分析，对RISC MCU进行总体设计以及具体的模块划分。
2．介绍MCU核控制通路的具体设计，包括控制模块，指令译码部分以及中断控制模块的详细分析与设计。
3．介绍MCU核的外围功能部件的具体设计，包括捕捉／比较／脉宽调制输出(CCP)部件与I2C总线控制器的的详细分析与设计。
4．对当今比较通用的IP标准做一简单介绍，并主要讨论了本MCU核的标准化设计问题。
5．通过编写测试激励程序完成了对系统的功能仿真、综合与布局布线。
通过本论文的研究，完成了8位RISC微控制器的设计与仿真综合，并对如何使其成为可复用的IP软核进行了讨论，为使用该MCU核进行更复杂的SoC设计提供了良好的基础。
This paper mainly discussed the design and standardization of 8 bit RISC microcontroller. The high level design methodology was used to implement it. It analyzed every step of the integration and the design flow of this methodology, with a focus on the design. This subject was supported by the national defence project--"The Applications of SoC In The New Generation Battleplan" .
The main research content of this subject is to design an 8 bit RISC MCU core, which has the independent intellectual property right. The instruction system of this MCU and the PIC16CXXX microcontroller's are totally compatible.
There are mainly five parts in this paper.
1. At the function demand and the analyses of instruction system, we finished the architecture design and the division of the function modules.
2. Introducing the analyse and design of the control path in detail, including the control module, instruction code module and interrupt control module.
3. Introducing the analyse and design of the periphery function parts in detail, including the Compare/Capture/PWM part and the I2C bus controller.
4. After simple introduction of the current IP standard , we discuss the standardization of our RISC MCU core.
5. We finished the functional simulation with the testing programs , synthesized the system with EDA tools and then implement it in FPGA device.
This paper not only introduced the design of RISC MCU core ,but also discussed its standardization. That has contributed a lot to the design of the more complex SoC design.
本课题的主要研究内容为设计一款与Microchip的PICl6CXXX系列微控制器的指令系统完全兼容的，有自主知识产权的标准8位RISC MCU IP软核。
论文主要内容包括以下几方面：
1．根据功能需求以及对PIC16CXXX指令系统的详细分析，对RISC MCU进行总体设计以及具体的模块划分。
2．介绍MCU核控制通路的具体设计，包括控制模块，指令译码部分以及中断控制模块的详细分析与设计。
3．介绍MCU核的外围功能部件的具体设计，包括捕捉／比较／脉宽调制输出(CCP)部件与I2C总线控制器的的详细分析与设计。
4．对当今比较通用的IP标准做一简单介绍，并主要讨论了本MCU核的标准化设计问题。
5．通过编写测试激励程序完成了对系统的功能仿真、综合与布局布线。
通过本论文的研究，完成了8位RISC微控制器的设计与仿真综合，并对如何使其成为可复用的IP软核进行了讨论，为使用该MCU核进行更复杂的SoC设计提供了良好的基础。
This paper mainly discussed the design and standardization of 8 bit RISC microcontroller. The high level design methodology was used to implement it. It analyzed every step of the integration and the design flow of this methodology, with a focus on the design. This subject was supported by the national defence project--"The Applications of SoC In The New Generation Battleplan" .
The main research content of this subject is to design an 8 bit RISC MCU core, which has the independent intellectual property right. The instruction system of this MCU and the PIC16CXXX microcontroller's are totally compatible.
There are mainly five parts in this paper.
1. At the function demand and the analyses of instruction system, we finished the architecture design and the division of the function modules.
2. Introducing the analyse and design of the control path in detail, including the control module, instruction code module and interrupt control module.
3. Introducing the analyse and design of the periphery function parts in detail, including the Compare/Capture/PWM part and the I2C bus controller.
4. After simple introduction of the current IP standard , we discuss the standardization of our RISC MCU core.
5. We finished the functional simulation with the testing programs , synthesized the system with EDA tools and then implement it in FPGA device.
This paper not only introduced the design of RISC MCU core ,but also discussed its standardization. That has contributed a lot to the design of the more complex SoC design.
引文
[1] PIC16C63A/65B/73B/74B Data Sheet, Microchip Technology Inc,2000.
[2] Apex20k Programmable Logic Device Family Data Sheet,Altera Inc.,February 2002.
[3] Specification for the WISHBONE System-on-Chip(SoC) Interconnection Architecture for portable IP Cores, Revision:B.3,Released:September 7,2002.
[4] OpenCores SoC Bus Review, Rudolf Usselmann,
[5] The Verilog Golden Reference Guide,August 1996.
[6] FPGA Design Methodologies for High-Performance Application, LEONG Monk Ping
[7] Synthesizable Verilog syntax and semantics, Mike Gordon
[8] The I2C-bus specification version 2.1, January 2000
[9] Nios Embedded Processor Data Sheet,Altera Corporation,March 2001,Verl. 1.
[10] Designing safe verilog state machines with synplify,Synplicity Inc,1999.
[11] State Machine Coding Styles for Synthesis, Clifford E. Cummings
[12] Wayne Wolf: Modem VLSI Design:System-on-Chip Design,2003.
[13] ZANYANG,Semi-Reconfigurable Data-Path:Design and Verification, May 2001.
[14] J.BHASKER,VerilogHDL Synthesis: A Practical Primer,Lucent Technologies,1998.
[15] QUSARTus Tutorial,Altera Corporation,November 1999.
[16] http://www.microchip.com.
[17] http://www.opencores.org.
[18] http://www.goldenchip.com.cn/
[19] http://www.fpga.com
[20] http://www.ewbbs.com/ewbbs/
[21] http://www.eetchina.com/
[22] VSIA IP标准
[23] 白中英：计算机组成原理，科学出版社，1994。
[24] 郑纬民、陈修环、石岩、汤志忠：计算机系统结构(第二版)，北京清华大学出版社，1998年。
[25] 李学海：PIC单片机实用教程—提高篇，北京航空航天大学出版社，2002年9月。
[26] 窦振中：PIC系列单片机原理和程序设计，北京航空航天大学出版社，2001年10月。
[27] Donald E. Thomas & Philip R. Moorby著，刘明业、蒋敬旗、刁岚松等译：硬件描述语言Verilog(第四版)，清华大学出版社，2001年8月。
[28] 李丽、高明伦、张多利、程作仁：8位RISC微控制器IP软核的设计
[29] 牛风举、刘元成、朱明程：基于IP复用的数字IC设计技术，电子工业出版社，2003年9月。
[30] 李哲英 骆丽：单片机与嵌入式系统应用，SOC与单片机应用技术的发展。
[31] 微电子学与计算机，2001，第3期。
[32] 朱霞：P1750A微处理器数据通路设计实现，西北工业大学硕士学位论文，2001。
[33] 夏宇闻：复杂数字电路与系统的Verilog HDL设计技术，北京航空航天大学出版社，1999年。
[34] 孙富明：基于多种EDA工具的FPGA设计，国防科技大学。
[35] 杨之廉、申明：超大规模集成电路设计方法学导论(第二版)，清华大学出版社，1999年。
[2] Apex20k Programmable Logic Device Family Data Sheet,Altera Inc.,February 2002.
[3] Specification for the WISHBONE System-on-Chip(SoC) Interconnection Architecture for portable IP Cores, Revision:B.3,Released:September 7,2002.
[4] OpenCores SoC Bus Review, Rudolf Usselmann,
[5] The Verilog Golden Reference Guide,August 1996.
[6] FPGA Design Methodologies for High-Performance Application, LEONG Monk Ping
[7] Synthesizable Verilog syntax and semantics, Mike Gordon
[8] The I2C-bus specification version 2.1, January 2000
[9] Nios Embedded Processor Data Sheet,Altera Corporation,March 2001,Verl. 1.
[10] Designing safe verilog state machines with synplify,Synplicity Inc,1999.
[11] State Machine Coding Styles for Synthesis, Clifford E. Cummings
[12] Wayne Wolf: Modem VLSI Design:System-on-Chip Design,2003.
[13] ZANYANG,Semi-Reconfigurable Data-Path:Design and Verification, May 2001.
[14] J.BHASKER,VerilogHDL Synthesis: A Practical Primer,Lucent Technologies,1998.
[15] QUSARTus Tutorial,Altera Corporation,November 1999.
[16] http://www.microchip.com.
[17] http://www.opencores.org.
[18] http://www.goldenchip.com.cn/
[19] http://www.fpga.com
[20] http://www.ewbbs.com/ewbbs/
[21] http://www.eetchina.com/
[22] VSIA IP标准
[23] 白中英：计算机组成原理，科学出版社，1994。
[24] 郑纬民、陈修环、石岩、汤志忠：计算机系统结构(第二版)，北京清华大学出版社，1998年。
[25] 李学海：PIC单片机实用教程—提高篇，北京航空航天大学出版社，2002年9月。
[26] 窦振中：PIC系列单片机原理和程序设计，北京航空航天大学出版社，2001年10月。
[27] Donald E. Thomas & Philip R. Moorby著，刘明业、蒋敬旗、刁岚松等译：硬件描述语言Verilog(第四版)，清华大学出版社，2001年8月。
[28] 李丽、高明伦、张多利、程作仁：8位RISC微控制器IP软核的设计
[29] 牛风举、刘元成、朱明程：基于IP复用的数字IC设计技术，电子工业出版社，2003年9月。
[30] 李哲英 骆丽：单片机与嵌入式系统应用，SOC与单片机应用技术的发展。
[31] 微电子学与计算机，2001，第3期。
[32] 朱霞：P1750A微处理器数据通路设计实现，西北工业大学硕士学位论文，2001。
[33] 夏宇闻：复杂数字电路与系统的Verilog HDL设计技术，北京航空航天大学出版社，1999年。
[34] 孙富明：基于多种EDA工具的FPGA设计，国防科技大学。
[35] 杨之廉、申明：超大规模集成电路设计方法学导论(第二版)，清华大学出版社，1999年。