一类异构多处理器片上系统任务调度算法研究与应用
|
摘要
由于芯片制造工艺的限制，处理器频率的继续提升遇到了物理瓶颈，多处理器技术被认为是维持片上系统性能增长的有效方法。异构多处理器片上系统(Multi-Processor System-on-Chip, MPSoC)兼顾了系统的通用性与灵活性，受到了工业界和学术界的青睐，已经被广泛应用于移动通信、嵌入式多媒体等领域。对于异构MPSoC来说，其性能的充分发挥依赖于所采用的任务调度算法。高效的调度算法可以缓解处理器数目增加所带来的高能耗、高温度、高成本等问题，能够进一步扩大MPSoC的应用范围。在满足各种约束的前提下对异构MPSoC进行优化调度已经证明是NP难问题。因而，针对异构MPSoC的各种应用需求，寻求不同优化目标下的最佳调度方案，已经成为当今多处理器技术的研究热点和重点。
随着可重构技术和MPSoC的发展，出现了包含可重构资源的异构MPSoC，它兼具可重构资源的高效性和MPSoC的灵活性，为系统设计和应用提供了更多的选择。对含有可重构资源的异构MPSoC而言，任务调度时还需要完成软硬件划分，因而进一步增加了问题的复杂度。针对具有可重构功能的异构MPSoC，以充分发挥可重构资源的性能、解决异构MPSoC所面临的能耗和温度问题为出发点，分别开展软硬件优化划分算法、节能调度算法和温度感知调度算法研究。论文的具体工作如下：
(1)针对双路软硬件划分的特点，借鉴0/1背包问题的相关算法思想，基于模拟退火算法的全局寻优特性，提出了一种融合贪心算法与模拟退火算法的软硬件划分方法。该方法在研究双路软硬件划分系统结构基础上，首先将软硬件划分问题规约为0/1背包问题，采用贪心算法进行快速初始划分；然后设计一种新的接收准则，根据新解在扰动模型中的位置来计算其接收概率，基于贪心算法的预划分结果，采用改进的模拟退火算法进行全局寻优。由于该算法兼具贪心算法的高效性和模拟退火算法的全局寻优能力，从而避免了模拟退火算法初始划分难以设定的问题，在任务划分质量和算法运行时间方面均取得了较好的效果。仿真实验证明了本文所提算法的有效性。
(2)针对异构MPSoC中处理器数目增长所引起的高能耗问题，考虑遗传算法的高效搜索能力，采用动态电压缩放技术，提出了一种新的节能调度算法。该算法首先对遗传算法的选择算子和群体更新机制进行改进，增强了群体的多样性，然后基于改进的遗传算法来确定任务优先级，采用链表调度方法确定任务执行顺序；最后根据任务能量和时间关系，设计了一种新的任务缩放优先级计算方法，基于该优先级进行节能调度。该算法在具备遗传算法的高效搜索能力的同时，弥补了其容易陷入局部最优解的缺陷，并且通过对高能耗任务进行有针对性的缩放，很好地实现系统节能。
(3)针对能量密度增长给异构MPSoC所带来的温度提升，考虑漏极功率、供电电压和温度之间的关系，以系统峰值温度最小化为优化目标，提出了一种新的温度感知调度算法。温度升高将直接缩短处理器的生命周期，同时影响系统性能和使用舒适度。本文首先针对异构MPSoC应用推广所面临的温度问题，在温度与供电电压关系的基础上，考虑处理器的漏极功率，建立温度模型；然后根据任务关键路径进行初始调度，在温度模型基础上计算任务的运行温度，运用动态电压缩放技术，通过迭代操作优化系统峰值温度。该算法中所考虑的温度模型更为实际，并且直接对具有峰值温度的任务进行优化，从而能够显著降低系统峰值温度和平均温度。
(4)针对本文提出的任务调度算法，在相关嵌入式系统中进行了应用研究。针对湖南省科研条件创新专项“三维荧光光谱仪高性能数学分离关键部件研制”，进行了软硬件划分算法应用研究。该部件的核心是“数学分离”算法，涉及到大量的高维矩阵运算，在嵌入式应用中需要解决复杂计算问题。本文通过分析问题的计算特性，采用通用处理器和可重构资源相结合的方式，进行系统结构设计；然后运用本文提出的软硬件划分方法，对任务进行划分，获得了较好的系统性能。针对国家发改委项目“中国网上教育平台”子项——“移动学习平台”，进行了节能调度算法应用研究。嵌入式移动平台特别关注能耗问题，本文采用具有较好电源管理功能的PXA255芯片进行系统设计，并进行动态电压缩放技术的具体实现。在此基础上，运用本文的节能调度方法，对AVS视频解码任务进行节能调度应用研究。应用结果表明了本文算法的有效性。
Due to the limitations of the chip manufacturing process, the increasing ofprocessor frequency has encountered the physical bottleneck, multiprocessortechnology is considered to be an effective way to maintain the growth inperformance of the on-chip system. Heterogeneous multi-processor system on chip(MPSoC) owns the versatility and flexibility, has caused the common concern ofindustry and academia, and has been widely used in area s such as mobilecommunication, embedded multimedia and so on. For the heterogeneous MPSoC, itsperformance depends on the efficient task scheduling algorithm. An effectivescheduling algorithm can alleviate the problems of high energy consumption, hightemperature, high-cost which are brought by the increasing number of processors,and extend the applications of heterogeneous MPSoC. The optimal scheduling ofheterogeneous MPSoC under a variety of constraints has been proven to be NP-hardproblem. Thus, taking account of the various kinds of application req uirements ofheterogeneous MPSoC, seeking for the optimal scheduling policy for differentoptimization goals has become the focus and hot research of today's multi-processortechnology.
As the development of reconfigurable technology and the MPSoC, one kin d ofheterogeneous MPSoC which contains the reconfigurable resources has appeared.This kind of MPSoC combines the flexibility of MPSoC and the efficiency ofreconfigurable resources, and provides more alternatives for system design andapplication. For the heterogeneous MPSoC which contains reconfigurable resources,task scheduling also needs to partition the software and hardware, which increasesthe complexity of task scheduling further. Considering the heterogeneous MPSoCwhich owns the reconfigurable function, in order to take full use of thereconfigurable resources, address the energy consumption and temperature problemof the heterogeneous MPSoC, we have carried out the research of hardware/softwarepartitioning algorithm, energy-saving scheduling algorithm, and temperature-awarescheduling algorithm respectively. The specific work of the paper is as follows:
(1) According to the characteristics of the hardware/software bi-partition, takingthe algorithm of the0/1knapsack problem as a reference, a h ardware/softwarepartitioning algorithm was proposed based on the global optimization features if simulated annealing algorithm which combined the greedy algorithm and thesimulated annealing algorithm. After analyzing the system structure ofhardware/software bi-partitioning, this method reduced the hardware/softwarepartitioning problem to the0/1knapsack problem, and used the greedy algorithm todo the initial rapid partition; then designed a new acceptance criteria to calculate theprobability of acceptance according to the new position of the solution inperturbation model. Based on pre-partitioning results of the greedy algorithm, usedthe improved simulated annealing algorithm to search the global optimal solution.The proposed algorithm combines the efficiency of greedy algorithm and the globaloptimization ability of simulated annealing algorithm, and avoided the difficulty inthe initial partition of simulated annealing algorithm, and expected to have a bettereffect in the quality of the partition and running time of the algorithm. Thesimulation results show the effectiveness of the proposed algorithm.
(2) The energy consumption of heterogeneous MPSoC is becoming higher as thenumber of processors increases. Considering the efficient search capab ilities ofgenetic algorithm, using the dynamic voltage scaling techniques, we proposed a newenergy-efficient scheduling algorithm. Firstly, the algorithm improved the selectionoperator and population update mechanism of genetic firstly, which enhance th ediversity of the population. Secondly, using the improved genetic algorithm todetermine the priorities of the task, and then, determined the task execution order bylist scheduling method. Finally, according to the relationship between energy andtime of tasks, we designed a new method to calculate the scaling priority of the task,which is used in energy-efficient scheduling. The proposed algorithm is of theefficient search capabilities of genetic algorithms, and recover the defect that beingeasy to fall into local optimal solution as well. And it scales down the high-energytask, is expected to achieve better system energy.
(3) The growth of energy density in heterogeneous MPSoC causes the increase oftemperature. Considering the relationship among the drain power, supply voltage andtemperature, taking the minimizing of system peak temperature as the optimizationtarget, a new temperature-aware scheduling algorithm is proposed. The rising oftemperatures will shorten the life cycle of the processor, and affect the systemperformance and comfort at the same time. Considering the temperature problemwhich hinders the application of heterogeneous MPSoC, we took account of thedrain power of the processor and established a temperature model based on therelationship between temperature and supply voltage. We used the mission-critical path algorithm to schedule at first, calculated the operating temperature of task bythe temperature model, and used the dynamic voltage scaling techniques to optimizethe peak temperature of system by iterative operation. As the temperature model inthis thesis is more practical, and we optimized the task with a peak temperaturedirectly, the system peak temperature is expected to be efficiently reduced.
(4) Applications and researches were done on related embedded systems aboutthe proposed task scheduling algorithms. In the project that the development of thekey device based on―Mathematical Separation‖for three-dimensional fluorescencespectrometer from the Research Conditions Innovation Program of Hunan Province,the hardware/software division algorithm is applied and researched. The kernel ofthe component is the―Mathematical Separation‖algorithm, which involves a largenumber of high-dimensional matrix operations and requires works to solve theproblem of complicated computing in embedded applications. After analyzing thecomputational characteristics of the problem, a way of general processor andreconfigurable resource combined was chosen to design the system. Then theproposed hardware/software division scheme was applied to divide the tasks toobtain better performance. The application and research of energy-saving schedulingalgorithm were carried out in―Mobile Learning Platform‖, a sub-project in―ChineseOnline Education Platform‖from the National Development and ReformCommission. Power consumption is the biggest concern on embedded mobileplatforms. PXA255, a platform which has good power management, was decided tobe used to accomplish the system design. The dynamic voltage scaling technique wasimplemented. Based on that, using the proposed energy-saving scheme, the researchof the energy-saving scheduling algorithm was done on the AVS decoding task. Theresults proved the effectiveness of the proposed algorithm.
随着可重构技术和MPSoC的发展，出现了包含可重构资源的异构MPSoC，它兼具可重构资源的高效性和MPSoC的灵活性，为系统设计和应用提供了更多的选择。对含有可重构资源的异构MPSoC而言，任务调度时还需要完成软硬件划分，因而进一步增加了问题的复杂度。针对具有可重构功能的异构MPSoC，以充分发挥可重构资源的性能、解决异构MPSoC所面临的能耗和温度问题为出发点，分别开展软硬件优化划分算法、节能调度算法和温度感知调度算法研究。论文的具体工作如下：
(1)针对双路软硬件划分的特点，借鉴0/1背包问题的相关算法思想，基于模拟退火算法的全局寻优特性，提出了一种融合贪心算法与模拟退火算法的软硬件划分方法。该方法在研究双路软硬件划分系统结构基础上，首先将软硬件划分问题规约为0/1背包问题，采用贪心算法进行快速初始划分；然后设计一种新的接收准则，根据新解在扰动模型中的位置来计算其接收概率，基于贪心算法的预划分结果，采用改进的模拟退火算法进行全局寻优。由于该算法兼具贪心算法的高效性和模拟退火算法的全局寻优能力，从而避免了模拟退火算法初始划分难以设定的问题，在任务划分质量和算法运行时间方面均取得了较好的效果。仿真实验证明了本文所提算法的有效性。
(2)针对异构MPSoC中处理器数目增长所引起的高能耗问题，考虑遗传算法的高效搜索能力，采用动态电压缩放技术，提出了一种新的节能调度算法。该算法首先对遗传算法的选择算子和群体更新机制进行改进，增强了群体的多样性，然后基于改进的遗传算法来确定任务优先级，采用链表调度方法确定任务执行顺序；最后根据任务能量和时间关系，设计了一种新的任务缩放优先级计算方法，基于该优先级进行节能调度。该算法在具备遗传算法的高效搜索能力的同时，弥补了其容易陷入局部最优解的缺陷，并且通过对高能耗任务进行有针对性的缩放，很好地实现系统节能。
(3)针对能量密度增长给异构MPSoC所带来的温度提升，考虑漏极功率、供电电压和温度之间的关系，以系统峰值温度最小化为优化目标，提出了一种新的温度感知调度算法。温度升高将直接缩短处理器的生命周期，同时影响系统性能和使用舒适度。本文首先针对异构MPSoC应用推广所面临的温度问题，在温度与供电电压关系的基础上，考虑处理器的漏极功率，建立温度模型；然后根据任务关键路径进行初始调度，在温度模型基础上计算任务的运行温度，运用动态电压缩放技术，通过迭代操作优化系统峰值温度。该算法中所考虑的温度模型更为实际，并且直接对具有峰值温度的任务进行优化，从而能够显著降低系统峰值温度和平均温度。
(4)针对本文提出的任务调度算法，在相关嵌入式系统中进行了应用研究。针对湖南省科研条件创新专项“三维荧光光谱仪高性能数学分离关键部件研制”，进行了软硬件划分算法应用研究。该部件的核心是“数学分离”算法，涉及到大量的高维矩阵运算，在嵌入式应用中需要解决复杂计算问题。本文通过分析问题的计算特性，采用通用处理器和可重构资源相结合的方式，进行系统结构设计；然后运用本文提出的软硬件划分方法，对任务进行划分，获得了较好的系统性能。针对国家发改委项目“中国网上教育平台”子项——“移动学习平台”，进行了节能调度算法应用研究。嵌入式移动平台特别关注能耗问题，本文采用具有较好电源管理功能的PXA255芯片进行系统设计，并进行动态电压缩放技术的具体实现。在此基础上，运用本文的节能调度方法，对AVS视频解码任务进行节能调度应用研究。应用结果表明了本文算法的有效性。
Due to the limitations of the chip manufacturing process, the increasing ofprocessor frequency has encountered the physical bottleneck, multiprocessortechnology is considered to be an effective way to maintain the growth inperformance of the on-chip system. Heterogeneous multi-processor system on chip(MPSoC) owns the versatility and flexibility, has caused the common concern ofindustry and academia, and has been widely used in area s such as mobilecommunication, embedded multimedia and so on. For the heterogeneous MPSoC, itsperformance depends on the efficient task scheduling algorithm. An effectivescheduling algorithm can alleviate the problems of high energy consumption, hightemperature, high-cost which are brought by the increasing number of processors,and extend the applications of heterogeneous MPSoC. The optimal scheduling ofheterogeneous MPSoC under a variety of constraints has been proven to be NP-hardproblem. Thus, taking account of the various kinds of application req uirements ofheterogeneous MPSoC, seeking for the optimal scheduling policy for differentoptimization goals has become the focus and hot research of today's multi-processortechnology.
As the development of reconfigurable technology and the MPSoC, one kin d ofheterogeneous MPSoC which contains the reconfigurable resources has appeared.This kind of MPSoC combines the flexibility of MPSoC and the efficiency ofreconfigurable resources, and provides more alternatives for system design andapplication. For the heterogeneous MPSoC which contains reconfigurable resources,task scheduling also needs to partition the software and hardware, which increasesthe complexity of task scheduling further. Considering the heterogeneous MPSoCwhich owns the reconfigurable function, in order to take full use of thereconfigurable resources, address the energy consumption and temperature problemof the heterogeneous MPSoC, we have carried out the research of hardware/softwarepartitioning algorithm, energy-saving scheduling algorithm, and temperature-awarescheduling algorithm respectively. The specific work of the paper is as follows:
(1) According to the characteristics of the hardware/software bi-partition, takingthe algorithm of the0/1knapsack problem as a reference, a h ardware/softwarepartitioning algorithm was proposed based on the global optimization features if simulated annealing algorithm which combined the greedy algorithm and thesimulated annealing algorithm. After analyzing the system structure ofhardware/software bi-partitioning, this method reduced the hardware/softwarepartitioning problem to the0/1knapsack problem, and used the greedy algorithm todo the initial rapid partition; then designed a new acceptance criteria to calculate theprobability of acceptance according to the new position of the solution inperturbation model. Based on pre-partitioning results of the greedy algorithm, usedthe improved simulated annealing algorithm to search the global optimal solution.The proposed algorithm combines the efficiency of greedy algorithm and the globaloptimization ability of simulated annealing algorithm, and avoided the difficulty inthe initial partition of simulated annealing algorithm, and expected to have a bettereffect in the quality of the partition and running time of the algorithm. Thesimulation results show the effectiveness of the proposed algorithm.
(2) The energy consumption of heterogeneous MPSoC is becoming higher as thenumber of processors increases. Considering the efficient search capab ilities ofgenetic algorithm, using the dynamic voltage scaling techniques, we proposed a newenergy-efficient scheduling algorithm. Firstly, the algorithm improved the selectionoperator and population update mechanism of genetic firstly, which enhance th ediversity of the population. Secondly, using the improved genetic algorithm todetermine the priorities of the task, and then, determined the task execution order bylist scheduling method. Finally, according to the relationship between energy andtime of tasks, we designed a new method to calculate the scaling priority of the task,which is used in energy-efficient scheduling. The proposed algorithm is of theefficient search capabilities of genetic algorithms, and recover the defect that beingeasy to fall into local optimal solution as well. And it scales down the high-energytask, is expected to achieve better system energy.
(3) The growth of energy density in heterogeneous MPSoC causes the increase oftemperature. Considering the relationship among the drain power, supply voltage andtemperature, taking the minimizing of system peak temperature as the optimizationtarget, a new temperature-aware scheduling algorithm is proposed. The rising oftemperatures will shorten the life cycle of the processor, and affect the systemperformance and comfort at the same time. Considering the temperature problemwhich hinders the application of heterogeneous MPSoC, we took account of thedrain power of the processor and established a temperature model based on therelationship between temperature and supply voltage. We used the mission-critical path algorithm to schedule at first, calculated the operating temperature of task bythe temperature model, and used the dynamic voltage scaling techniques to optimizethe peak temperature of system by iterative operation. As the temperature model inthis thesis is more practical, and we optimized the task with a peak temperaturedirectly, the system peak temperature is expected to be efficiently reduced.
(4) Applications and researches were done on related embedded systems aboutthe proposed task scheduling algorithms. In the project that the development of thekey device based on―Mathematical Separation‖for three-dimensional fluorescencespectrometer from the Research Conditions Innovation Program of Hunan Province,the hardware/software division algorithm is applied and researched. The kernel ofthe component is the―Mathematical Separation‖algorithm, which involves a largenumber of high-dimensional matrix operations and requires works to solve theproblem of complicated computing in embedded applications. After analyzing thecomputational characteristics of the problem, a way of general processor andreconfigurable resource combined was chosen to design the system. Then theproposed hardware/software division scheme was applied to divide the tasks toobtain better performance. The application and research of energy-saving schedulingalgorithm were carried out in―Mobile Learning Platform‖, a sub-project in―ChineseOnline Education Platform‖from the National Development and ReformCommission. Power consumption is the biggest concern on embedded mobileplatforms. PXA255, a platform which has good power management, was decided tobe used to accomplish the system design. The dynamic voltage scaling technique wasimplemented. Based on that, using the proposed energy-saving scheme, the researchof the energy-saving scheduling algorithm was done on the AVS decoding task. Theresults proved the effectiveness of the proposed algorithm.
引文
[1] Agarwal V, Hrishikesh M S, Keckler S W, et al. Clock rate versus IPC: T he endof the road for conventional microarchitectures. In: Proc of the Int Symposiumon Computer Architecture, Canada: IEEE Computer Society,2000,248-259
[2] ITRS. The Int technology roadmap for semiconductors. www.itrs.net/Links/2009ITRS/Home2009.htm,2012-04-01
[3] Vangal S, Howard J, Ruhl G, et al. An80-tile1.28TFLOPS network-on-chip in65nm CMOS. In: Proc of the IEEE Int Solid-State Circuits Conf, San Francisco:IEEE Computer Society,2007,98-99
[4] Wentzlaff D, Griffin P, Hoffmann H, et al. On-chip interconnection architectureof the tile processor. IEEE Micro,2007,27(5):15-31
[5] TILE. TILE-Gx Processor Family. http://www.tilera.com/products/TILE-Gx.php,2012-05-14
[6] Kumar R, Tullsen D M, Jouppi N P, et al. Heterogeneous Chip Multi-processors.IEEE Computer Society,2005,38(11):32-38
[7] Li T, Paul B, Rob K, et al. Operating System Support for Overlapping-ISAHeterogeneous Multi-core Architectures. In: Proc of the16th IEEE IntSymposium on High-Performance Computer Architecture (HPCA), Bangalore:IEEE,2010,1-12
[8] Rakesh K, Dean M T, Parthasarathy R, et al. Single-ISA HeterogeneousMulti-Core Architecture for Multithreaded Workload Performance. In: Proc ofthe31st Int Symposium on Computer Architecture, Germany: IEEE ComputerSociety,2004,64-75
[9] Miquel P, Adrian C, Francisco J, et al. A Flexible Heterogeneous Multi-CoreArchitecture. In: Proc of the16th Int Conf on Parallel Architecture andCompilation Techniques, Washington, DC: IEEE Computer Society,2007,13-24
[10] Michael G. The Cell Broadband Engine: Exploiting Multiple Levels ofParallelism in a Chip Multiprocessor. Int Journal of Parallel Programming,2007,35(3):233-262
[11] Perry H W, Jamison D C, Gautham N C, et al. EXOCHI: Architecture andProgramming Environment for a Heterogeneous Multi-Core Mult ithreadedSystem. In: Proc of the ACM SIGPLAN Conf on Programming language designand implementation, San Diego: ACM,2007,156-166
[12] Abmed J, Hannu T, Wayne W. Guest Editors' Introduction: MultiprocessorSystems-on-Chip. IEEE Computer,2005,38(7):36-40
[13] Garey M R, Johnson D S. Computers and Intractability: A Guide to the Theory ofNP-Completeness. New York: W H Freeman Company,1979
[14] Viswanath R, Wakharkar V, Watwe A, et al. Thermal performance challengesfrom silicon to systems. Intel Technology Journal,2000,4(3):1-16
[15](美)克里兹著,孟宪元译.高级FPGA设计:结构、实现和优化.北京:机械工业出版社,2009
[16] Crafts J, Bogdan D, Conti D, et al. Testing the IBM Power74GHz eight coremicroprocessor. In: Proc of the IEEE Int Test Conf, Austin: IEEE,2010,1-10
[17] Pham D, Asano S, Bolliger M, et al. The design and implementation of afirst-generation CELL processor. In: Proc of the IEEE Int Solid-State CircuitsConf, San Francisco: IEEE Computer Society,2005,184-l86
[18] XILINX. Zynq-7000产品简介. http://www. xilinx. com/publications/prod_mktg/zynq7000/Product-Brief. pdf,2012-01-03
[19] INTEL.支持嵌入式计算的基于英特尔凌动处理器E6x5C系列的平台. http://www. intel.com/p/zh_CN/embedded/hwsw/hardware/atom-e6x5c/hardware,2012-03-05
[20] Hammond L, Hubbert B A, Siu M, et al. The Stanford Hydra CMP. IEEE Micro,2000,20(2):71-84
[21] Taylor M B, Kim J, Miller J, et al. The Raw Microprocessor: a ComputationalFabric for Software Circuits and General-Purpose Programs. IEEE Micro,2002,22(2):25-35
[22] Friebe L, Stolberg H J, Berekovic M, et al. HiBRID-SoC: a system-on-chiparchitecture with two multimedia DSPs and a RISC core. In: Proc of the IEEE IntSystems-on-Chip Conf, New York: IEEE,2003,85-88
[23] Givargis T, Vahid F. Platune: a tuning framework for system-on-a-chip platforms.IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems,2002,21(11):1317-1327
[24] Krasnov A, Schultz A, Wawrzynek J, et al. RAMP Blue: A Message-PassingManycore System in FPGAs. In: Proc of Int Conf on Field Programmable Logicand Applications, Amsterdam: IEEE Computer Society,2007,54-61
[25] Consortium M. MultiCube Final Publishable Summary. http://www.multicube.eu/documents/MULTICUBE_Publishable_Summary_Y3. pdf,2010
[26] Liu C, Layland J. Scheduling algorithms for multiprogramming in a hardreal-time environment. Journal of the ACM,1973,20(1):46-61
[27] Baruah S. Feasibility analysis of preemptive real-time systems uponheterogeneous multiprocessor platforms. In: Proc of the25th IEEE IntReal-Time Systems Symposium, Washington: IEEE Computer Society,2004,37-46
[28] Buttazzo G, Abeni L. Adaptive workload management through elastic scheduling.Real-Time Systems,2002,23(3):7-24
[29] Dutot P. Complexity of master-slave tasking on heterogeneous trees. EuropeanJournal on Operational Research,2005,164(3):690-695
[30] Haluk T, Salim H, Wu M Y. Performance-Effective and Low-Complexity TaskScheduling for Heterogeneous Computing. IEEE Transactions on Parallel andDistributed Systems,2002,13(3):260-274
[31] Baruah S. Task partitioning upon heterogeneous multiprocessor platform. In:Proc of the10th IEEE Real-Time and Embedded Technology and ApplicationsSymposium, Canada: IEEE Computer Society,2004,536-543
[32] Baruah S. Feasibility analysis of preemptive real-time systems uponheterogeneous multiprocessor platforms. In: Proc of the25th IEEE IntReal-Time Systems Symposium, New York: IEEE Computer Society,2004,37-46
[33] Baruah S, Fisher N. The Partitioned Multiprocessor Scheduling ofDeadline-Constrained Sporadic Task Systems. IEEE Transactions on Computers,2006,55(7):918-923
[34] Shelby F, Baruah S. Task assignment on uniform heterogeneous multiprocessors.In: Proc of the17th Euromicro Conf on Real-Time Systems, Spain: IEEEComputer Society,2005:219-226
[35] Gopalakrishnan S, Caccamo M. Task partitioning with replication uponheterogeneous multiprocessor systems. In: Proc of the12th IEEE Real-Time andEmbedded Technology and Applications Symposium, California: IEEEComputer Society.2006,199-207
[36] Hsu H R, Chen J J, Kuo T W. Multiprocessor Synthesis for Periodic HardReal-Time Tasks under a Given Energy Constraint. In: Proc of the Conf onDesign, Automation and Test in Europe, Belgium: EDAA,2006,1061-1066
[37] Ahmad I, Kwok Y K. On exploiting task duplication in parallel programscheduling. IEEE Transaction on Parallel and Distributed Systems,1998,9(9):872-892
[38] Bansal S, Kumar P, Singh K. Dealing with heterogeneity through limitedduplication for scheduling precedence constrained task graphs. Parallel andDistributed Computing,2005,65(6):479-491
[39] Shin K, Cha M, Jang M, et al. Task scheduling algorithm using minimizedduplications in homogeneous systems. Parallel and Distributed Computing,2008,68(8):1146-1156
[40] Tarek F, Abdelzaher, Kang G S. Period-Based partitioning and assignment forlarge Real-Time Applications. IEEE Transactions on Computers,2000,49(1):81-87
[41]宾雪莲,杨玉梅,金士尧.一种基于分组与适当选取策略的实时多处理器系统的动态调度算法.计算机学报,2006,29(1):81-91
[42] Agarwal A, Kumar P. Economical Duplication Based Task Scheduling forHeterogeneous and Homogeneous Computing Systems. In: Proc of the IEEE IntConf Advance Computing, New York: IEEE,2009,87-93
[43] Nicolau G. Weakly hard real-time systems. IEEE transactions on Computers,2001,50(4):308-321
[44]王堃,乔颖,王宏安等.实时异构系统的动态调度算法.计算机研究与发展,2002,39(6):725-732
[45]乔颖,王宏安,戴国忠.一种新的实时多处理器系统的动态调度算法.软件学报,2002,13(1):51-58
[46]金宏,王宏安,王强等.一种任务优先级的综合设计方法.软件学报,2003,14(3):376-382
[47]乔颖,邹冰,方亭等.一种实时异构系统的集成动态调度算法研究.软件学报,2002,13(12):2251-2258
[48]邱卫东,陈燕,李洁萍等.一种实时异构嵌入式系统的任务调度算法.软件学报,2004,15(4):504-511
[49]沈卓炜,汪芸.基于EDF调度策略的端到端实时系统可调度性分析算法.计算机研究与发展,2006,43(5):813-820
[50]梁洪涛,袁由光,方明.一种基于任务全局迁移的静态调度算法.计算机研究与发展,2006,43(5):797-804
[51]肖鹏,胡志刚.截止时间约束下独立网格任务的协同调度模型.电子学报,2011,39(8):1852-1857
[52]刘海迪,杨裔,马生峰等.基于分层遗传算法的网格任务调度策略.计算机研究与发展,2008,45(z1):35-39
[53]钟诚,李显宁.异构机群系统上带返回信息的可分负载多轮调度算法.计算机研究与发展,2008,45(z1):99-104
[54]江维,常政威,桑楠等.安全和能量关键的分布式协作任务调度.电子学报,2011,39(4):757-762
[55] Holland J H. Adaptation in Natural and Artificial Systems. Ann Arbor:University of Michigan press,1975
[56] Dorigo M, Maniezzo V, Colorni A. Ant System: Optimization by a Colony ofCooperating Agents. IEEE Transactions on Systems, Man and Cybernetics Part B,1996,26(1):29-41
[57] Kennedy J, Eberhart R C. Particle swarm optimization. In: Proc of the IEEE IntConf on Neural Networks, Washington D C: IEEE Computer Society,1995,1942-1948
[58] Wu JG, Srikanthan T, Zou GW. New Model and Algorithm forHardware/Software Partitioning. Computer Science and Technology,2008,23(4):644-651
[59] Rakhmatov D N, Vrudhula S B K. Hardware-software bi-partitioning fordynamically reconfigurable systems. In: Proc of the12th Int symposium onHardware/software code sign, New York, NY, USA: ACM,2002,145-150
[60]李仁发,周祖德,陈幼平等.可重构计算的硬件结构.计算机研究与发展,2003,140(13):500-507
[61] Saha P, El-Ghazawi T. Automatic Software Hardware Co-Design forReconfigurable Computing Systems. In: Proc of the Int Conf on FieldProgrammable Logic and Applications, Amsterdam: IEEE,2007,507-508
[62]周学功,梁棵,黄勋章等.可重构系统中的实时任务在线调度与放置算法.计算机学报,2007,30(11):1901-1909
[63] Danne K, Platzner M. A Heuristic Approach to Schedule Periodic Real-TimeTasks on Reconfigurable Hardware. In: Proc of the Int Conf on FieldProgrammable Logic and Applications,2005,568-573
[64] Marconi T, Lu Y, Bertels K, et al. Online Hardware Task Scheduling andPlacement Algorithm on Partially Reconfigurable Devices, In: Proc of the4th Intworkshop on Reconfigurable Computing: Architectures, Tools and Applications,2008,306-311
[65] Jerraya A A. HW/SW Implementation from Abstract Architecture Models. In:Proc of the Design, Automation and Test in Europe, Belgium: EDAA,2007,1470-1471
[66] Wolf W. A decade of hardware/software codesign. IEEE Computer,2003,36(4):38-43
[67] Abdelhalim M B, Habib S E D. Fast FPGA-Based Area and Latency Estimationfor A Novel Hardware/Software Partitioning Scheme. In: Proc of the CanadianConf on Electrical and Computer Engineering, Niagara Falls: IEEE,2008,775-780
[68] Pellizzoni R, Caccamo M. Adaptive Allocation of Software and HardwareReal-Time Tasks for FPGA-based Embedded Systems.In: Proc of the12th IEEEReal-Time and Embedded Technology and Applications Symposium, Washington,DC, USA: IEEE Computer Society,2006,208-220
[69] Guo Z, Buyukkurt B, Najjar W, et al. Optimized generation of data-path from Ccodes for FPGAs. In: Proc of the Conf on Design, Automation and Test inEurope, Belgium: EDAA,2005,112-117
[70] Péter A, Zoltán á M, András O. Algorithmic aspects of hardware/softwarepartitioning. ACM Transactions on Design Automation of Electronic Systems,2005,10(1):136-156
[71] Wu J G, Thambipillai S. Efficient Algorithms for Hardware/SoftwarePartitioning to Minimize Hardware Area. In: Proc of the IEEE Asia Pacific Confon Circuits and Systems, Singapore: IEEE Computer Society,2006,1875-1878
[72] Wu J G, Ting L, Thambipillai S. Efficient Approximate Algorithm for HardwareSoftware Partitioning. In: Proc of the eighth IEEE/ACIS Int Conf on Computerand Information Science, Shanghai: IEEE Computer Society,2009,261-269
[73] Wu J G, Thambipillai S. Algorithmic Aspects of Hardware/Software Partitioning:1D Search Algorithms. IEEE Transactions on Computer,2010,59(4):532-544
[74] Arato P, Mann Z A, Orban A. Algorithmic Aspects of Hardware/SoftwarePartitioning. ACM Transactions on Design Automation of Electronic Systems,2005,10(1):136-156
[75] Lo C. C, Luo J. G, Shieh M. D..Hardware/Software Codesign of ResourceConstrained Real-Time Systems.In: Proc of the fifth Int Conf on InformationAssurance and Security,2009:177-180
[76] Amin F F, Mehdi K, Sied M F. HW/SW Partitioning Using Discrete ParticleSwarm. In: Proc of the17th ACM Great Lakes symposium on VLSI, tresa-LagoMaggiore (Italy),2007,359-364
[77] Abdelhalim M B, Salama A E, Habib S. Constrained and UnconstrainedHardware-Software Partitioning Using Particle Swarm Optimization Technique.IFIP Advances in Information and Communication Technology, Xi'an: IEEEComputer Society,2007,231:207-220
[78] Chehida K B, Auguin M. HW/SW partition approach for reconfigurable systemdesign. In: Proc of the2002Int Conf on Compilers, architecture, and synthesisfor embedded systems, Paris, France: IEEE,2002,247-251
[79] Banerjee S, Dutt N. Efficient Search Space Exploration for HW-SW Partitioning.In: Proc of the2nd IEEE/ACM/IFIP Int Conf on Hardware/so ftware codesignand system synthesis,2004,122-127
[80]吴强,边计年,薛宏熙.基于抽象体系结构模板的多路软硬件划分算法.计算机辅助设计与图形学学报,2004,16(11):1562-1567
[81] Wiangtong T, Cheung P, Luk W. Comparing three heuristic search methods forfunctional partitioning in hardware-software codesign. Journal of DesignAutomation for Embedded Systems,2002,6(4):425-449
[82]罗胜钦,马萧萧,陆忆.基于改进的NSGA遗传算法的SOC软硬件划分方法.电子学报,2009,37(11):2595-2599
[83] Yiguo Zhang, Wenjian Luo, Zeming Zhang, et al. A hardware/softwarepartitioning algorithm based on artificial immune principles. Applied SoftComputing,2008,8(1):383-391
[84]盛蓝平,林涛.采用启发式分支定界的软硬件划分.计算机辅助设计与图形学学报,2005,17(3):414-417
[85]于苏东,刘雷波,尹首一等.嵌入式粗颗粒度可重构处理器的软硬件协同设计流程.电子学报,2009,37(5):1136-1140
[86]彭艺频,凌明,杨军等.基于关键路径和面积预测的软硬件划分方法.电子学报,2005,33(2):249-253
[87]沈英哲,周学海.一种用于可重构计算系统的软硬件划分算法.中国科学技术学报,2009,39(2):182-189
[88] Proshanta S, Tarek E G. A Methodology for Automating Co-Scheduling forReconfigurable Computing Systems. In: Proc of the5th ACM and IEEE Int Confon Formal Methods and Models for Co-Design, New York, NY, USA: ACM,2007,159-168
[89] Ji Y, Li L Y, Shi M, et al. Hardware/software partitioning algorithm using hybridgenetic and tabu search. Computer Engineering and Applications,2009,45(20):81-83
[90]熊志辉,李思昆,陈吉华.遗传算法与蚂蚁算法动态融合的软硬件划分.软件学报,2005,16(4):503-512
[91]刘安,冯金富,梁晓龙等.基于遗传粒子群优化的嵌入式系统软硬件划分算法.计算机辅助设计与图形学学报,2010,22(6):928-933
[92] Walder H, Platzner M. Reconfigurable Hardware Operating Systems:FromDesign Concepts to Realizations. In: Proc of the Intel Conf Eng. ofReconfigurable Systems and Algorithms, Las Vegas, USA: IEEE,2003,284-287
[93]李肯立,李庆华,戴光明等.背包问题的一种自适应算法.计算机研究与发展.2004,41(7):1292-1297
[94] Mylène B. Optimal acceptance rates for Metropolis algorithms Moving beyond0.234. Stochastic Processes and their Applications,2008,118(12):2198-2222
[95] Taghi M, Baghmisheh V, Navarbaf A. A Modified Very Fast Simulated AnnealingAlgorithm.In: Proc of the2008Internatioal Symposium on Telecommunications,Tehran, Iran: IEEE,2008,61-66
[96] Eles P, Peng Z, Kuchinski K, et al. System Level Hardware/Software Partitioningbased on simulated annealing and Tabu Search. Design Automation forEmbedded Systems,1997,2:71-76
[97]熊志辉,李思昆,陈吉华.具有初始信息素的蚂蚁寻优软硬件划分算法.计算机研究与发展,2005,42(12):2176-2183
[98] Tahaee S A, Jahangir A H. A polynomial algorithm for partitioning problems.ACM Transactions on Embedded Computing Systems,2010,9(4),34:1-38
[99] GUTHAUS M R, RINGENBERG J S, ERNST D, et al. Mibench: A free,commercially representative embedded benchmark suite. In: Proc of theWorkload Characterization, IEEE Int Workshop,2001,3-14
[100] Vallerio K S, Jha N K. Task graph extraction for embedded system synthesis. In:Proc of the16th Int Conf on VLSI Design, Berlin, Heidelberg: Springer-Verlag,2003,480-486
[101] Arato P, Juhasz S, Mann Z, et al. Hardware-Software partitioning in embeddedsystem design. In: Proc of the IEEE Int Symposium on Intelligent SignalProcessing,2003,197-202
[102] L′opez-Vallejo M, L′opez J C. On the hardware-software partitioningproblem:System modeling and partitioning techniques. ACM Transactions onDesign Automation of Electronic Systems (TODAES).2003,8(3):269-297
[103] Dick R P, Rhodes D L, Wolf W. TGFF Task Graphs for Free. In: Proc of the6thInt Workshop Hardware/Software Codesign, Mar.1998,97-101
[104]李仁发,刘彦,徐成.多处理器片上系统任务调度研究进展评述.计算机研究与发展.2008,45(9):1620-1629
[105] Andrei A, Schmitz M, Eles P, et al. Overhead-conscious voltage selection fordynamic and leakage energy reduction of time-constrained systems. In: Proc ofDesign, Automation and Test in Europe Conf and Exposition, Belgium: EDAA,2005,518-523
[106] Bautista D, Sahuquillo J, Hassan H, et al. A Simple Power-Aware Schecluling forMulticore Systems When Running Real-Time Applieations. In: Proc of the22ndIEEE/ACM Internationa1Parallel and Distributed Processing Symposium, NewYork, NY, USA: ACM,2008,1-7
[107] Singh K, Bhadauria M, McKee S A. Real Time Power Estimation and ThreadScheduling via Performance Counters. ACM SIGARCH Computer ArchitectureNews,2009,37(2):46-55
[108] Huang X, Li K L, Li R F.A Energy Efficient Scheduling Base on DynamicVoltage and Frequency Scaling for Multi-Core Embedded Real-Time System. In:Proc of the ICA3PP’09,2009,137-145
[109] Rotem E, Mendelson A,Ginosar R,et al.Multiple Clock and Voltage Domains forChip Multi Processors. In: Proc of the ACM MICRO’09,2009,459-468
[110] Zhang Y, Hu X, Chen D Z. Task Scheduling and Voltage Selection for EnergyMinimization. In: Proc of the39th Design Automation Conf, June2002,183-188
[111] Leung L F, Tsui C Y, Ki W H. Minimizing Energy Consumption of MultipleProcessors-Core Systems with Simultaneous Task Allocation, Scheduling andVoltage Assignment. In: Proc of the Asia and South Pacific Design AutomationConf,2004,647-652
[112] Luo J, Jha N K. Power-Conscious Joint Scheduling of Periodic Task Graphs andAperiodic Tasks in Distributed Real-time Embedded Systems. In: Proc of the IntConf of Computer-Aided Design, NJ, USA: IEEE Press Piscataway,2000,357-364
[113] Gorjiara B, Chou P, Bagherzadeh N, et al. Fast and efficient voltage schedulingby evolutionary slack distribution. In: Proc of the Asia and South Pacific DesignAutomation Conf, Jan.2004,659-662
[114] Gorjiara B, Bagherzadeh N, Chou P. An efficient voltage scaling algorithm forcomplex SoCs with few number of voltage modes. In: Proc of the Int Symposiumon Low Power Electronics and Design,2004,381-386
[115] Gorjiara B, Bagherzadeh N, Chou P. Ultra-fast and efficient algorithm for energyoptimization by gradient-based stochastic voltage and task scheduling. ACMTransactions on Design Automation of Electronic Systems, Sep.2007,12(4):3911-3920
[116] Gruian F, Kuchcinski K. LEneS: Task Scheduling for Low-Energy SystemsUsing Variable Supply Voltage Processors. In: Proc of the Asia and South PacificDesign Automation Conf, Jan.2001,449-455,
[117] Liu Y, Veeravalli B, Viswanathan S. Novel critical-path based low-energyscheduling algorithms for heterogeneous multiprocessor real-time embeddedsystems. In13th Int Conf on Parallel and Distributed Systems,2007,1-8
[118] Schmitz M T, Al-Hashimi B M, Eles P. Energy-Efficient Mapping andScheduling for DVS Enabled Distributed Embedded Systems. In: Proc of theDesign, Automation and Test in Europe Conf. and Exposition, Belgium: EDAA,2002,514-521
[119] Schmitz M T, Al-Hashimi B M. Considering Power Variations of DVSProcessing Elements for Energy Minimisation in Distributed Systems. In Proc.Int’l Symp. Systems Synthesis,2001,250-255
[120] Kianzad V, Bhattacharyya S S, Qu G. CASPER: an integrated energy-drivenapproach for task graph scheduling on distributed embedded systems. In: Proc of16th IEEE Int Conf on Application-specific Systems, Architectures andProcessors,2005,191-197
[121] Luo J, Jha N. Power-efficient scheduling for heterogeneous distributed real-timeembedded systems. Computer-Aided Design of Integrated Circuits and Systems,2007,26(6):1161-1170
[122] Niu L W. Energy Efficient Scheduling for Real-Time Embedded Systems withQoS Guarantee. In: Proc of the16th IEEE Int Conf on Embedded and Real-TimeComputing Systems and Applications, Macau SAR: IEEE Computer Society2010,163-172
[123] Goh L K, Veeravalli B, Viswanathan S. Design of fast and efficient energy-awaregradient-based scheduling algorithms heterogeneous embedded multiprocessorsystems. IEEE Transactions on Parallel and Distributed Systems,2009,20(1):1-12
[124] SIA2009. Int technology roadmap for semiconductors (ITRS).http://www.itrs.net/reports. html,2011-08-23
[125] Arstechnica. Ars Technica. NVIDIA denies rumors of faulty chips, mass GPUfailures.www.arstechnica.com/hardware/news/2008/07/nvidia-denies–rumors-of-mass-gpu–failures.ars,2008-06-5
[126] Li Y, Lee B C, Brooks D, et al. CMP design space exploration subject to physicalconstraints. In: Proc of the12th IEEE Int Symposium on High PerformanceComputer Architecture,2006,15-26
[127] Mesa-Martinez F J, Ardestani E K, Renau J. Characterizing processor thermalbehavior. In: Proc of the Int Conf on Architectural Support for ProgrammingLanguages and Operating Systems, Pittsburgh, Pennsylvania, USA:ACM,2010,193-204
[128] Venkatachalam V, ranz M F. Power reduction techniques for microprocessorsystems. ACM Computing Surveys (CSUR),2005,37(3):195-237
[129] Li Y, Brooks D, Hu Z, et al. Performance, energy, and thermal considerations forSMT and CMP architectures. In: Proc of the11th Int Symposium onHigh-Performance Computer Architecture, Washington, DC: IEEE ComputerSociety, USA,2005,71-82
[130] Bansal N, Kimbrel T, Pruhs K. Speed scaling to manage energy and temperatur e.Journal of the ACM,2007,54(1):1-39
[131] Skadron K, Stan M R, Wei H, et al. Temperature-aware computer systems:opportunities and challenges. IEEE Micro,2003,23(6):52-61
[132] Chaturvedi V, Gang Q. Leakage conscious DVS scheduling for peak temperatureminimization. In: Proc of the16th Asia and South Pacific Design AutomationConf (ASP-DAC), NJ, USA: IEEE Press Piscataway,2011,135-140
[133] Liu Y, Dick R P, Shang L, et al. Accurate temperature-dependent integratedcircuit leakage power estimation is easy. In: Proc of the Design, Automation andTest in Europe, Belgium: EDAA,2007,1526-1531
[134] Schor L, Yang H, Bacivarov I, et al. Worst-case temperature analysis forreal-time systems. In: Proc of the Design, Automation and Test in Europe,Belgium: EDAA,2011,1-6
[135] Kumar A, Shang L, Peh L-S, et al. HybDTM: a coordinated hardware-softwareapproach for dynamic thermal management. In: Proc of the43rd annual DesignAutomation Conf, San Francisco, CA, USA:ACM,2006,548-553
[136] Kumar A, Shang L, Peh L-S, et al. System-level dynamic thermal managementfor high-performance microprocessors. IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems,2008,27(1):96-108
[137] Merkel A, Bellosa F, Weissel A. Event-driven thermal management in SMPsystems. In: Proc of the Second Workshop on Temperature-Aware ComputerSystems, Madison, USA:IEEE,2005
[138] Choi J, Cher C Y, Franke H, et al. Thermal-aware task scheduling at the systemsoftware level. In: Proc of the Int Symposium on Low Power Electronics andDesign, New York, NY, USA: ACM,2007,213-218
[139] Arani A S. Online thermal-aware scheduling for multiple clock domain CMPs. In:Proc of the IEEE Int SOC Conf, Hsin Chu, Taiwan: IEEE,2007,137-140
[140] Merkel A, Bellosa F. Task activity vectors: a new metric for temperature-awarescheduling.In: Proc of the3rd ACM SIGOPS EuroSys Conf, Glasgow, Scotland,UK:ACM,2008,1-12
[141] Yang J, Zhou X, Chrobak M, et al. Dynamic thermal management through taskscheduling.In: Proc of the IEEE Int Symposium on Performance Analysis ofSystems and software, Austin, TX: IEEE,2008,191-201
[142] Zhou X, Xu Y, Du Y, et al. Thermal management for3D processors via taskscheduling. In: Proc of the37th Int Conf on Parallel Processing, Portland, OR:IEEE Computer Society,2008,115-122
[143] Chen J J, Hung C M, Kuo T W. On the minimization of the instantaneoustemperature for periodic real-time tasks. In: Proc of the13th IEEE Real-Timeand Embedded Technology and Applications Symposium, Washington, USA:IEEE Computer Society,2007,236-248
[144] Aydin H, Melhem R, Mosse D, et al. Dynamic and aggressive schedulingtechniques for power-aware real-time systems. In: Proc of the22nd IEEEReal-Time Systems Symposium, Washington, DC, USA: IEEE Computer Society,2001,95-105
[145] Vazirani V V. Approximation algorithms. Springer,2001
[146] Yuan L, Qu G. ALT-DVS: dynamic voltage scaling with awareness of leakageand temperature for real-time systems. In: Proc of the2nd NASA/ESA Conf onAdaptive Hardware and Systems, Edinburgh: IEEE Computer Society,2007,660-670
[147] Jayaseelan R, Mitra T. Temperature aware scheduling for embedded processors.In: Proc of the22nd Int Conf on VLSI Design, Washington, DC, USA:IEEEComputer Society,2009,541-546
[148] Mulas F, Pittau M, Buttu M, et al. Thermal balancing policy for streamingcomputing on multiprocessor architectures. In: Proc of the Design, Automationand Test in Europe Conf and Exhibition, Belgium: EDAA,2008,734-739
[149] Coskun A K, Rosing T S, Whisnant K, et al. Temperature-aware MPSoCscheduling for reducing hot spots and gradients. In: Proc of the2008Asia andSouth Pacific Design Automation Conf, Seoul: IEEE Computer Society,2008,49-54
[150] Coskun A K, Rosing T S, Whisnant K. Temperature aware task scheduling inMPSoCs. In: Proc of the Conf on Design, Automation and Test in Europe Confand Exhibition, Belgium: EDAA,2007,1659-1664
[151] Thidapat C, Robert P D, Hu X S. Temperature-Aware Scheduling andAssignment for Hard Real-Time Applications on MPSoC. IEEE Transactions onVery Large Scale Integration Systems,2011,19(10):1884-1897
[152] Wang S, Bettati R. Delay analysis in temperature-constrained hard real-timesystems with general task arrivals. In: Proc of the27th IEEE Int Real-TimeSystems Symposium, Washington, DC, USA: IEEE Computer Society,2006,323-332
[153] Chen J J, Wang S, Thiele L. Proactive speed scheduling for real-time tasks underthermal con-straints. In: Proc of the15th IEEE Real-Time and EmbeddedTechnology and Applications Symposium, San Francisco, US: IEEE,2009,141-150
[154] Mutapcic A, Boyd S, Murali S, et al. Processor speed control with thermalconstraints. IEEE Transactions on Circuits and Systems I: Regular Papers,2009,56(9):1994-2008
[155] Rao R, Vrudhula S. Efficient online computation of core speeds to maximize thethroughput of thermally constrained multi-core processors. In: Proc of the IntConf on Computer-Aided Design, NJ, USA: IEEE Press Piscataway,2008,537-542
[156] Jung H, Rong P, Pedram M. Stochastic modeling of a thermally-managedmulti-core system. In: Proc of the45th annual Design Automation Conf, NewYork: ACM,2008,728-733
[157] Sun C, Shang L, Dick R P. Three-dimensional multiprocessor system-on-chipthermal opti-mization. In: Proc of the5th Int Conf on Hardware/SoftwareCodesign and System Synthesis, New York: ACM,2007,117-122
[158] Wang S, Bettati R. Reactive speed control in temperature-constrained real-timesystems. In: Proc of the18th Euromicro Conf on Real-Time Systems(ECRTS’06), MA, USA: Kluwer Academic Publishers Norwell,2006,161-170
[159] Rao R, Vrudhula S, Chakrabarti C, et al. An optimal analytical solution forprocessor speed control with thermal consstraints. In: Proc of the2006IntSymposium on Low Power Electronics and Design, Tegernsee, Germany:ACM,2006,292-297
[160] Yuan L, Leventhal S, Qu G. Temperature-aware leakage minimization techniquefor real-time systems. In: Proc of the IEEE/ACM Int Conf on Computer-aideddesign (ICCAD '06), New York: ACM,2006,761-764
[161] Bao M, Andrei A, Eles P, et al. Temperature-aware idle time distribution forenergy optimization with dynamic voltage scaling. In: Proc of the Design,Automation and Test in Europe Conf and Exhibition, Belgium: EDAA,2010,21-26
[162] Fisher N, Chen J J, Wang S, et al. Thermal-aware global real-time scheduling onmulticore systems. In: Proc of the15th IEEE Real-Time and EmbeddedTechnology and Applications Symposium, San Francisco, CA: IEEE ComputerSociety,2009,131-140
[163] Chantem T, Hu X S, Dick R P. Online work maximization under a peaktemperature constraint, In: Proc of the14th ACM/IEEE Int symposium on Lowpower electronics and design, New York: ACM,2009,105-110
[164] Yang C Y, Chen J J, Thiele L, et al. Energy-efficient real-time task schedulingwith temperature-dependent leakage. In: Proc of the Conf on Design,Automation and Test in Europe, Belgium: EDAA,2010,9-14
[165] Quan G, Chaturvedi V. Feasibility analysis for temperature-constraint hardreal-time periodic tasks. IEEE Transaction on Industrial Informatics,2010,6(3):329-339
[166] Xie Y, Hung W L. Temperature-aware task allocation and scheduling forembedded multiprocessor systems-on-chip (MPSoC) design. The Journal ofVLSI Signal Processing,2006,45(3):177-189
[167]汪尔康主编.生命分析化学.北京：科学出版社,2006.7:667-688
[168] Wu H L, Shibukawa M, Oguma K. An alternating trilinear decomposition methodwith application to calibration of HPLC-DAD for simultaneous determination ofoverlapped chlorinated aromatic hydrocarbons. Journal of Chemo metrics,1998,12(1):1-26
[169] Maharatna K, Dhar A S, Banerjee S. A VLSI array architecture for realization ofDFT.DHT, DCT and DST. Signal Process,2001,81(9):1813-1822
[170] Mingqian T Z, Madhukumar A S, Chin F. QRD-RLS Adaptive Equalizer and itsCORDIC-Based Implementation for CDMA Systems. Int Journal on Wireless&Optical Communications,2003,1(1):25-39
[171] Pramod K M, Javier V, Juang T B, et al.50Years of CORDIC: Algorithms,Architectures, and Applications. IEEE Transactions on Circuits and Systems,2009,56(9):1893-1907
[172] Intel Corporation. Intel PXA255Processor, Developer's Manual. March2003
[2] ITRS. The Int technology roadmap for semiconductors. www.itrs.net/Links/2009ITRS/Home2009.htm,2012-04-01
[3] Vangal S, Howard J, Ruhl G, et al. An80-tile1.28TFLOPS network-on-chip in65nm CMOS. In: Proc of the IEEE Int Solid-State Circuits Conf, San Francisco:IEEE Computer Society,2007,98-99
[4] Wentzlaff D, Griffin P, Hoffmann H, et al. On-chip interconnection architectureof the tile processor. IEEE Micro,2007,27(5):15-31
[5] TILE. TILE-Gx Processor Family. http://www.tilera.com/products/TILE-Gx.php,2012-05-14
[6] Kumar R, Tullsen D M, Jouppi N P, et al. Heterogeneous Chip Multi-processors.IEEE Computer Society,2005,38(11):32-38
[7] Li T, Paul B, Rob K, et al. Operating System Support for Overlapping-ISAHeterogeneous Multi-core Architectures. In: Proc of the16th IEEE IntSymposium on High-Performance Computer Architecture (HPCA), Bangalore:IEEE,2010,1-12
[8] Rakesh K, Dean M T, Parthasarathy R, et al. Single-ISA HeterogeneousMulti-Core Architecture for Multithreaded Workload Performance. In: Proc ofthe31st Int Symposium on Computer Architecture, Germany: IEEE ComputerSociety,2004,64-75
[9] Miquel P, Adrian C, Francisco J, et al. A Flexible Heterogeneous Multi-CoreArchitecture. In: Proc of the16th Int Conf on Parallel Architecture andCompilation Techniques, Washington, DC: IEEE Computer Society,2007,13-24
[10] Michael G. The Cell Broadband Engine: Exploiting Multiple Levels ofParallelism in a Chip Multiprocessor. Int Journal of Parallel Programming,2007,35(3):233-262
[11] Perry H W, Jamison D C, Gautham N C, et al. EXOCHI: Architecture andProgramming Environment for a Heterogeneous Multi-Core Mult ithreadedSystem. In: Proc of the ACM SIGPLAN Conf on Programming language designand implementation, San Diego: ACM,2007,156-166
[12] Abmed J, Hannu T, Wayne W. Guest Editors' Introduction: MultiprocessorSystems-on-Chip. IEEE Computer,2005,38(7):36-40
[13] Garey M R, Johnson D S. Computers and Intractability: A Guide to the Theory ofNP-Completeness. New York: W H Freeman Company,1979
[14] Viswanath R, Wakharkar V, Watwe A, et al. Thermal performance challengesfrom silicon to systems. Intel Technology Journal,2000,4(3):1-16
[15](美)克里兹著,孟宪元译.高级FPGA设计:结构、实现和优化.北京:机械工业出版社,2009
[16] Crafts J, Bogdan D, Conti D, et al. Testing the IBM Power74GHz eight coremicroprocessor. In: Proc of the IEEE Int Test Conf, Austin: IEEE,2010,1-10
[17] Pham D, Asano S, Bolliger M, et al. The design and implementation of afirst-generation CELL processor. In: Proc of the IEEE Int Solid-State CircuitsConf, San Francisco: IEEE Computer Society,2005,184-l86
[18] XILINX. Zynq-7000产品简介. http://www. xilinx. com/publications/prod_mktg/zynq7000/Product-Brief. pdf,2012-01-03
[19] INTEL.支持嵌入式计算的基于英特尔凌动处理器E6x5C系列的平台. http://www. intel.com/p/zh_CN/embedded/hwsw/hardware/atom-e6x5c/hardware,2012-03-05
[20] Hammond L, Hubbert B A, Siu M, et al. The Stanford Hydra CMP. IEEE Micro,2000,20(2):71-84
[21] Taylor M B, Kim J, Miller J, et al. The Raw Microprocessor: a ComputationalFabric for Software Circuits and General-Purpose Programs. IEEE Micro,2002,22(2):25-35
[22] Friebe L, Stolberg H J, Berekovic M, et al. HiBRID-SoC: a system-on-chiparchitecture with two multimedia DSPs and a RISC core. In: Proc of the IEEE IntSystems-on-Chip Conf, New York: IEEE,2003,85-88
[23] Givargis T, Vahid F. Platune: a tuning framework for system-on-a-chip platforms.IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems,2002,21(11):1317-1327
[24] Krasnov A, Schultz A, Wawrzynek J, et al. RAMP Blue: A Message-PassingManycore System in FPGAs. In: Proc of Int Conf on Field Programmable Logicand Applications, Amsterdam: IEEE Computer Society,2007,54-61
[25] Consortium M. MultiCube Final Publishable Summary. http://www.multicube.eu/documents/MULTICUBE_Publishable_Summary_Y3. pdf,2010
[26] Liu C, Layland J. Scheduling algorithms for multiprogramming in a hardreal-time environment. Journal of the ACM,1973,20(1):46-61
[27] Baruah S. Feasibility analysis of preemptive real-time systems uponheterogeneous multiprocessor platforms. In: Proc of the25th IEEE IntReal-Time Systems Symposium, Washington: IEEE Computer Society,2004,37-46
[28] Buttazzo G, Abeni L. Adaptive workload management through elastic scheduling.Real-Time Systems,2002,23(3):7-24
[29] Dutot P. Complexity of master-slave tasking on heterogeneous trees. EuropeanJournal on Operational Research,2005,164(3):690-695
[30] Haluk T, Salim H, Wu M Y. Performance-Effective and Low-Complexity TaskScheduling for Heterogeneous Computing. IEEE Transactions on Parallel andDistributed Systems,2002,13(3):260-274
[31] Baruah S. Task partitioning upon heterogeneous multiprocessor platform. In:Proc of the10th IEEE Real-Time and Embedded Technology and ApplicationsSymposium, Canada: IEEE Computer Society,2004,536-543
[32] Baruah S. Feasibility analysis of preemptive real-time systems uponheterogeneous multiprocessor platforms. In: Proc of the25th IEEE IntReal-Time Systems Symposium, New York: IEEE Computer Society,2004,37-46
[33] Baruah S, Fisher N. The Partitioned Multiprocessor Scheduling ofDeadline-Constrained Sporadic Task Systems. IEEE Transactions on Computers,2006,55(7):918-923
[34] Shelby F, Baruah S. Task assignment on uniform heterogeneous multiprocessors.In: Proc of the17th Euromicro Conf on Real-Time Systems, Spain: IEEEComputer Society,2005:219-226
[35] Gopalakrishnan S, Caccamo M. Task partitioning with replication uponheterogeneous multiprocessor systems. In: Proc of the12th IEEE Real-Time andEmbedded Technology and Applications Symposium, California: IEEEComputer Society.2006,199-207
[36] Hsu H R, Chen J J, Kuo T W. Multiprocessor Synthesis for Periodic HardReal-Time Tasks under a Given Energy Constraint. In: Proc of the Conf onDesign, Automation and Test in Europe, Belgium: EDAA,2006,1061-1066
[37] Ahmad I, Kwok Y K. On exploiting task duplication in parallel programscheduling. IEEE Transaction on Parallel and Distributed Systems,1998,9(9):872-892
[38] Bansal S, Kumar P, Singh K. Dealing with heterogeneity through limitedduplication for scheduling precedence constrained task graphs. Parallel andDistributed Computing,2005,65(6):479-491
[39] Shin K, Cha M, Jang M, et al. Task scheduling algorithm using minimizedduplications in homogeneous systems. Parallel and Distributed Computing,2008,68(8):1146-1156
[40] Tarek F, Abdelzaher, Kang G S. Period-Based partitioning and assignment forlarge Real-Time Applications. IEEE Transactions on Computers,2000,49(1):81-87
[41]宾雪莲,杨玉梅,金士尧.一种基于分组与适当选取策略的实时多处理器系统的动态调度算法.计算机学报,2006,29(1):81-91
[42] Agarwal A, Kumar P. Economical Duplication Based Task Scheduling forHeterogeneous and Homogeneous Computing Systems. In: Proc of the IEEE IntConf Advance Computing, New York: IEEE,2009,87-93
[43] Nicolau G. Weakly hard real-time systems. IEEE transactions on Computers,2001,50(4):308-321
[44]王堃,乔颖,王宏安等.实时异构系统的动态调度算法.计算机研究与发展,2002,39(6):725-732
[45]乔颖,王宏安,戴国忠.一种新的实时多处理器系统的动态调度算法.软件学报,2002,13(1):51-58
[46]金宏,王宏安,王强等.一种任务优先级的综合设计方法.软件学报,2003,14(3):376-382
[47]乔颖,邹冰,方亭等.一种实时异构系统的集成动态调度算法研究.软件学报,2002,13(12):2251-2258
[48]邱卫东,陈燕,李洁萍等.一种实时异构嵌入式系统的任务调度算法.软件学报,2004,15(4):504-511
[49]沈卓炜,汪芸.基于EDF调度策略的端到端实时系统可调度性分析算法.计算机研究与发展,2006,43(5):813-820
[50]梁洪涛,袁由光,方明.一种基于任务全局迁移的静态调度算法.计算机研究与发展,2006,43(5):797-804
[51]肖鹏,胡志刚.截止时间约束下独立网格任务的协同调度模型.电子学报,2011,39(8):1852-1857
[52]刘海迪,杨裔,马生峰等.基于分层遗传算法的网格任务调度策略.计算机研究与发展,2008,45(z1):35-39
[53]钟诚,李显宁.异构机群系统上带返回信息的可分负载多轮调度算法.计算机研究与发展,2008,45(z1):99-104
[54]江维,常政威,桑楠等.安全和能量关键的分布式协作任务调度.电子学报,2011,39(4):757-762
[55] Holland J H. Adaptation in Natural and Artificial Systems. Ann Arbor:University of Michigan press,1975
[56] Dorigo M, Maniezzo V, Colorni A. Ant System: Optimization by a Colony ofCooperating Agents. IEEE Transactions on Systems, Man and Cybernetics Part B,1996,26(1):29-41
[57] Kennedy J, Eberhart R C. Particle swarm optimization. In: Proc of the IEEE IntConf on Neural Networks, Washington D C: IEEE Computer Society,1995,1942-1948
[58] Wu JG, Srikanthan T, Zou GW. New Model and Algorithm forHardware/Software Partitioning. Computer Science and Technology,2008,23(4):644-651
[59] Rakhmatov D N, Vrudhula S B K. Hardware-software bi-partitioning fordynamically reconfigurable systems. In: Proc of the12th Int symposium onHardware/software code sign, New York, NY, USA: ACM,2002,145-150
[60]李仁发,周祖德,陈幼平等.可重构计算的硬件结构.计算机研究与发展,2003,140(13):500-507
[61] Saha P, El-Ghazawi T. Automatic Software Hardware Co-Design forReconfigurable Computing Systems. In: Proc of the Int Conf on FieldProgrammable Logic and Applications, Amsterdam: IEEE,2007,507-508
[62]周学功,梁棵,黄勋章等.可重构系统中的实时任务在线调度与放置算法.计算机学报,2007,30(11):1901-1909
[63] Danne K, Platzner M. A Heuristic Approach to Schedule Periodic Real-TimeTasks on Reconfigurable Hardware. In: Proc of the Int Conf on FieldProgrammable Logic and Applications,2005,568-573
[64] Marconi T, Lu Y, Bertels K, et al. Online Hardware Task Scheduling andPlacement Algorithm on Partially Reconfigurable Devices, In: Proc of the4th Intworkshop on Reconfigurable Computing: Architectures, Tools and Applications,2008,306-311
[65] Jerraya A A. HW/SW Implementation from Abstract Architecture Models. In:Proc of the Design, Automation and Test in Europe, Belgium: EDAA,2007,1470-1471
[66] Wolf W. A decade of hardware/software codesign. IEEE Computer,2003,36(4):38-43
[67] Abdelhalim M B, Habib S E D. Fast FPGA-Based Area and Latency Estimationfor A Novel Hardware/Software Partitioning Scheme. In: Proc of the CanadianConf on Electrical and Computer Engineering, Niagara Falls: IEEE,2008,775-780
[68] Pellizzoni R, Caccamo M. Adaptive Allocation of Software and HardwareReal-Time Tasks for FPGA-based Embedded Systems.In: Proc of the12th IEEEReal-Time and Embedded Technology and Applications Symposium, Washington,DC, USA: IEEE Computer Society,2006,208-220
[69] Guo Z, Buyukkurt B, Najjar W, et al. Optimized generation of data-path from Ccodes for FPGAs. In: Proc of the Conf on Design, Automation and Test inEurope, Belgium: EDAA,2005,112-117
[70] Péter A, Zoltán á M, András O. Algorithmic aspects of hardware/softwarepartitioning. ACM Transactions on Design Automation of Electronic Systems,2005,10(1):136-156
[71] Wu J G, Thambipillai S. Efficient Algorithms for Hardware/SoftwarePartitioning to Minimize Hardware Area. In: Proc of the IEEE Asia Pacific Confon Circuits and Systems, Singapore: IEEE Computer Society,2006,1875-1878
[72] Wu J G, Ting L, Thambipillai S. Efficient Approximate Algorithm for HardwareSoftware Partitioning. In: Proc of the eighth IEEE/ACIS Int Conf on Computerand Information Science, Shanghai: IEEE Computer Society,2009,261-269
[73] Wu J G, Thambipillai S. Algorithmic Aspects of Hardware/Software Partitioning:1D Search Algorithms. IEEE Transactions on Computer,2010,59(4):532-544
[74] Arato P, Mann Z A, Orban A. Algorithmic Aspects of Hardware/SoftwarePartitioning. ACM Transactions on Design Automation of Electronic Systems,2005,10(1):136-156
[75] Lo C. C, Luo J. G, Shieh M. D..Hardware/Software Codesign of ResourceConstrained Real-Time Systems.In: Proc of the fifth Int Conf on InformationAssurance and Security,2009:177-180
[76] Amin F F, Mehdi K, Sied M F. HW/SW Partitioning Using Discrete ParticleSwarm. In: Proc of the17th ACM Great Lakes symposium on VLSI, tresa-LagoMaggiore (Italy),2007,359-364
[77] Abdelhalim M B, Salama A E, Habib S. Constrained and UnconstrainedHardware-Software Partitioning Using Particle Swarm Optimization Technique.IFIP Advances in Information and Communication Technology, Xi'an: IEEEComputer Society,2007,231:207-220
[78] Chehida K B, Auguin M. HW/SW partition approach for reconfigurable systemdesign. In: Proc of the2002Int Conf on Compilers, architecture, and synthesisfor embedded systems, Paris, France: IEEE,2002,247-251
[79] Banerjee S, Dutt N. Efficient Search Space Exploration for HW-SW Partitioning.In: Proc of the2nd IEEE/ACM/IFIP Int Conf on Hardware/so ftware codesignand system synthesis,2004,122-127
[80]吴强,边计年,薛宏熙.基于抽象体系结构模板的多路软硬件划分算法.计算机辅助设计与图形学学报,2004,16(11):1562-1567
[81] Wiangtong T, Cheung P, Luk W. Comparing three heuristic search methods forfunctional partitioning in hardware-software codesign. Journal of DesignAutomation for Embedded Systems,2002,6(4):425-449
[82]罗胜钦,马萧萧,陆忆.基于改进的NSGA遗传算法的SOC软硬件划分方法.电子学报,2009,37(11):2595-2599
[83] Yiguo Zhang, Wenjian Luo, Zeming Zhang, et al. A hardware/softwarepartitioning algorithm based on artificial immune principles. Applied SoftComputing,2008,8(1):383-391
[84]盛蓝平,林涛.采用启发式分支定界的软硬件划分.计算机辅助设计与图形学学报,2005,17(3):414-417
[85]于苏东,刘雷波,尹首一等.嵌入式粗颗粒度可重构处理器的软硬件协同设计流程.电子学报,2009,37(5):1136-1140
[86]彭艺频,凌明,杨军等.基于关键路径和面积预测的软硬件划分方法.电子学报,2005,33(2):249-253
[87]沈英哲,周学海.一种用于可重构计算系统的软硬件划分算法.中国科学技术学报,2009,39(2):182-189
[88] Proshanta S, Tarek E G. A Methodology for Automating Co-Scheduling forReconfigurable Computing Systems. In: Proc of the5th ACM and IEEE Int Confon Formal Methods and Models for Co-Design, New York, NY, USA: ACM,2007,159-168
[89] Ji Y, Li L Y, Shi M, et al. Hardware/software partitioning algorithm using hybridgenetic and tabu search. Computer Engineering and Applications,2009,45(20):81-83
[90]熊志辉,李思昆,陈吉华.遗传算法与蚂蚁算法动态融合的软硬件划分.软件学报,2005,16(4):503-512
[91]刘安,冯金富,梁晓龙等.基于遗传粒子群优化的嵌入式系统软硬件划分算法.计算机辅助设计与图形学学报,2010,22(6):928-933
[92] Walder H, Platzner M. Reconfigurable Hardware Operating Systems:FromDesign Concepts to Realizations. In: Proc of the Intel Conf Eng. ofReconfigurable Systems and Algorithms, Las Vegas, USA: IEEE,2003,284-287
[93]李肯立,李庆华,戴光明等.背包问题的一种自适应算法.计算机研究与发展.2004,41(7):1292-1297
[94] Mylène B. Optimal acceptance rates for Metropolis algorithms Moving beyond0.234. Stochastic Processes and their Applications,2008,118(12):2198-2222
[95] Taghi M, Baghmisheh V, Navarbaf A. A Modified Very Fast Simulated AnnealingAlgorithm.In: Proc of the2008Internatioal Symposium on Telecommunications,Tehran, Iran: IEEE,2008,61-66
[96] Eles P, Peng Z, Kuchinski K, et al. System Level Hardware/Software Partitioningbased on simulated annealing and Tabu Search. Design Automation forEmbedded Systems,1997,2:71-76
[97]熊志辉,李思昆,陈吉华.具有初始信息素的蚂蚁寻优软硬件划分算法.计算机研究与发展,2005,42(12):2176-2183
[98] Tahaee S A, Jahangir A H. A polynomial algorithm for partitioning problems.ACM Transactions on Embedded Computing Systems,2010,9(4),34:1-38
[99] GUTHAUS M R, RINGENBERG J S, ERNST D, et al. Mibench: A free,commercially representative embedded benchmark suite. In: Proc of theWorkload Characterization, IEEE Int Workshop,2001,3-14
[100] Vallerio K S, Jha N K. Task graph extraction for embedded system synthesis. In:Proc of the16th Int Conf on VLSI Design, Berlin, Heidelberg: Springer-Verlag,2003,480-486
[101] Arato P, Juhasz S, Mann Z, et al. Hardware-Software partitioning in embeddedsystem design. In: Proc of the IEEE Int Symposium on Intelligent SignalProcessing,2003,197-202
[102] L′opez-Vallejo M, L′opez J C. On the hardware-software partitioningproblem:System modeling and partitioning techniques. ACM Transactions onDesign Automation of Electronic Systems (TODAES).2003,8(3):269-297
[103] Dick R P, Rhodes D L, Wolf W. TGFF Task Graphs for Free. In: Proc of the6thInt Workshop Hardware/Software Codesign, Mar.1998,97-101
[104]李仁发,刘彦,徐成.多处理器片上系统任务调度研究进展评述.计算机研究与发展.2008,45(9):1620-1629
[105] Andrei A, Schmitz M, Eles P, et al. Overhead-conscious voltage selection fordynamic and leakage energy reduction of time-constrained systems. In: Proc ofDesign, Automation and Test in Europe Conf and Exposition, Belgium: EDAA,2005,518-523
[106] Bautista D, Sahuquillo J, Hassan H, et al. A Simple Power-Aware Schecluling forMulticore Systems When Running Real-Time Applieations. In: Proc of the22ndIEEE/ACM Internationa1Parallel and Distributed Processing Symposium, NewYork, NY, USA: ACM,2008,1-7
[107] Singh K, Bhadauria M, McKee S A. Real Time Power Estimation and ThreadScheduling via Performance Counters. ACM SIGARCH Computer ArchitectureNews,2009,37(2):46-55
[108] Huang X, Li K L, Li R F.A Energy Efficient Scheduling Base on DynamicVoltage and Frequency Scaling for Multi-Core Embedded Real-Time System. In:Proc of the ICA3PP’09,2009,137-145
[109] Rotem E, Mendelson A,Ginosar R,et al.Multiple Clock and Voltage Domains forChip Multi Processors. In: Proc of the ACM MICRO’09,2009,459-468
[110] Zhang Y, Hu X, Chen D Z. Task Scheduling and Voltage Selection for EnergyMinimization. In: Proc of the39th Design Automation Conf, June2002,183-188
[111] Leung L F, Tsui C Y, Ki W H. Minimizing Energy Consumption of MultipleProcessors-Core Systems with Simultaneous Task Allocation, Scheduling andVoltage Assignment. In: Proc of the Asia and South Pacific Design AutomationConf,2004,647-652
[112] Luo J, Jha N K. Power-Conscious Joint Scheduling of Periodic Task Graphs andAperiodic Tasks in Distributed Real-time Embedded Systems. In: Proc of the IntConf of Computer-Aided Design, NJ, USA: IEEE Press Piscataway,2000,357-364
[113] Gorjiara B, Chou P, Bagherzadeh N, et al. Fast and efficient voltage schedulingby evolutionary slack distribution. In: Proc of the Asia and South Pacific DesignAutomation Conf, Jan.2004,659-662
[114] Gorjiara B, Bagherzadeh N, Chou P. An efficient voltage scaling algorithm forcomplex SoCs with few number of voltage modes. In: Proc of the Int Symposiumon Low Power Electronics and Design,2004,381-386
[115] Gorjiara B, Bagherzadeh N, Chou P. Ultra-fast and efficient algorithm for energyoptimization by gradient-based stochastic voltage and task scheduling. ACMTransactions on Design Automation of Electronic Systems, Sep.2007,12(4):3911-3920
[116] Gruian F, Kuchcinski K. LEneS: Task Scheduling for Low-Energy SystemsUsing Variable Supply Voltage Processors. In: Proc of the Asia and South PacificDesign Automation Conf, Jan.2001,449-455,
[117] Liu Y, Veeravalli B, Viswanathan S. Novel critical-path based low-energyscheduling algorithms for heterogeneous multiprocessor real-time embeddedsystems. In13th Int Conf on Parallel and Distributed Systems,2007,1-8
[118] Schmitz M T, Al-Hashimi B M, Eles P. Energy-Efficient Mapping andScheduling for DVS Enabled Distributed Embedded Systems. In: Proc of theDesign, Automation and Test in Europe Conf. and Exposition, Belgium: EDAA,2002,514-521
[119] Schmitz M T, Al-Hashimi B M. Considering Power Variations of DVSProcessing Elements for Energy Minimisation in Distributed Systems. In Proc.Int’l Symp. Systems Synthesis,2001,250-255
[120] Kianzad V, Bhattacharyya S S, Qu G. CASPER: an integrated energy-drivenapproach for task graph scheduling on distributed embedded systems. In: Proc of16th IEEE Int Conf on Application-specific Systems, Architectures andProcessors,2005,191-197
[121] Luo J, Jha N. Power-efficient scheduling for heterogeneous distributed real-timeembedded systems. Computer-Aided Design of Integrated Circuits and Systems,2007,26(6):1161-1170
[122] Niu L W. Energy Efficient Scheduling for Real-Time Embedded Systems withQoS Guarantee. In: Proc of the16th IEEE Int Conf on Embedded and Real-TimeComputing Systems and Applications, Macau SAR: IEEE Computer Society2010,163-172
[123] Goh L K, Veeravalli B, Viswanathan S. Design of fast and efficient energy-awaregradient-based scheduling algorithms heterogeneous embedded multiprocessorsystems. IEEE Transactions on Parallel and Distributed Systems,2009,20(1):1-12
[124] SIA2009. Int technology roadmap for semiconductors (ITRS).http://www.itrs.net/reports. html,2011-08-23
[125] Arstechnica. Ars Technica. NVIDIA denies rumors of faulty chips, mass GPUfailures.www.arstechnica.com/hardware/news/2008/07/nvidia-denies–rumors-of-mass-gpu–failures.ars,2008-06-5
[126] Li Y, Lee B C, Brooks D, et al. CMP design space exploration subject to physicalconstraints. In: Proc of the12th IEEE Int Symposium on High PerformanceComputer Architecture,2006,15-26
[127] Mesa-Martinez F J, Ardestani E K, Renau J. Characterizing processor thermalbehavior. In: Proc of the Int Conf on Architectural Support for ProgrammingLanguages and Operating Systems, Pittsburgh, Pennsylvania, USA:ACM,2010,193-204
[128] Venkatachalam V, ranz M F. Power reduction techniques for microprocessorsystems. ACM Computing Surveys (CSUR),2005,37(3):195-237
[129] Li Y, Brooks D, Hu Z, et al. Performance, energy, and thermal considerations forSMT and CMP architectures. In: Proc of the11th Int Symposium onHigh-Performance Computer Architecture, Washington, DC: IEEE ComputerSociety, USA,2005,71-82
[130] Bansal N, Kimbrel T, Pruhs K. Speed scaling to manage energy and temperatur e.Journal of the ACM,2007,54(1):1-39
[131] Skadron K, Stan M R, Wei H, et al. Temperature-aware computer systems:opportunities and challenges. IEEE Micro,2003,23(6):52-61
[132] Chaturvedi V, Gang Q. Leakage conscious DVS scheduling for peak temperatureminimization. In: Proc of the16th Asia and South Pacific Design AutomationConf (ASP-DAC), NJ, USA: IEEE Press Piscataway,2011,135-140
[133] Liu Y, Dick R P, Shang L, et al. Accurate temperature-dependent integratedcircuit leakage power estimation is easy. In: Proc of the Design, Automation andTest in Europe, Belgium: EDAA,2007,1526-1531
[134] Schor L, Yang H, Bacivarov I, et al. Worst-case temperature analysis forreal-time systems. In: Proc of the Design, Automation and Test in Europe,Belgium: EDAA,2011,1-6
[135] Kumar A, Shang L, Peh L-S, et al. HybDTM: a coordinated hardware-softwareapproach for dynamic thermal management. In: Proc of the43rd annual DesignAutomation Conf, San Francisco, CA, USA:ACM,2006,548-553
[136] Kumar A, Shang L, Peh L-S, et al. System-level dynamic thermal managementfor high-performance microprocessors. IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems,2008,27(1):96-108
[137] Merkel A, Bellosa F, Weissel A. Event-driven thermal management in SMPsystems. In: Proc of the Second Workshop on Temperature-Aware ComputerSystems, Madison, USA:IEEE,2005
[138] Choi J, Cher C Y, Franke H, et al. Thermal-aware task scheduling at the systemsoftware level. In: Proc of the Int Symposium on Low Power Electronics andDesign, New York, NY, USA: ACM,2007,213-218
[139] Arani A S. Online thermal-aware scheduling for multiple clock domain CMPs. In:Proc of the IEEE Int SOC Conf, Hsin Chu, Taiwan: IEEE,2007,137-140
[140] Merkel A, Bellosa F. Task activity vectors: a new metric for temperature-awarescheduling.In: Proc of the3rd ACM SIGOPS EuroSys Conf, Glasgow, Scotland,UK:ACM,2008,1-12
[141] Yang J, Zhou X, Chrobak M, et al. Dynamic thermal management through taskscheduling.In: Proc of the IEEE Int Symposium on Performance Analysis ofSystems and software, Austin, TX: IEEE,2008,191-201
[142] Zhou X, Xu Y, Du Y, et al. Thermal management for3D processors via taskscheduling. In: Proc of the37th Int Conf on Parallel Processing, Portland, OR:IEEE Computer Society,2008,115-122
[143] Chen J J, Hung C M, Kuo T W. On the minimization of the instantaneoustemperature for periodic real-time tasks. In: Proc of the13th IEEE Real-Timeand Embedded Technology and Applications Symposium, Washington, USA:IEEE Computer Society,2007,236-248
[144] Aydin H, Melhem R, Mosse D, et al. Dynamic and aggressive schedulingtechniques for power-aware real-time systems. In: Proc of the22nd IEEEReal-Time Systems Symposium, Washington, DC, USA: IEEE Computer Society,2001,95-105
[145] Vazirani V V. Approximation algorithms. Springer,2001
[146] Yuan L, Qu G. ALT-DVS: dynamic voltage scaling with awareness of leakageand temperature for real-time systems. In: Proc of the2nd NASA/ESA Conf onAdaptive Hardware and Systems, Edinburgh: IEEE Computer Society,2007,660-670
[147] Jayaseelan R, Mitra T. Temperature aware scheduling for embedded processors.In: Proc of the22nd Int Conf on VLSI Design, Washington, DC, USA:IEEEComputer Society,2009,541-546
[148] Mulas F, Pittau M, Buttu M, et al. Thermal balancing policy for streamingcomputing on multiprocessor architectures. In: Proc of the Design, Automationand Test in Europe Conf and Exhibition, Belgium: EDAA,2008,734-739
[149] Coskun A K, Rosing T S, Whisnant K, et al. Temperature-aware MPSoCscheduling for reducing hot spots and gradients. In: Proc of the2008Asia andSouth Pacific Design Automation Conf, Seoul: IEEE Computer Society,2008,49-54
[150] Coskun A K, Rosing T S, Whisnant K. Temperature aware task scheduling inMPSoCs. In: Proc of the Conf on Design, Automation and Test in Europe Confand Exhibition, Belgium: EDAA,2007,1659-1664
[151] Thidapat C, Robert P D, Hu X S. Temperature-Aware Scheduling andAssignment for Hard Real-Time Applications on MPSoC. IEEE Transactions onVery Large Scale Integration Systems,2011,19(10):1884-1897
[152] Wang S, Bettati R. Delay analysis in temperature-constrained hard real-timesystems with general task arrivals. In: Proc of the27th IEEE Int Real-TimeSystems Symposium, Washington, DC, USA: IEEE Computer Society,2006,323-332
[153] Chen J J, Wang S, Thiele L. Proactive speed scheduling for real-time tasks underthermal con-straints. In: Proc of the15th IEEE Real-Time and EmbeddedTechnology and Applications Symposium, San Francisco, US: IEEE,2009,141-150
[154] Mutapcic A, Boyd S, Murali S, et al. Processor speed control with thermalconstraints. IEEE Transactions on Circuits and Systems I: Regular Papers,2009,56(9):1994-2008
[155] Rao R, Vrudhula S. Efficient online computation of core speeds to maximize thethroughput of thermally constrained multi-core processors. In: Proc of the IntConf on Computer-Aided Design, NJ, USA: IEEE Press Piscataway,2008,537-542
[156] Jung H, Rong P, Pedram M. Stochastic modeling of a thermally-managedmulti-core system. In: Proc of the45th annual Design Automation Conf, NewYork: ACM,2008,728-733
[157] Sun C, Shang L, Dick R P. Three-dimensional multiprocessor system-on-chipthermal opti-mization. In: Proc of the5th Int Conf on Hardware/SoftwareCodesign and System Synthesis, New York: ACM,2007,117-122
[158] Wang S, Bettati R. Reactive speed control in temperature-constrained real-timesystems. In: Proc of the18th Euromicro Conf on Real-Time Systems(ECRTS’06), MA, USA: Kluwer Academic Publishers Norwell,2006,161-170
[159] Rao R, Vrudhula S, Chakrabarti C, et al. An optimal analytical solution forprocessor speed control with thermal consstraints. In: Proc of the2006IntSymposium on Low Power Electronics and Design, Tegernsee, Germany:ACM,2006,292-297
[160] Yuan L, Leventhal S, Qu G. Temperature-aware leakage minimization techniquefor real-time systems. In: Proc of the IEEE/ACM Int Conf on Computer-aideddesign (ICCAD '06), New York: ACM,2006,761-764
[161] Bao M, Andrei A, Eles P, et al. Temperature-aware idle time distribution forenergy optimization with dynamic voltage scaling. In: Proc of the Design,Automation and Test in Europe Conf and Exhibition, Belgium: EDAA,2010,21-26
[162] Fisher N, Chen J J, Wang S, et al. Thermal-aware global real-time scheduling onmulticore systems. In: Proc of the15th IEEE Real-Time and EmbeddedTechnology and Applications Symposium, San Francisco, CA: IEEE ComputerSociety,2009,131-140
[163] Chantem T, Hu X S, Dick R P. Online work maximization under a peaktemperature constraint, In: Proc of the14th ACM/IEEE Int symposium on Lowpower electronics and design, New York: ACM,2009,105-110
[164] Yang C Y, Chen J J, Thiele L, et al. Energy-efficient real-time task schedulingwith temperature-dependent leakage. In: Proc of the Conf on Design,Automation and Test in Europe, Belgium: EDAA,2010,9-14
[165] Quan G, Chaturvedi V. Feasibility analysis for temperature-constraint hardreal-time periodic tasks. IEEE Transaction on Industrial Informatics,2010,6(3):329-339
[166] Xie Y, Hung W L. Temperature-aware task allocation and scheduling forembedded multiprocessor systems-on-chip (MPSoC) design. The Journal ofVLSI Signal Processing,2006,45(3):177-189
[167]汪尔康主编.生命分析化学.北京：科学出版社,2006.7:667-688
[168] Wu H L, Shibukawa M, Oguma K. An alternating trilinear decomposition methodwith application to calibration of HPLC-DAD for simultaneous determination ofoverlapped chlorinated aromatic hydrocarbons. Journal of Chemo metrics,1998,12(1):1-26
[169] Maharatna K, Dhar A S, Banerjee S. A VLSI array architecture for realization ofDFT.DHT, DCT and DST. Signal Process,2001,81(9):1813-1822
[170] Mingqian T Z, Madhukumar A S, Chin F. QRD-RLS Adaptive Equalizer and itsCORDIC-Based Implementation for CDMA Systems. Int Journal on Wireless&Optical Communications,2003,1(1):25-39
[171] Pramod K M, Javier V, Juang T B, et al.50Years of CORDIC: Algorithms,Architectures, and Applications. IEEE Transactions on Circuits and Systems,2009,56(9):1893-1907
[172] Intel Corporation. Intel PXA255Processor, Developer's Manual. March2003