基于FPGA的影像监测系统的设计与实现
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摘要
随着产业工艺进化,元件微型化趋势不断推进,AOI在SMT业内蓬勃发展,新的元件规格对原有的AOI系统的处理精度及速度提出了挑战,而另一种AOI系统架构更显优势:阵列影像侦测系统。现阶段的目标是完成一个适用这种架构、具备完整功能的子影像系统,包括影像输入、存储、传输、处理和输出五大模块。
     本设计的主要工作是进行影像输入模块和影像处理模块的设计。
     影像获取模块的设计参考影像获取的主要芯片——感光芯片的器件数据手册,进行芯片驱动,对从芯片获取的原始数据进行相应处理得到系统需要的影像数据。这部分设计是给系统输入能达到的最清晰并且正确的原始影像数据。
     影像处理模块的设计主要是:以数据流为中心设计了模块的架构,包括数据存取和数据处理两部分;提出一种新的快速图像识别方法,阐述了它的原理、验证、设计方法,并最终实现了这个新的图像识别方法。
     整个系统的主控芯片是Xilinx公司的Spartan3E系列1200E,使用VHDL语言设计开发,实现整个系统的驱动、控制。涉及到:300W像素CMOS感光芯片的开发(同步时序、RGB处理、I2C总线协议), SDRAM的开发(SDRAM内部控制系统和DMA控制),Gigabit Ethernet通讯系统的建立(包括芯片IP1000A的开发和UDP协议的FPGA实现),影像处理技术。
     系统各个功能模块均经过测试,达到了预期结果。实践证明,本文的研究成果和文中所描述的设计思路和实现方法是合理的、切实可行的,对于类似的影像系统开发具有一定的参考价值。
With the development of the industry techniques, AOI is flourished and progressing quickly. Facing the challenge, which from the new part specification, another AOI system architecture is brought forward, that is Array, arranged Image System. Recently, the goal is to complete a child system of entire function, and suit for this architecture, including image input, storage, transmission, process, and output module.
     The image input and process module is the main subject of the paper.
     The image input module is developed based on the datasheet of the CMOS sensor, which is the main chip for image input module. The job is mainly done on the driver of the chip, and what should be done for the transformation from the raw data obtained from the chip to image data. The design is aimed at the most and accurate original image data of system’s highest ability.
     The design of image process module is mainly discussed on: the structure of the module is based on the data flow, includes data access and data process; and a new and specialized image recognizing method, the principle and implement, veryfication of which is discussed.
     The system is mainly in the charge of Spartan 3E 1200E, which is produced by Xilinx, corporation, using VHDL language describing the driver and control of the entire system. The development of the CMOS sensor (including timing synchronization, RGB raw data process), 32M SDRAM chip (the inner coding system and DMA control design), gigabit Ethernet communication system set-up (chip IP1000A and implement of UDP protocol based on FPGA), and image process techniques is involved.
     Experiment proved that, all the function is done in the rough, and the new image process technology is testified. It is reasonable and practical to design ideas and methods showed in this thesis. And these are valuable for developing similar systems.
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