800MHz-1.2GHz CMOS变带宽自适应锁相环设计
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摘要
本文设计了一个具有变带宽自适应功能的输出频率范围为800MHz到1.2GHz的CMOS锁相环电路。此锁相环电路具有快速锁定和突出的噪声抑制特性,可应用于数字通信系统中接收模块的数据时钟恢复或时钟产生。
基于传统的电荷泵锁相环电路,本论文中设计了一种新型的模拟自适应带宽控制电路模块。具有模拟自适应带宽控制电路模块的变带宽自适应锁相环可根据系统锁定状态和输入信号相位差自动调节系统环路带宽,从而实现低噪声和快速锁定。对于鉴频鉴相器电路模块设计,采用了新型TSPC结构D触发器,满足了设计指标中对于输入信号频率百兆的速度要求;同时,通过加入延时单元解决了死区问题。对于压控振荡器模块的设计,则使用负歪斜延迟单元组成的双延迟回路环形振荡器,实现了设计要求的输出频率范围。
变带宽自适应锁相环的设计是基于Charted 0.35um EEPROM工艺,并采用了自顶向下的设计方法。系统级设计过程中,基于给出的变带宽自适应锁相环环路增益KLOOP和带宽控制电压的VBW的回归迭代公式,使用Matlab对包含模拟自适应带宽控制模块的整体变带宽自适应锁相环进行了稳定性分析。电路级设计过程中,使用Cadence Spectre RF对各个模块和整体电路进行仿真与验证。
在五种工艺角下,本论文所设计的变带宽自适应锁相环均能满足800MHz到1.2GHz的输出频率范围要求,并且建立时间均小于2μs。在1GHz的输出频率下,位于500kHz频偏处的相位噪声为-93dBc/Hz,整体电路的功耗为23.8mW。此外,通过对普通电荷泵锁相环和带有模拟自适应带宽控制模块的变带宽自适应锁相环的锁定时间和环路带宽的仿真比较,验证了变带宽自适应锁相环的快速锁定和低噪声性能。仿真结果表明,变带宽自适应锁相环的设计实现了带宽自动调节的设计目标,它的各项参数也均达到了设计指标的要求。
A Phase Locked Loop (PLL) with Analog Adaptive Bandwidth Control (AABC) and an 800MHz to 1.2GHz output range has been designed in this paper. The Adaptive PLL (APLL) can be widely used for Clock & Data Recovery (CDR) or Clock Generation in high-speed data communication systems since its special performance in fast locking and noise immunity.
A new-type AABC has been presented based on conventional Charge pump PLL (CP-PLL) circuit. The APLL with AABC block can control the loop bandwidth according to the locking status and the amount of inputs’phase error adaptively; and consequently low-noise and fast-lock performance are achieved. In the design of Phase Frequency Detector (PFD), D Flip Flop (DFF) with the True Signal Phase Clock (TSPC) structure is adopted to satisfy the requirement of a hundred megahertz input frequency. And a delay cell is added in PFD to eliminate Dead Zone. Furthermore, the dual-delay path technique is adopted in Voltage Controlled Oscillator (VCO) design to implement high oscillation frequency and obtain a wide tuning range.
Based on Chartered 0.35μm EEPROM process, the APLL is designed by means of Top to Down design method. The stability analyse of APLL has been done using Matlab. Then, the essential blocks and the whole circuit have been design in schematic and simulated using Cadence Spectre RF.
In all five process corner, the designed APLL satisfies an 800MHz to 1.2GHz output range and a 2μs maximum settling time. Working at 1GHz, the phase noises are–93dBc/Hz at 500 kHz offset, and the whole circuit draws 7.2mA current from 3.3V supply. Furthermore, the fast locking and noise immunity characteristic are verified by contrasting APLL and conventional CP-PLL. The simulation results show that the designed APLL realizes the function of adaptive bandwidth control and meets the design specification.
基于传统的电荷泵锁相环电路,本论文中设计了一种新型的模拟自适应带宽控制电路模块。具有模拟自适应带宽控制电路模块的变带宽自适应锁相环可根据系统锁定状态和输入信号相位差自动调节系统环路带宽,从而实现低噪声和快速锁定。对于鉴频鉴相器电路模块设计,采用了新型TSPC结构D触发器,满足了设计指标中对于输入信号频率百兆的速度要求;同时,通过加入延时单元解决了死区问题。对于压控振荡器模块的设计,则使用负歪斜延迟单元组成的双延迟回路环形振荡器,实现了设计要求的输出频率范围。
变带宽自适应锁相环的设计是基于Charted 0.35um EEPROM工艺,并采用了自顶向下的设计方法。系统级设计过程中,基于给出的变带宽自适应锁相环环路增益KLOOP和带宽控制电压的VBW的回归迭代公式,使用Matlab对包含模拟自适应带宽控制模块的整体变带宽自适应锁相环进行了稳定性分析。电路级设计过程中,使用Cadence Spectre RF对各个模块和整体电路进行仿真与验证。
在五种工艺角下,本论文所设计的变带宽自适应锁相环均能满足800MHz到1.2GHz的输出频率范围要求,并且建立时间均小于2μs。在1GHz的输出频率下,位于500kHz频偏处的相位噪声为-93dBc/Hz,整体电路的功耗为23.8mW。此外,通过对普通电荷泵锁相环和带有模拟自适应带宽控制模块的变带宽自适应锁相环的锁定时间和环路带宽的仿真比较,验证了变带宽自适应锁相环的快速锁定和低噪声性能。仿真结果表明,变带宽自适应锁相环的设计实现了带宽自动调节的设计目标,它的各项参数也均达到了设计指标的要求。
A Phase Locked Loop (PLL) with Analog Adaptive Bandwidth Control (AABC) and an 800MHz to 1.2GHz output range has been designed in this paper. The Adaptive PLL (APLL) can be widely used for Clock & Data Recovery (CDR) or Clock Generation in high-speed data communication systems since its special performance in fast locking and noise immunity.
A new-type AABC has been presented based on conventional Charge pump PLL (CP-PLL) circuit. The APLL with AABC block can control the loop bandwidth according to the locking status and the amount of inputs’phase error adaptively; and consequently low-noise and fast-lock performance are achieved. In the design of Phase Frequency Detector (PFD), D Flip Flop (DFF) with the True Signal Phase Clock (TSPC) structure is adopted to satisfy the requirement of a hundred megahertz input frequency. And a delay cell is added in PFD to eliminate Dead Zone. Furthermore, the dual-delay path technique is adopted in Voltage Controlled Oscillator (VCO) design to implement high oscillation frequency and obtain a wide tuning range.
Based on Chartered 0.35μm EEPROM process, the APLL is designed by means of Top to Down design method. The stability analyse of APLL has been done using Matlab. Then, the essential blocks and the whole circuit have been design in schematic and simulated using Cadence Spectre RF.
In all five process corner, the designed APLL satisfies an 800MHz to 1.2GHz output range and a 2μs maximum settling time. Working at 1GHz, the phase noises are–93dBc/Hz at 500 kHz offset, and the whole circuit draws 7.2mA current from 3.3V supply. Furthermore, the fast locking and noise immunity characteristic are verified by contrasting APLL and conventional CP-PLL. The simulation results show that the designed APLL realizes the function of adaptive bandwidth control and meets the design specification.
引文
[1]张厥盛,郑继禹,万心平,锁相技术,西安:西安电子科技大学出版社,2000
[2] Padmanabhan, M.,Martin, K., A CMOS analog multi-sinusoidal phase locked loop,IEEE Journal of Solid-State Circuits,vol. 29 ,pp. 1046-1057 ,Sept. 1994
[3] Roland E.Best, Phase-Locked Loops Design, Simulation And Applications, U.S.A: Mc Graw Hill, 2003
[4] Luong, Howard Cam, Low-Voltage CMOS RF Frequency Synthesizers, England: Cambridge University Press, 2004
[5] J. Dunning et al., An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors, IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995
[6] B. Kim, D. N. Helman, and P.R.Gray, A 30-MHz hybrid analog/digital clock recovery circuit in 2-um CMOS, IEEE J. Sold-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990
[7] G. Roh, Y. Lee, B. Kim, An optimum phase-acquisition technique for charge-pump phase-locked loops, IEEE Trans. Circuit Syst. II, vol. 44, pp. 729-740, Sept. 1997
[8] B. Chun, Y. Lee, and B. Kim, Design of variable loop gain of dual-loop DPLL, IEEE Trans. Commun., vol. 45, pp. 1520-1522, Dec. 1997
[9] P. F. Driessen, DPLL bit synchronizer with rapid acquisition using adaptive Kalman filtering techniques, IEEE Trans. Commun., vol. 452, pp.2673-2675, Sept. 1994
[10]毕查德·拉扎维,模拟CMOS集成电路设计(陈贵灿等),西安市:西安交通大学出版社,2003
[11] Thomas H.Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition, Beijing: Publishing House of Electronics Industry, 2005, 659-762
[12] Ali Hajimiri, Thomas H. Lee, A General Theory of Phase Noise in Electrical Oscillators, IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998
[13] Ali Hajimiri, Thomas H. Lee, Corrections to“A General Theory of Phase Noise in Electrical Oscillators”, IEEE J. Solid-State Circuits, vol. 33, Jun. 1998
[14] M. Mizuno et al., A 0.18um CMOS hot-standby phase-locked loop using a noise immune adaptive-gain voltage-controlled oscillator, ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 1995
[15] Joonsuk Lee, Beomsup Kim, A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control, IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, August. 2000
[16] S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice Hall,1995
[17] Syed Irfan Ahmed, B. Eng, Submicron CMOS Components For PLL-Based Frequency Synthesis, Master, Carleton University, Aug, 2002
[18] A. J. Bishop, et al., Adaptive Phase Locked Loop for Video Signal Sampling, Circuits and Systems, 1992. ISCAS’92. Proceedings., vol. 4, pp. 1664-1667, May. 1992
[19] Dae Sun Oh, et al., Convergence Analysis of a PLL for a Digital Recording Channel with an Adaptive Partial Response Equalizer, Global Telecommunication Conference, 1996. GLOBECOM’96., vol.2, pp. 979-983, Nov. 1996
[20] Masaomi Toyama, et al., A Design of a Compact 2 Hz-PLL with a New Adaptive Active Loop Filter Circuit, VLSI Circuits, 2003. Digest of Technical Papers, pp. 185-188, Jun. 2003
[21]刘常澍,数字逻辑电路,北京市:国防工业出版社,2002
[22] Phillip E. Allen, Douglas R. Holberg, CMOS模拟集成电路设计(冯军,李智群),北京市:电子工业出版社,2005
[23]吴大正,信号与线性系统分析,北京市:高等教育出版社,2000
[24]张志涌,徐彦琴,MATLAB教程,北京市:北京航空航天大学出版社,2004
[25]樊勃,SOC用400MHz-800MHz锁相环设计:[硕士学位论文],天津:南开大学,2006
[26] Won Hyo Lee, Jun Dong Cho, A High Speed and Low Power Phase-Frequency Detector and Charge-pump, Design Automation Conference, 1999. Proceedings of the ASP-DAC’99, vol. 1, pp. 269-272, Jan. 1999
[27] Henrik O. Johansson, A Simple Precharged CMOS Phase Frequency Detector, IEEE J. Solid-State Circuits, vol. 33, pp. 295-299, Feb. 1998
[28] Kun-Seok Lee et al., Phase Frequency Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile Communication Systems, Solid-State Circuits Conference, 2003. ESSCIRC’03, pp. 525-528, Sep. 2003 65
[29] Hai Qi Liu, Wang Ling Goh, 1.8-V 10GHz Ring VCO Design Using 0.18-um CMOS Technology, SOC Conference, 2005. Proceedings, pp. 77-78, Sep. 2005
[30] Ge Yan, Chen Zhongjian, et al., Design of CMOS High Speed Self-Regulating VCO Using Negative Skewed Delay Scheme, Solid-State and Integrated Circuits Technology, 2004. Proceedings, vol. 2, pp. 1333-1336, Oct. 2004
[31] Chan-Hong Park, Beomsup Kim, A Low-Noise 900-MHz VCO in 0.6-um CMOS, IEEE J. Sold-State Circuits, vol. 34, pp. 586-591, May. 1999
[32] Kuo Hsing Cheng, et al., A Low Noise 2.0GHz CMOS VCO Design, Circuits and Systems, 2003. MVVSCAS’03, vol. 1, pp. 205-208, Dec. 2003
[33] Tie Sun, et al., A VCO with High Supply Noise Rejection and Its Application to PLL Frequency Synthesizer, Communications and Information Technology, 2005. ISCIT 2005, pp. 1027-1030, Oct. 2005
[34] Yalcin Alper Eken, John P. Uyemura, Multiple-GHz Ring and LC VCOs in 0.18um CMOS, Radio Frequency Inteqrated Circuits(RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE, pp. 475-478, Jun. 2004
[35] Mohamad El-Hage, Fei Yuan, An Overview Of Low-Voltage VCO Delay Cells And A Worst-Case Analysis Of Supply Noise Sensitivity, Electrical and Computer Engineering, 2004. Canadian Conference on, vol. 3, pp. 1785-1788, May. 2004
[36] Seog-Jun Lee et al., A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme, IEEE J. Sold-State Circuits, vol. 32, pp. 289-291, Feb. 1997
[2] Padmanabhan, M.,Martin, K., A CMOS analog multi-sinusoidal phase locked loop,IEEE Journal of Solid-State Circuits,vol. 29 ,pp. 1046-1057 ,Sept. 1994
[3] Roland E.Best, Phase-Locked Loops Design, Simulation And Applications, U.S.A: Mc Graw Hill, 2003
[4] Luong, Howard Cam, Low-Voltage CMOS RF Frequency Synthesizers, England: Cambridge University Press, 2004
[5] J. Dunning et al., An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors, IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995
[6] B. Kim, D. N. Helman, and P.R.Gray, A 30-MHz hybrid analog/digital clock recovery circuit in 2-um CMOS, IEEE J. Sold-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990
[7] G. Roh, Y. Lee, B. Kim, An optimum phase-acquisition technique for charge-pump phase-locked loops, IEEE Trans. Circuit Syst. II, vol. 44, pp. 729-740, Sept. 1997
[8] B. Chun, Y. Lee, and B. Kim, Design of variable loop gain of dual-loop DPLL, IEEE Trans. Commun., vol. 45, pp. 1520-1522, Dec. 1997
[9] P. F. Driessen, DPLL bit synchronizer with rapid acquisition using adaptive Kalman filtering techniques, IEEE Trans. Commun., vol. 452, pp.2673-2675, Sept. 1994
[10]毕查德·拉扎维,模拟CMOS集成电路设计(陈贵灿等),西安市:西安交通大学出版社,2003
[11] Thomas H.Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition, Beijing: Publishing House of Electronics Industry, 2005, 659-762
[12] Ali Hajimiri, Thomas H. Lee, A General Theory of Phase Noise in Electrical Oscillators, IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998
[13] Ali Hajimiri, Thomas H. Lee, Corrections to“A General Theory of Phase Noise in Electrical Oscillators”, IEEE J. Solid-State Circuits, vol. 33, Jun. 1998
[14] M. Mizuno et al., A 0.18um CMOS hot-standby phase-locked loop using a noise immune adaptive-gain voltage-controlled oscillator, ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 1995
[15] Joonsuk Lee, Beomsup Kim, A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control, IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, August. 2000
[16] S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice Hall,1995
[17] Syed Irfan Ahmed, B. Eng, Submicron CMOS Components For PLL-Based Frequency Synthesis, Master, Carleton University, Aug, 2002
[18] A. J. Bishop, et al., Adaptive Phase Locked Loop for Video Signal Sampling, Circuits and Systems, 1992. ISCAS’92. Proceedings., vol. 4, pp. 1664-1667, May. 1992
[19] Dae Sun Oh, et al., Convergence Analysis of a PLL for a Digital Recording Channel with an Adaptive Partial Response Equalizer, Global Telecommunication Conference, 1996. GLOBECOM’96., vol.2, pp. 979-983, Nov. 1996
[20] Masaomi Toyama, et al., A Design of a Compact 2 Hz-PLL with a New Adaptive Active Loop Filter Circuit, VLSI Circuits, 2003. Digest of Technical Papers, pp. 185-188, Jun. 2003
[21]刘常澍,数字逻辑电路,北京市:国防工业出版社,2002
[22] Phillip E. Allen, Douglas R. Holberg, CMOS模拟集成电路设计(冯军,李智群),北京市:电子工业出版社,2005
[23]吴大正,信号与线性系统分析,北京市:高等教育出版社,2000
[24]张志涌,徐彦琴,MATLAB教程,北京市:北京航空航天大学出版社,2004
[25]樊勃,SOC用400MHz-800MHz锁相环设计:[硕士学位论文],天津:南开大学,2006
[26] Won Hyo Lee, Jun Dong Cho, A High Speed and Low Power Phase-Frequency Detector and Charge-pump, Design Automation Conference, 1999. Proceedings of the ASP-DAC’99, vol. 1, pp. 269-272, Jan. 1999
[27] Henrik O. Johansson, A Simple Precharged CMOS Phase Frequency Detector, IEEE J. Solid-State Circuits, vol. 33, pp. 295-299, Feb. 1998
[28] Kun-Seok Lee et al., Phase Frequency Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile Communication Systems, Solid-State Circuits Conference, 2003. ESSCIRC’03, pp. 525-528, Sep. 2003 65
[29] Hai Qi Liu, Wang Ling Goh, 1.8-V 10GHz Ring VCO Design Using 0.18-um CMOS Technology, SOC Conference, 2005. Proceedings, pp. 77-78, Sep. 2005
[30] Ge Yan, Chen Zhongjian, et al., Design of CMOS High Speed Self-Regulating VCO Using Negative Skewed Delay Scheme, Solid-State and Integrated Circuits Technology, 2004. Proceedings, vol. 2, pp. 1333-1336, Oct. 2004
[31] Chan-Hong Park, Beomsup Kim, A Low-Noise 900-MHz VCO in 0.6-um CMOS, IEEE J. Sold-State Circuits, vol. 34, pp. 586-591, May. 1999
[32] Kuo Hsing Cheng, et al., A Low Noise 2.0GHz CMOS VCO Design, Circuits and Systems, 2003. MVVSCAS’03, vol. 1, pp. 205-208, Dec. 2003
[33] Tie Sun, et al., A VCO with High Supply Noise Rejection and Its Application to PLL Frequency Synthesizer, Communications and Information Technology, 2005. ISCIT 2005, pp. 1027-1030, Oct. 2005
[34] Yalcin Alper Eken, John P. Uyemura, Multiple-GHz Ring and LC VCOs in 0.18um CMOS, Radio Frequency Inteqrated Circuits(RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE, pp. 475-478, Jun. 2004
[35] Mohamad El-Hage, Fei Yuan, An Overview Of Low-Voltage VCO Delay Cells And A Worst-Case Analysis Of Supply Noise Sensitivity, Electrical and Computer Engineering, 2004. Canadian Conference on, vol. 3, pp. 1785-1788, May. 2004
[36] Seog-Jun Lee et al., A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme, IEEE J. Sold-State Circuits, vol. 32, pp. 289-291, Feb. 1997