结合数字校正技术的低功耗流水线ADC研究与设计
|
摘要
模数转换器(Analog-to-Digital Converter, ADC)是将模拟信号转换成数字信号的电子系统，在无线通讯、航空航天、医疗等领域有广泛的应用。在这些系统中，为降低成本，模数转换器常与其它数字电路集成到同一硅片上，组成片上系统(System-on-Chip,SOC)。作为模拟世界和数字世界之间桥梁的模数转换器，已经是SOC中不可或缺的部分。而随着片上系统广泛应用和半导体CMOS工艺的进步，要求片上系统中的模拟电路如ADC等和数字电路使用相同大小的电源电压，进一步降低SOC的成本。以现代通信和消费类电子产品为代表的手持设备应用发展，不但推动了高速、高精度ADC的发展，而且对芯片的功耗也提出了更为苛刻的要求。高速高精度的实现往往需要以增加功耗和面积为代价，因此在ADC具有高速高精度特性的同时，降低功耗是目前研究的热点领域。
本论文深入研究了应用于数字视频和数字通讯等领域的低功耗、高精度流水线ADC，提出了一种采用运放共享技术的无采样保持电路前端架构，提出了一种新的数字后台校正算法，完成了两款流水线ADC的设计，并完成其中一款流水线ADC的流片和测试工作。本论文的主要成果和研究工作包括：
1.详细分析了流水线ADC传统无采样保持运放前端架构中存在的孔径误差等非理想因素，提出了一种新的将采样保持电路与首级余量增益电路（SMDAC）合并的前端架构。使ADC电路系统在消除孔径误差的同时，无需复位时钟，系统功耗也得到了进一步降低。
2.为实现ADC低功耗设计，在采用级间运放共享和逐级缩减等技术同时，提出采用数控方法控制运放偏置电流，可使ADC在不同应用场合进一步降低功耗。为消除传统级间运放共享引入的记忆效应影响，提出了采用偏置与输入轮换技术。
3.针对影响ADC速度和精度的采样开关，提出了一种对称型栅压自举开关电路，削弱了采样开关电荷注入效应的影响，进一步改善了采样的线性度。
4.研究了流水线ADC的数字后台校正技术，提出了一种新的适用于每级多比特结构流水线ADC的信号相关抖动校正算法。该算法可对运放有限增益和电容失配等非理想因素造成的误差在数字域内进行校正，使用该算法达到13-bit测量精度所要求的采样点为6224个，所需校正时间仅为1.34秒。该算法无需复杂运算，具有实现电路结构简单，系统工作速度快，节省芯片面积等优点，能有效提高流水线ADC系统的性能。
Analog to digital converter (ADC), convers the analog signals in real world to digitalsignals which is more convenient for furer processing. It is widely used in the system ofmobile wireless communication、aerospace and medical treatment, etc. In the SOC of theseapplications systems, the ADC resides on the same silicon (system-on-a-chip) with other largedigtal circuits in order to reduce overhead cost. As the bridge between analog domain anddigital domain, the ADC is the indispensable part of SoC. As required by system-on-a-chipintegration and state-of-the-art CMOS technology, analog supply voltage is forced to decrease,following that of digital part. Meanwhile, handset equipments impose stringent requirementon power consumption of the ADC and accelerate the development of high-speedhigh-resolution ADC. To acquire high speed and high accuracy are often needed to increasethe cost of power and area. Therefore, how to achieve high-speed, high-resolutionand,low-power consumption simultaneously becomes a focus.
This work focused on the the high resolution and low-power pipelined ADC for dgitalvideo application and modern communication system. Since apperture error was induced bythe conversional SHA-less architecture, to overcome it, a novel SHA-less architecture as wellas circuital level tecniques are proposed for designing high-resolution low-power pipelinedADC. A new digital background calibration with high convergence rate is also proposed toimprove the system accuracy. Two chips were designed and one of the two was measured. Thespecific research contributions of this work include:
1. Since the samling rate of pipeline ADC without a SHA can be limited due to theaperture error and other nonideal factors, a novel sample-and-hold amplifier(SHA) merged with the first mutiplying digital to analog converter (SMDAC)architecture is proposed, and to achieve high speed and low power consumptionwithout reset phase.
2. To achieve low-power design, opamp-sharing between successive stage andstage scaling-down were adopted. And more, a SC bias current generator wasintroduced to effectively control power consumption for different application. To get rid of the problem of memory effect, the bias-and-input interchangingtechnique for the OTA in the MDAC is proposed.
3. A symmetry gate-bootstrapping circuit is proposed for the bottom-samplingswitch of sample-and-hold circuit or SMDAC. It minimizes the effect of switchcharge injection, suppresses the effect of bulk bias, and improves the linearity ofsampling result.
4. Digtial background calibration technique for pipelined ADC is investigated, anda novel signal-dependent dithering algorithm is propsed for multibit per stage, inwhich capacitor mismantch and gain error in multibit stage can be calibrated asone error. This scheme shortens the calibration time, reduces the analog circuitdesign complexity, as well as improves the ADC linearity. This calibrationtechnique speeds up the convergence rate of calibration and takes only6224samples to achieve13-bit resolution. It costs1.34s to calibrate this ADC at100MS/s. This calibration algorithm is easy to realize without complicatedmathmatic operation and works at very high speed.
本论文深入研究了应用于数字视频和数字通讯等领域的低功耗、高精度流水线ADC，提出了一种采用运放共享技术的无采样保持电路前端架构，提出了一种新的数字后台校正算法，完成了两款流水线ADC的设计，并完成其中一款流水线ADC的流片和测试工作。本论文的主要成果和研究工作包括：
1.详细分析了流水线ADC传统无采样保持运放前端架构中存在的孔径误差等非理想因素，提出了一种新的将采样保持电路与首级余量增益电路（SMDAC）合并的前端架构。使ADC电路系统在消除孔径误差的同时，无需复位时钟，系统功耗也得到了进一步降低。
2.为实现ADC低功耗设计，在采用级间运放共享和逐级缩减等技术同时，提出采用数控方法控制运放偏置电流，可使ADC在不同应用场合进一步降低功耗。为消除传统级间运放共享引入的记忆效应影响，提出了采用偏置与输入轮换技术。
3.针对影响ADC速度和精度的采样开关，提出了一种对称型栅压自举开关电路，削弱了采样开关电荷注入效应的影响，进一步改善了采样的线性度。
4.研究了流水线ADC的数字后台校正技术，提出了一种新的适用于每级多比特结构流水线ADC的信号相关抖动校正算法。该算法可对运放有限增益和电容失配等非理想因素造成的误差在数字域内进行校正，使用该算法达到13-bit测量精度所要求的采样点为6224个，所需校正时间仅为1.34秒。该算法无需复杂运算，具有实现电路结构简单，系统工作速度快，节省芯片面积等优点，能有效提高流水线ADC系统的性能。
Analog to digital converter (ADC), convers the analog signals in real world to digitalsignals which is more convenient for furer processing. It is widely used in the system ofmobile wireless communication、aerospace and medical treatment, etc. In the SOC of theseapplications systems, the ADC resides on the same silicon (system-on-a-chip) with other largedigtal circuits in order to reduce overhead cost. As the bridge between analog domain anddigital domain, the ADC is the indispensable part of SoC. As required by system-on-a-chipintegration and state-of-the-art CMOS technology, analog supply voltage is forced to decrease,following that of digital part. Meanwhile, handset equipments impose stringent requirementon power consumption of the ADC and accelerate the development of high-speedhigh-resolution ADC. To acquire high speed and high accuracy are often needed to increasethe cost of power and area. Therefore, how to achieve high-speed, high-resolutionand,low-power consumption simultaneously becomes a focus.
This work focused on the the high resolution and low-power pipelined ADC for dgitalvideo application and modern communication system. Since apperture error was induced bythe conversional SHA-less architecture, to overcome it, a novel SHA-less architecture as wellas circuital level tecniques are proposed for designing high-resolution low-power pipelinedADC. A new digital background calibration with high convergence rate is also proposed toimprove the system accuracy. Two chips were designed and one of the two was measured. Thespecific research contributions of this work include:
1. Since the samling rate of pipeline ADC without a SHA can be limited due to theaperture error and other nonideal factors, a novel sample-and-hold amplifier(SHA) merged with the first mutiplying digital to analog converter (SMDAC)architecture is proposed, and to achieve high speed and low power consumptionwithout reset phase.
2. To achieve low-power design, opamp-sharing between successive stage andstage scaling-down were adopted. And more, a SC bias current generator wasintroduced to effectively control power consumption for different application. To get rid of the problem of memory effect, the bias-and-input interchangingtechnique for the OTA in the MDAC is proposed.
3. A symmetry gate-bootstrapping circuit is proposed for the bottom-samplingswitch of sample-and-hold circuit or SMDAC. It minimizes the effect of switchcharge injection, suppresses the effect of bulk bias, and improves the linearity ofsampling result.
4. Digtial background calibration technique for pipelined ADC is investigated, anda novel signal-dependent dithering algorithm is propsed for multibit per stage, inwhich capacitor mismantch and gain error in multibit stage can be calibrated asone error. This scheme shortens the calibration time, reduces the analog circuitdesign complexity, as well as improves the ADC linearity. This calibrationtechnique speeds up the convergence rate of calibration and takes only6224samples to achieve13-bit resolution. It costs1.34s to calibrate this ADC at100MS/s. This calibration algorithm is easy to realize without complicatedmathmatic operation and works at very high speed.
引文
[1]吴兴斌.高速A/D转换器的研究进展及发展趋势[J].微电子学，2009，139(3):420-423.
[2] Murmann B., ADC performance Survey,1997-2013[OL], http://www.stanford.edu/~murmann/adcsurvey.html.
[3] Cheng W., Ali W., Choi M. J., et al. A3b40GS/s ADC-DAC in0.12m SiGe [C]. In50thInternational Solid-State Circuits Conference (ISSCC), Digest of Technical Papers. Vol.12004:262-263.
[4] Schvan P., Bach J., Falt C., et al. A24GS/s6b ADC in90nm CMOS [C]. In54thInternatonal Solid-State Circuits Conference (ISSCC), Digest of Technical Papers.Vol.1,2008:544-545.
[5] Marcu C., Chowdhury D., Thakkar C., et al. A90nm CMOS low-power60-GHztransceiver with intergrated baseband ciruitry [C]. IEEE J. Solid-State Circuits,2009，44(12)：3434-3447.
[6]李福乐.适宜于系统集成的高速高精度模数转换电路设计技术研究[D].博士学位论文，清华大学电子工程系,2003.
[7] Li J., Zeng X.Y., Xie L., et al. A1.8-V22-mW10-bit30-MS/s Pipelined CMOS ADC forLow-Power Subsamping Applications [J]. IEEE J. Solid-State Circuits,2008,43(2):321-329.
[8] Luo L., Lin K.L., Cheng L., et al. A Digitally calibrated14-bit Linear100-MS/s PipelinedADC with Wideband Sampling Frontend [C]. IEEE Proc. ESSCIRC,2009:472-475.
[9] Guo D.D., Li F.L., Zhang C., et al. A13-bit8MSample/s pipeline A/D Converter [J].Journal of Semiconductors,2009,30(2):025006-5.
[10] Yin X.M., Wei Q., Xu L., et al. A Low Power12-b40-MS/s Pipeline ADC [J]. Journal ofSemiconductors,2010,31(3):035006-1.
[11] Long S.L., Shi L.X., Wu J.H., et al. A1.8V10bit100Msps Pipelined Analog to DigitalConveter [J]. Journal of Semiconductors,2008,29(5):923-929.
[12] Moore G. Progress in digital integrated electronics [C]. IEDM Tech Dig.1975:11-13.
[13]拉扎维.模拟CMOS集成电路设计[M].西安交通大学出版社,2004.
[14] Murmann B., Boser B. E. Digitally Assisted Pipeline ADCs Theory and implementation[M]. Springer,2004.
[15] Karanicolas A.N.，Lee H.S., Bacrania K. A15b1-MS/s Digitally Self-CalibratedPipelined ADC [J]. IEEE J. Solid-State Circuits，1993，28(12)：1207-1215.
[16] Xing H., et al, High-resolution ADC linearity testing using a fully digital-compatibleBIST strategy [J].IEEE Trans. Instrumentation and Measurement,2009,58(8):2697-2705.
[17] Chang D.Y., Li J., Moon U. Radix-based digital lcalibration techniques for multi-stagerecycling pipelined ADCs [J]. IEEE Trans. Circuits and Systems Ⅰ,2004,51(11):2133-2140.
[18] Ming J., Lewis S.H. An8-bit80-Msample/s pipelined analog-to-digital converter withbackground calibration [J]. IEEE J. Solid-State Circuits，2001，36(10)：1489-1497.
[19] Li J.P., Moon U.K. Background calibration techniques for multistage pipelined ADCswith digital redundancy [J]. IEEE Trans. Circuits and Systems Ⅱ: Analog and DigitalSignal Processing,2003,50(9):531-538.
[20] Liu H.C., Lee Z.M., Wu H.T. A15b20MS/s CMOS pipelined ADC with digitalbackground calibraion [C]. In54thInternatonal Solid--State Circuits Conference (ISSCC),Digest of Technical Papers. Vol.1,2004:454-455.
[21] Widrow B.，Samuel D. S.自适应信号处理[M].北京：机械工业出版社，2008.
[22] Chiu Y., Tsang C.Y.W. Least Mean square Adaptive Digtial Background Calibration ofPipelined Analog-to-ditial Converters [J]. IEEE Transactions on Circuits and Systems Ⅰ:Regular Papers,2004,51(1):38-46.
[23] Shu Y.S., Song B.S. A15-bit linear20-MS/s pipelined ADC digitally Calibrated withsignal-dependent dithering [J]. IEEE J. Solid-State Circuits，2008，43(2):342-350.
[24] Li W., Li F., Guo D., et al. An Undersampling14-bit Cyclic ADC with over100dBSFDR [J]. Chinese Journal of Semiconductors,2010,31:025008-6.
[25] Zhou L., Luo L., Ye F. et al. A12-bit100-Ms/s pipelined ADC with digital backgroundcalibration [J]. Journal of Semiconductors,2009,30:115007-5.
[26] Ahmed I. Pipelined ADC Design and Enhancement Techniques [M]. Springer,2010.
[27] Figueirdo P.M., Vital J.C. Offset Reduction Technique in high-speed analog-to-ditialconverter: Analysis, Deisign and Tradeoffs [M]. Springer2009:1-62.
[28] Yoshii Y., Asano K., Nakamura M., et al. An8b100MS/s Flash ADC [J]. IEEE J.Solid-State Circuits，1984，19(6)：842-846.
[29] McCall K.J.，Demler M.J., Plante M.W. A6-bit125MHz CMOS A/D Converter [C].Proceedings of the IEEE1992Custom Integrated Circuits Conference,1992：16.8.1-16.8.4.
[30] Dalton D., Spalding G., Reyhani H., et al. A200-MSPS6-bit Flash ADC in0.6-mCMOS [J]. IEEE Trans. Circuits Syst.,1998,45(11):1433-1444.
[31] Luri M., Declan D. A500-Msample/s6-bit nyquist-rate ADC for disk-drive read channelapplications [J]. IEEE J. Solid-State Circuits，1999,34(7)：912-920.
[32] Choi M., Asad A. A6-b1.3-Gsps AD Converter in0.35m CMOS [J]. IEEE J.Solid-State Circuits，2001,36(12)：1847-1858.
[33] Anwar A.F.M., Khondker A.N. A70-MS/s110-mW CMOS Folding and InterpolatingA/D converter [J]. IEEE J. Solid-State Circuits,1995,30(12):1302-1308.
[34] Lewis S.H., Gray P.R. A Pipelined5-Msample/s9-bit Analog-to-Digtial Converter [J].IEEE J. Solid-State Circuits,1987,22(6):954-961.
[35] Lewis S.H. Optimizing the stage resolution in pipelined, multistage analog-to-digtialconverters for video-rate applications [J]. IEEE Trans. Circuits and Systems Ⅱ: Analogand digital signal processing,1992,39(8):516-523.
[36] Dyer K., Fu D., Lewis S., Hurst P. Analog backgroud calibration of a10b40Msample/sparallel pipelined ADC [C]. IEEE International Solid-State Circuits conference,1998,ED-34(2):142-143.
[37] Song W.C., Choi H.W., Kwak S.U., Song B.S. A10-b20-Msample/s Low-Power CMOSADC [J]. IEEE J. Solid-State Circuits,1987,22(6):514-521.
[38] Nakamura K., Hotta M., Carley L.R., Allsot D.J. Allstot. An85mw,10b,40-Msample/sCMOS parallel-pipelined ADC [J]. IEEE J. Solid-State Circuits,1995,30(4):173-183.
[39] Mukheerjee S., Srinivasan C., Pawar V., et al. A2.5V10-bit SAR ADC [C]. InternationalConference on VLSI Design. Hyderabad, India: IEEE Computer Society,1997,46(1):525-526.
[40] Sheiing Y.N., Bahar J., Zhang P., et al. A low-voltage CMOS5-bit600MHz30mW SARADC for UWB wireless receivers [C]. Midwest Symp. Circuits Syst., Cincinnati, Ohio:IEEE Circuits and Systems Society,2005:187-190.
[41] Li C.C., Ikeda H., Inoue T., et al. A physical poly-Silicon thin film transistors model forcircuit simulations [C]. IEEE Custom Intergrated Circuits Conference. San Jose: IEEESolid-State Circuits Society,2005:403-06.
[42] Boser B.E., Wooley B.A. The design of sigma-delta modulation analog-to-digitalconverters [J]. IEEE J. Solid-State Circuits,1989,23(6):1298-1308.
[43] Signore B.P., Kerth D.A., Sooch N.S., et al. A monolithic20-bit delta-sigma A/Dconverter [J]. IEEE J. Solid-State Circuits,1990,25(6):1311-1316.
[44] Boser B.E., Wooley B.A. A50-MHz multibit sigma-delta modulator for12-b2-MHz A/Dconverter [J]. IEEE J. Solid-State Circuits,1991,26(12):1746-1755.
[45] Shu T., Song B., Bacrania K. A13-b10-Msample/s ADC digitally calibrated withoversampling delta-sigma converter [J]. IEEE J. Solid-State Circuits,1995,30(4):443-452.
[46] Rabii S., Wooley B.A. A1.8-V digital-audio sigma-delta modulator in0.8m CMOS [J].IEEE J. Solid-State Circuits,1997,32(6):783-796.
[47] Dessouky M., Kaiser A. Very low-voltage digital audio-modulator with88-dBdynamic range [J]. IEEE Journal of Solid-State Circuits,2001,36(3):349-355.
[48] Lewis S. H., Fetterman H.S., Gross G.F., et al. A10-b20-Msample/s analog-to-digitalconverters [J]. IEEE J. Solid-State Circuits,1992,27(3):351-358.
[49] Hadidi K. Temes G. C. Error analysis in pipeline A/D converters and its applications [J].IEEE Trans. Circuits and Systems Ⅱ: Analog and digital signal processing,1992,39(8):506-515.
[50] Ynag W., Kelly D., Mehr L., et al. A3-V340-mW14-b75-Msample/s CMOS ADC with85-Db SFDR at Nyquist input [J]. IEEE J. Solid-State Circuits,2001,36(12):1931-1936.
[51] Thomas B. Cho. Low-power Low-Voltage Analog-to-Digital Conversion TechniquesUsing pipelined Architectures [D]. California: University of California, Berkeley,1995.
[52] Cline D., Gray P.R. A power optimized13-b5-Msample/s pipelined analog-to-digitalconverter in1.2-mm CMOS [J]. IEEE J. Solid-State Circuits,1996,28(12):294-303.
[53] Waltari M. Circuit Techniques for Low-voltage and High-Speed A/D Converter [D].Helsinki University of Technology,2002.
[54] Kester W. The Data Conversion Handbook [M]. Elsevier/Newnes,2005.
[55] Shinagawa M., Akazawa Y., Wakimoto T. Jitter Analysis of High-Speed SamplingSystems [J]. IEEE J. Solid-State Circuits,1990,25(1):220-224.
[56] Karanicolas A.N., Lee H.S., Bacrania K. A15b1-MS/s Digitally self-Calibrated PipelineADC [J]. IEEE J. Solid-State Circuits,1993,28(12):1207-1215.
[57] Ginetti B., Jespers P.G.A., Vandemeulebroecke A. A CMOS13-b Cyclic RSD A/DConverter [J]. IEEE J. Solid-State Circuits,1992,27(7):957-966.
[58] Arias J., Boccuzzi V., Quintanilla L., et al. Low-Power Pipeline ADC for Wireless LANs[J]. IEEE J.Solid-state circuits,2004,39(8):1338-1340.
[59] Kwok P.T.F., luong H.C. Power optimized for pipelined analog-to-digital converters [J].IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing,1999,46(5):549-553.
[60]李建.低功耗低电压CMOS流水线模数转换器的结构研究与实现[D].博士学位论文，复旦大学，2008.
[61] Chiu Y., Gray P.R., and Nikolic B. A1.8V14b,10MS/s Pipelined ADC in0.18μmCMOS with99dB SFDR [C]. IEEE International Solid-State Circuits Conference, Digestof Technical Papers,2004:458-539.
[62] Cho T.B, Gray P.R. A10b,20Msample/s,35mW Pipeline A/D Converter [J]. IEEE J.Solid-State Circuits,1995,30(3):166-172.
[63] Waltari M., Halonen K.A. I.1-V,9-Bit Pipelined Switched-Opamp ADC [J]. IEEE J.Solid-State Circuits,2001,36(1):129-134.
[64] Min B.M., Kim P., Bowman F.W., et al. A69-mW10-bit80-MSample/s Pipelined CMOSADC [J]. IEEE J. Solid-State Circuits,2003,38(12):2031-2039.
[65] Fiorenza, J.K., Sepke T., Holloway P., et al. Comparator-Based Switched-CapacitorCircuits for Scaled CMOS technologies [J]. IEEE J. Solid-State Circuits,2006,41(12):2658-26681.
[66] Waltari M., Halonen K. A220-MSample/s CMOS Sample-and-Hold Circuit UsingDouble-Sampling [J]. Analog Integrated Circuits and Signal Processing,1999,18(1):21-31.
[67] Abo A.M., Gray P.R. A1.5-V,10-bit,14-MS/s CMOS pipeline analog-to-digitalconverter [J]. Symposium on VLSI Circuits,1998,33(2):166-169.
[68] Abo A.M., Gray P.R. A1.5-V,10-bit,14.3-MS/s CMOS pipeline analog-to-digitalconverter [J]. IEEE J. Solid-State Circuits,1999,34(5):599-606.
[69] Liu M. Demystifying Switched-Capacitor Circuits [M]. Elsevier,2006.
[70] Abo M. Design for Reliability of Low-voltage, Switched-capacitor Circuits [D]. DoctoralThesis, University of California, Berkeley,1999.
[71] Mehr I., Singer L. A55-mW,10-bit,40-Msample/s Nyquist-Rate CMOS ADC [J]. IEEEJ. Solid-State Circuits,2000,35(3):318-325.
[72] Li J., Zeng X.Y., Xie L., et al. A1.8-V22-mW10-bit30-MS/s Pipelined CMOS ADC forLow-Power Subsampling Application [J]. IEEE J. Solid-State Circuits,2008,43(2):321-329.
[73] Lee B.G., Min B.M., Manganaro G. et al. A14-b100-MS/s Pipelined ADC with aMerged SHA and First MDAC [J]. IEEE J. Solid-State Circuits,2008,43(12):2613-2619.
[74] Min B.M., Kim P., Bowman F.W., Boisvert D.M., Aude A. J. A69-mW10-bit80-MSample/s pipelined CMOS ADC [J]. IEEE J. Solid-State Circuits,2003,38(12):2031-2039.
[75] Nagaraj K., Fetterman H., Anidjar J., et al. A250-mW,8-b,52-MsampleParallel-pipelinedA/D Converters with Reduced Number of Amplifiers [J]. IEEE J.Solid-State Circuits,1994,32(3):312-320.
[76] Lee S.H., Song B.S. Digital-Domain Calibration of Multistep Analog-to-DigitalConverters [J]. IEEE J. Solid-State Circuits,1992,27(12):8084-8089.
[77] Chuang S. Y., Scylly T.L. A Digitally Self-Calibrating14-bit10-MHz CMOS PipelinedA/D Converters [D]. IEEE J. Solid-State Circuits,2002,37(6):674-683.
[78] Verma A., Razavi B. A10-Bit500-MS/s55mW CMOS ADC [J]. IEEE J. Solid-StateCircuits,2009,44(11):3039-3050.
[79] Grace C.R., Hurst P.J., Lewis S.H. A12-bit80-MSample Pipelined ADC withBootstrapped Digital Calibration [J]. IEEE J.Solid-State Circuits,2005,40(5):1038-1046.
[80] Daito M., Matsui H., Ueda M., lizuka K. A14-bit20-MS/s pipelined ADC with DigitalDistortion Calibration [A]. IEEE J. Solid-State Circuits,2006,41(11):2417-2423.
[81] Grace C.R., Hurst P.J., Lewis S.H. A12-bit80MS/s pipelined ADC with bootstrappeddigital calibration [J]. IEEE J. Solid-State Circuits,2005,40(5):1038-1046.
[82] Erdogan O.E., Hurst P. J., Lewis S.H. A12-b digital background calibrated algorithmicADC with90-dB THD [J]. IEEE J. Solid-State Circuits,1999,34(12):1812-1820.
[83] Ingino J.M., Wooley B.A. A continuously calibrated12-b,10-MS/s,3.3-V A/D converter[J]. IEEE J. Solid-State Circuits,1998,33(12):1920-1931.
[84] Moon U.K., Song B.S. Background digital calibtation techniques for pipelined ADCs [J].IEEE Trans. Circuits and Systems Ⅱ,1997,44(2):102-109.
[85] Chiu Y., Tsang C.W., Nikolic B., et al. Least-mean-square adaptive ditgital back-groundcalibration of pipelined A/D converters [J]. IEEE Trans. Circutis and System Ⅰ: RegularPapers,2004,51(1):38-46.
[86] Tsang C. Background ADC calibration in digital domain [C]. IEEE Custom IntegratedCircuits Conference,2008:301-304.
[87] Liu W., Chang Y.C., Hsien S.K., et al. A600MS/s30mW0.13μm CMOS ADC arrayachieving over60dB SFDR with adaptive digital equalization [C]. IEEE InternationalSolid-State Circuits Conference-Digest of Technical Papers,2009,53(9):82-83.
[88] Wang H., Wang X., Hurst P. J., Lewis S. H. Nested digital background calibration of a12-bit pipelined ADC without an input SHA [J]. IEEE J. Solid-State Circuits,2009,44(10):2780-2789.
[89] Gauwenberghs G., and Temes G.C. Adaptive Digital Correction of Analog Errors inMASH ADC’s-Part Ⅰ: Off-Line and Blind On-Line Calibration [J]. IEEE Trans. Circuitsand System Ⅱ: Analog and Digital Signal Processing,2000,47(7):621-628.
[90] Dogancay K. Blind compensation of nonlinear distortion for bandlimited signals [J].IEEE Trans. Circuits and System Ⅰ: Regular Paper,2005,52(9):1872-1882.
[91] Fetterman H.S, CMOS pipelined ADC employing dither to improve linearity [C].Proceedings of IEEE Custom Integrated Circuits Conference,1999:109-112.
[92] Siragusa E.J., Galton I. Gain error correction technique for pipelined analog-to-digitalconverters [J]. IEEE Electronics Letters,2000,36(7):617-618.
[93] Erup L., Gardner Floyd M., Harris R. A. Gildenblat G. Interpolation in digital modems.Ⅱ.Implementation and Performance [J]. IEEE Trans. Commun.,1992,41(6):998-1008.
[94] Siragusa E.J., Galton I. A digitally enhanced1.8-V15-bit40-MSample/s CMOSpipelined ADC [J]. IEEE J. Solid-State Circuits,2004,39(12):2126-2138.
[95] Yang W.H., Kelly D., Mehr I., et al. A3-V,20MS/s340-mW14-b75-Msample/s CMOSADC with85-dB SFDR at nyquist input [J]. IEEE J.Solid-state circuits,2001,36(12):1931-1936.
[96] McNeill J., Coln M.C.W., Larivee B.J.“Split-ADC” architecture for deterministic digitalbackground calibration of a16-bit1-MS/s ADC [J]. IEEE J.Solid-state circuits,2005,40(12):2437-2445.
[97] Shu Y.S., Song B.S. A15b-Linear,20MS/s,1.5b/Stage Pipelined ADC DigitallyCalibrated with Signal-Dependent Dithering [C]. Symposium on VLSI Circuits, Digest ofTechnical Papers,2006:218-219.
[98] Shi Longxing, Zhao Wei, and Wu Jianghui, et al. Digital background calibrationtechniques for pipelined ADC on comparator Dithering [J]. IEEE Trans. Circuits andSystem Ⅱ: EXPRESS BRIEFS,2012,59(4):239-243.
[99] Liu H.C., Lee Z.M. and Wu J.T.. A15-bit40-MS/s CMOS Pipelined analog-to-digitalconverter with digital background calibration [J]. IEEE J.Solid-state circuits,2005,40(5):1047-1056.
[2] Murmann B., ADC performance Survey,1997-2013[OL], http://www.stanford.edu/~murmann/adcsurvey.html.
[3] Cheng W., Ali W., Choi M. J., et al. A3b40GS/s ADC-DAC in0.12m SiGe [C]. In50thInternational Solid-State Circuits Conference (ISSCC), Digest of Technical Papers. Vol.12004:262-263.
[4] Schvan P., Bach J., Falt C., et al. A24GS/s6b ADC in90nm CMOS [C]. In54thInternatonal Solid-State Circuits Conference (ISSCC), Digest of Technical Papers.Vol.1,2008:544-545.
[5] Marcu C., Chowdhury D., Thakkar C., et al. A90nm CMOS low-power60-GHztransceiver with intergrated baseband ciruitry [C]. IEEE J. Solid-State Circuits,2009，44(12)：3434-3447.
[6]李福乐.适宜于系统集成的高速高精度模数转换电路设计技术研究[D].博士学位论文，清华大学电子工程系,2003.
[7] Li J., Zeng X.Y., Xie L., et al. A1.8-V22-mW10-bit30-MS/s Pipelined CMOS ADC forLow-Power Subsamping Applications [J]. IEEE J. Solid-State Circuits,2008,43(2):321-329.
[8] Luo L., Lin K.L., Cheng L., et al. A Digitally calibrated14-bit Linear100-MS/s PipelinedADC with Wideband Sampling Frontend [C]. IEEE Proc. ESSCIRC,2009:472-475.
[9] Guo D.D., Li F.L., Zhang C., et al. A13-bit8MSample/s pipeline A/D Converter [J].Journal of Semiconductors,2009,30(2):025006-5.
[10] Yin X.M., Wei Q., Xu L., et al. A Low Power12-b40-MS/s Pipeline ADC [J]. Journal ofSemiconductors,2010,31(3):035006-1.
[11] Long S.L., Shi L.X., Wu J.H., et al. A1.8V10bit100Msps Pipelined Analog to DigitalConveter [J]. Journal of Semiconductors,2008,29(5):923-929.
[12] Moore G. Progress in digital integrated electronics [C]. IEDM Tech Dig.1975:11-13.
[13]拉扎维.模拟CMOS集成电路设计[M].西安交通大学出版社,2004.
[14] Murmann B., Boser B. E. Digitally Assisted Pipeline ADCs Theory and implementation[M]. Springer,2004.
[15] Karanicolas A.N.，Lee H.S., Bacrania K. A15b1-MS/s Digitally Self-CalibratedPipelined ADC [J]. IEEE J. Solid-State Circuits，1993，28(12)：1207-1215.
[16] Xing H., et al, High-resolution ADC linearity testing using a fully digital-compatibleBIST strategy [J].IEEE Trans. Instrumentation and Measurement,2009,58(8):2697-2705.
[17] Chang D.Y., Li J., Moon U. Radix-based digital lcalibration techniques for multi-stagerecycling pipelined ADCs [J]. IEEE Trans. Circuits and Systems Ⅰ,2004,51(11):2133-2140.
[18] Ming J., Lewis S.H. An8-bit80-Msample/s pipelined analog-to-digital converter withbackground calibration [J]. IEEE J. Solid-State Circuits，2001，36(10)：1489-1497.
[19] Li J.P., Moon U.K. Background calibration techniques for multistage pipelined ADCswith digital redundancy [J]. IEEE Trans. Circuits and Systems Ⅱ: Analog and DigitalSignal Processing,2003,50(9):531-538.
[20] Liu H.C., Lee Z.M., Wu H.T. A15b20MS/s CMOS pipelined ADC with digitalbackground calibraion [C]. In54thInternatonal Solid--State Circuits Conference (ISSCC),Digest of Technical Papers. Vol.1,2004:454-455.
[21] Widrow B.，Samuel D. S.自适应信号处理[M].北京：机械工业出版社，2008.
[22] Chiu Y., Tsang C.Y.W. Least Mean square Adaptive Digtial Background Calibration ofPipelined Analog-to-ditial Converters [J]. IEEE Transactions on Circuits and Systems Ⅰ:Regular Papers,2004,51(1):38-46.
[23] Shu Y.S., Song B.S. A15-bit linear20-MS/s pipelined ADC digitally Calibrated withsignal-dependent dithering [J]. IEEE J. Solid-State Circuits，2008，43(2):342-350.
[24] Li W., Li F., Guo D., et al. An Undersampling14-bit Cyclic ADC with over100dBSFDR [J]. Chinese Journal of Semiconductors,2010,31:025008-6.
[25] Zhou L., Luo L., Ye F. et al. A12-bit100-Ms/s pipelined ADC with digital backgroundcalibration [J]. Journal of Semiconductors,2009,30:115007-5.
[26] Ahmed I. Pipelined ADC Design and Enhancement Techniques [M]. Springer,2010.
[27] Figueirdo P.M., Vital J.C. Offset Reduction Technique in high-speed analog-to-ditialconverter: Analysis, Deisign and Tradeoffs [M]. Springer2009:1-62.
[28] Yoshii Y., Asano K., Nakamura M., et al. An8b100MS/s Flash ADC [J]. IEEE J.Solid-State Circuits，1984，19(6)：842-846.
[29] McCall K.J.，Demler M.J., Plante M.W. A6-bit125MHz CMOS A/D Converter [C].Proceedings of the IEEE1992Custom Integrated Circuits Conference,1992：16.8.1-16.8.4.
[30] Dalton D., Spalding G., Reyhani H., et al. A200-MSPS6-bit Flash ADC in0.6-mCMOS [J]. IEEE Trans. Circuits Syst.,1998,45(11):1433-1444.
[31] Luri M., Declan D. A500-Msample/s6-bit nyquist-rate ADC for disk-drive read channelapplications [J]. IEEE J. Solid-State Circuits，1999,34(7)：912-920.
[32] Choi M., Asad A. A6-b1.3-Gsps AD Converter in0.35m CMOS [J]. IEEE J.Solid-State Circuits，2001,36(12)：1847-1858.
[33] Anwar A.F.M., Khondker A.N. A70-MS/s110-mW CMOS Folding and InterpolatingA/D converter [J]. IEEE J. Solid-State Circuits,1995,30(12):1302-1308.
[34] Lewis S.H., Gray P.R. A Pipelined5-Msample/s9-bit Analog-to-Digtial Converter [J].IEEE J. Solid-State Circuits,1987,22(6):954-961.
[35] Lewis S.H. Optimizing the stage resolution in pipelined, multistage analog-to-digtialconverters for video-rate applications [J]. IEEE Trans. Circuits and Systems Ⅱ: Analogand digital signal processing,1992,39(8):516-523.
[36] Dyer K., Fu D., Lewis S., Hurst P. Analog backgroud calibration of a10b40Msample/sparallel pipelined ADC [C]. IEEE International Solid-State Circuits conference,1998,ED-34(2):142-143.
[37] Song W.C., Choi H.W., Kwak S.U., Song B.S. A10-b20-Msample/s Low-Power CMOSADC [J]. IEEE J. Solid-State Circuits,1987,22(6):514-521.
[38] Nakamura K., Hotta M., Carley L.R., Allsot D.J. Allstot. An85mw,10b,40-Msample/sCMOS parallel-pipelined ADC [J]. IEEE J. Solid-State Circuits,1995,30(4):173-183.
[39] Mukheerjee S., Srinivasan C., Pawar V., et al. A2.5V10-bit SAR ADC [C]. InternationalConference on VLSI Design. Hyderabad, India: IEEE Computer Society,1997,46(1):525-526.
[40] Sheiing Y.N., Bahar J., Zhang P., et al. A low-voltage CMOS5-bit600MHz30mW SARADC for UWB wireless receivers [C]. Midwest Symp. Circuits Syst., Cincinnati, Ohio:IEEE Circuits and Systems Society,2005:187-190.
[41] Li C.C., Ikeda H., Inoue T., et al. A physical poly-Silicon thin film transistors model forcircuit simulations [C]. IEEE Custom Intergrated Circuits Conference. San Jose: IEEESolid-State Circuits Society,2005:403-06.
[42] Boser B.E., Wooley B.A. The design of sigma-delta modulation analog-to-digitalconverters [J]. IEEE J. Solid-State Circuits,1989,23(6):1298-1308.
[43] Signore B.P., Kerth D.A., Sooch N.S., et al. A monolithic20-bit delta-sigma A/Dconverter [J]. IEEE J. Solid-State Circuits,1990,25(6):1311-1316.
[44] Boser B.E., Wooley B.A. A50-MHz multibit sigma-delta modulator for12-b2-MHz A/Dconverter [J]. IEEE J. Solid-State Circuits,1991,26(12):1746-1755.
[45] Shu T., Song B., Bacrania K. A13-b10-Msample/s ADC digitally calibrated withoversampling delta-sigma converter [J]. IEEE J. Solid-State Circuits,1995,30(4):443-452.
[46] Rabii S., Wooley B.A. A1.8-V digital-audio sigma-delta modulator in0.8m CMOS [J].IEEE J. Solid-State Circuits,1997,32(6):783-796.
[47] Dessouky M., Kaiser A. Very low-voltage digital audio-modulator with88-dBdynamic range [J]. IEEE Journal of Solid-State Circuits,2001,36(3):349-355.
[48] Lewis S. H., Fetterman H.S., Gross G.F., et al. A10-b20-Msample/s analog-to-digitalconverters [J]. IEEE J. Solid-State Circuits,1992,27(3):351-358.
[49] Hadidi K. Temes G. C. Error analysis in pipeline A/D converters and its applications [J].IEEE Trans. Circuits and Systems Ⅱ: Analog and digital signal processing,1992,39(8):506-515.
[50] Ynag W., Kelly D., Mehr L., et al. A3-V340-mW14-b75-Msample/s CMOS ADC with85-Db SFDR at Nyquist input [J]. IEEE J. Solid-State Circuits,2001,36(12):1931-1936.
[51] Thomas B. Cho. Low-power Low-Voltage Analog-to-Digital Conversion TechniquesUsing pipelined Architectures [D]. California: University of California, Berkeley,1995.
[52] Cline D., Gray P.R. A power optimized13-b5-Msample/s pipelined analog-to-digitalconverter in1.2-mm CMOS [J]. IEEE J. Solid-State Circuits,1996,28(12):294-303.
[53] Waltari M. Circuit Techniques for Low-voltage and High-Speed A/D Converter [D].Helsinki University of Technology,2002.
[54] Kester W. The Data Conversion Handbook [M]. Elsevier/Newnes,2005.
[55] Shinagawa M., Akazawa Y., Wakimoto T. Jitter Analysis of High-Speed SamplingSystems [J]. IEEE J. Solid-State Circuits,1990,25(1):220-224.
[56] Karanicolas A.N., Lee H.S., Bacrania K. A15b1-MS/s Digitally self-Calibrated PipelineADC [J]. IEEE J. Solid-State Circuits,1993,28(12):1207-1215.
[57] Ginetti B., Jespers P.G.A., Vandemeulebroecke A. A CMOS13-b Cyclic RSD A/DConverter [J]. IEEE J. Solid-State Circuits,1992,27(7):957-966.
[58] Arias J., Boccuzzi V., Quintanilla L., et al. Low-Power Pipeline ADC for Wireless LANs[J]. IEEE J.Solid-state circuits,2004,39(8):1338-1340.
[59] Kwok P.T.F., luong H.C. Power optimized for pipelined analog-to-digital converters [J].IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing,1999,46(5):549-553.
[60]李建.低功耗低电压CMOS流水线模数转换器的结构研究与实现[D].博士学位论文，复旦大学，2008.
[61] Chiu Y., Gray P.R., and Nikolic B. A1.8V14b,10MS/s Pipelined ADC in0.18μmCMOS with99dB SFDR [C]. IEEE International Solid-State Circuits Conference, Digestof Technical Papers,2004:458-539.
[62] Cho T.B, Gray P.R. A10b,20Msample/s,35mW Pipeline A/D Converter [J]. IEEE J.Solid-State Circuits,1995,30(3):166-172.
[63] Waltari M., Halonen K.A. I.1-V,9-Bit Pipelined Switched-Opamp ADC [J]. IEEE J.Solid-State Circuits,2001,36(1):129-134.
[64] Min B.M., Kim P., Bowman F.W., et al. A69-mW10-bit80-MSample/s Pipelined CMOSADC [J]. IEEE J. Solid-State Circuits,2003,38(12):2031-2039.
[65] Fiorenza, J.K., Sepke T., Holloway P., et al. Comparator-Based Switched-CapacitorCircuits for Scaled CMOS technologies [J]. IEEE J. Solid-State Circuits,2006,41(12):2658-26681.
[66] Waltari M., Halonen K. A220-MSample/s CMOS Sample-and-Hold Circuit UsingDouble-Sampling [J]. Analog Integrated Circuits and Signal Processing,1999,18(1):21-31.
[67] Abo A.M., Gray P.R. A1.5-V,10-bit,14-MS/s CMOS pipeline analog-to-digitalconverter [J]. Symposium on VLSI Circuits,1998,33(2):166-169.
[68] Abo A.M., Gray P.R. A1.5-V,10-bit,14.3-MS/s CMOS pipeline analog-to-digitalconverter [J]. IEEE J. Solid-State Circuits,1999,34(5):599-606.
[69] Liu M. Demystifying Switched-Capacitor Circuits [M]. Elsevier,2006.
[70] Abo M. Design for Reliability of Low-voltage, Switched-capacitor Circuits [D]. DoctoralThesis, University of California, Berkeley,1999.
[71] Mehr I., Singer L. A55-mW,10-bit,40-Msample/s Nyquist-Rate CMOS ADC [J]. IEEEJ. Solid-State Circuits,2000,35(3):318-325.
[72] Li J., Zeng X.Y., Xie L., et al. A1.8-V22-mW10-bit30-MS/s Pipelined CMOS ADC forLow-Power Subsampling Application [J]. IEEE J. Solid-State Circuits,2008,43(2):321-329.
[73] Lee B.G., Min B.M., Manganaro G. et al. A14-b100-MS/s Pipelined ADC with aMerged SHA and First MDAC [J]. IEEE J. Solid-State Circuits,2008,43(12):2613-2619.
[74] Min B.M., Kim P., Bowman F.W., Boisvert D.M., Aude A. J. A69-mW10-bit80-MSample/s pipelined CMOS ADC [J]. IEEE J. Solid-State Circuits,2003,38(12):2031-2039.
[75] Nagaraj K., Fetterman H., Anidjar J., et al. A250-mW,8-b,52-MsampleParallel-pipelinedA/D Converters with Reduced Number of Amplifiers [J]. IEEE J.Solid-State Circuits,1994,32(3):312-320.
[76] Lee S.H., Song B.S. Digital-Domain Calibration of Multistep Analog-to-DigitalConverters [J]. IEEE J. Solid-State Circuits,1992,27(12):8084-8089.
[77] Chuang S. Y., Scylly T.L. A Digitally Self-Calibrating14-bit10-MHz CMOS PipelinedA/D Converters [D]. IEEE J. Solid-State Circuits,2002,37(6):674-683.
[78] Verma A., Razavi B. A10-Bit500-MS/s55mW CMOS ADC [J]. IEEE J. Solid-StateCircuits,2009,44(11):3039-3050.
[79] Grace C.R., Hurst P.J., Lewis S.H. A12-bit80-MSample Pipelined ADC withBootstrapped Digital Calibration [J]. IEEE J.Solid-State Circuits,2005,40(5):1038-1046.
[80] Daito M., Matsui H., Ueda M., lizuka K. A14-bit20-MS/s pipelined ADC with DigitalDistortion Calibration [A]. IEEE J. Solid-State Circuits,2006,41(11):2417-2423.
[81] Grace C.R., Hurst P.J., Lewis S.H. A12-bit80MS/s pipelined ADC with bootstrappeddigital calibration [J]. IEEE J. Solid-State Circuits,2005,40(5):1038-1046.
[82] Erdogan O.E., Hurst P. J., Lewis S.H. A12-b digital background calibrated algorithmicADC with90-dB THD [J]. IEEE J. Solid-State Circuits,1999,34(12):1812-1820.
[83] Ingino J.M., Wooley B.A. A continuously calibrated12-b,10-MS/s,3.3-V A/D converter[J]. IEEE J. Solid-State Circuits,1998,33(12):1920-1931.
[84] Moon U.K., Song B.S. Background digital calibtation techniques for pipelined ADCs [J].IEEE Trans. Circuits and Systems Ⅱ,1997,44(2):102-109.
[85] Chiu Y., Tsang C.W., Nikolic B., et al. Least-mean-square adaptive ditgital back-groundcalibration of pipelined A/D converters [J]. IEEE Trans. Circutis and System Ⅰ: RegularPapers,2004,51(1):38-46.
[86] Tsang C. Background ADC calibration in digital domain [C]. IEEE Custom IntegratedCircuits Conference,2008:301-304.
[87] Liu W., Chang Y.C., Hsien S.K., et al. A600MS/s30mW0.13μm CMOS ADC arrayachieving over60dB SFDR with adaptive digital equalization [C]. IEEE InternationalSolid-State Circuits Conference-Digest of Technical Papers,2009,53(9):82-83.
[88] Wang H., Wang X., Hurst P. J., Lewis S. H. Nested digital background calibration of a12-bit pipelined ADC without an input SHA [J]. IEEE J. Solid-State Circuits,2009,44(10):2780-2789.
[89] Gauwenberghs G., and Temes G.C. Adaptive Digital Correction of Analog Errors inMASH ADC’s-Part Ⅰ: Off-Line and Blind On-Line Calibration [J]. IEEE Trans. Circuitsand System Ⅱ: Analog and Digital Signal Processing,2000,47(7):621-628.
[90] Dogancay K. Blind compensation of nonlinear distortion for bandlimited signals [J].IEEE Trans. Circuits and System Ⅰ: Regular Paper,2005,52(9):1872-1882.
[91] Fetterman H.S, CMOS pipelined ADC employing dither to improve linearity [C].Proceedings of IEEE Custom Integrated Circuits Conference,1999:109-112.
[92] Siragusa E.J., Galton I. Gain error correction technique for pipelined analog-to-digitalconverters [J]. IEEE Electronics Letters,2000,36(7):617-618.
[93] Erup L., Gardner Floyd M., Harris R. A. Gildenblat G. Interpolation in digital modems.Ⅱ.Implementation and Performance [J]. IEEE Trans. Commun.,1992,41(6):998-1008.
[94] Siragusa E.J., Galton I. A digitally enhanced1.8-V15-bit40-MSample/s CMOSpipelined ADC [J]. IEEE J. Solid-State Circuits,2004,39(12):2126-2138.
[95] Yang W.H., Kelly D., Mehr I., et al. A3-V,20MS/s340-mW14-b75-Msample/s CMOSADC with85-dB SFDR at nyquist input [J]. IEEE J.Solid-state circuits,2001,36(12):1931-1936.
[96] McNeill J., Coln M.C.W., Larivee B.J.“Split-ADC” architecture for deterministic digitalbackground calibration of a16-bit1-MS/s ADC [J]. IEEE J.Solid-state circuits,2005,40(12):2437-2445.
[97] Shu Y.S., Song B.S. A15b-Linear,20MS/s,1.5b/Stage Pipelined ADC DigitallyCalibrated with Signal-Dependent Dithering [C]. Symposium on VLSI Circuits, Digest ofTechnical Papers,2006:218-219.
[98] Shi Longxing, Zhao Wei, and Wu Jianghui, et al. Digital background calibrationtechniques for pipelined ADC on comparator Dithering [J]. IEEE Trans. Circuits andSystem Ⅱ: EXPRESS BRIEFS,2012,59(4):239-243.
[99] Liu H.C., Lee Z.M. and Wu J.T.. A15-bit40-MS/s CMOS Pipelined analog-to-digitalconverter with digital background calibration [J]. IEEE J.Solid-state circuits,2005,40(5):1047-1056.