基于FPGA的SpaceWire路由器设计与分析
摘要
随着航天技术的进步,星载设备的种类和数量大幅度增加。需要一种高速、可扩展、低功耗、低成本的总线技术来满足数据处理要求。SpaceWire总线是一种串行、高速、点对点、双向全双工的数据通信协议,具有高性能、低费用、容错网络结构等优点,是专门面向航天应用的新一代高速总线标准,为包括欧洲航天局,美国国家航空航天局在内的众多航天机构和航天工业所采用,具有广阔的应用前景。但国内对其的研究还处于起步阶段。本文对SpaceWire路由器设计进行了相关研究。
本文从SpaceWire协议出发,详细分析了SpaceWire路由器的工作原理和特点。提出了一种支持4个SpaceWire接口和1个用于级联的外部扩展接口的SpaceWire路由器的设计方案。该设计将SpaceWire路由器划分为接口电路和路由开关两大模块。基于FPGA平台通过使用硬件描述语言,按照自顶向下的设计原则进行设计。接口电路部分增加了数据缓冲的接收FIFO模块和发送FIFO模块。同时使用EDAC技术和容错状态机的结构来提高抗辐照能力。路由开关设计了一种基于虚拟通道缓冲和虫孔路由算法的低时延、无阻塞、5端口的SpaceWire交换开关。
With the advances in space technology, and significant increase in the types and quantities of satellite equipment, A new bus technology with high speed, scalable, low power consumption, and low cost is needed to meet requirements of data handling. SpaceWire is a new data communication protocol, which is serial, high speed, point to point, bi directional, full duplex, with the advantages of high performance, low cost, fault tolerant network structure and so on. As a new generation of high speed bus standard special for aerospace applications, it is widely used by space agencies and industry like ESA, NASA and so on. But in China, the study on this subject is still in the early stage. The work of this paper is SpaceWire router design related research.
This paper embarks from the SpaceWire protocol, introduces and discusses SpaceWire router principle and characteristic in detail. A SpaceWire router design is also proposed in this paper which supports four SpaceWire interfaces and an external interface for cascading. This design includes two modules: SpaceWire router interface circuit and routing switch. This router is designed by hardware description language, and realized on FPGA platforms, according to the top down design principle of design. Receive FIFO and send FIFO used to cach data are added in the interface circuit. At the same time EDAC technology and fault tolerant state machine structure are used to improve radiation resistance. And we design a low delay, non blocking, 5 ports Crossbar Switch which based on virtual channel buffer and Wormhole Routing.
本文从SpaceWire协议出发,详细分析了SpaceWire路由器的工作原理和特点。提出了一种支持4个SpaceWire接口和1个用于级联的外部扩展接口的SpaceWire路由器的设计方案。该设计将SpaceWire路由器划分为接口电路和路由开关两大模块。基于FPGA平台通过使用硬件描述语言,按照自顶向下的设计原则进行设计。接口电路部分增加了数据缓冲的接收FIFO模块和发送FIFO模块。同时使用EDAC技术和容错状态机的结构来提高抗辐照能力。路由开关设计了一种基于虚拟通道缓冲和虫孔路由算法的低时延、无阻塞、5端口的SpaceWire交换开关。
With the advances in space technology, and significant increase in the types and quantities of satellite equipment, A new bus technology with high speed, scalable, low power consumption, and low cost is needed to meet requirements of data handling. SpaceWire is a new data communication protocol, which is serial, high speed, point to point, bi directional, full duplex, with the advantages of high performance, low cost, fault tolerant network structure and so on. As a new generation of high speed bus standard special for aerospace applications, it is widely used by space agencies and industry like ESA, NASA and so on. But in China, the study on this subject is still in the early stage. The work of this paper is SpaceWire router design related research.
This paper embarks from the SpaceWire protocol, introduces and discusses SpaceWire router principle and characteristic in detail. A SpaceWire router design is also proposed in this paper which supports four SpaceWire interfaces and an external interface for cascading. This design includes two modules: SpaceWire router interface circuit and routing switch. This router is designed by hardware description language, and realized on FPGA platforms, according to the top down design principle of design. Receive FIFO and send FIFO used to cach data are added in the interface circuit. At the same time EDAC technology and fault tolerant state machine structure are used to improve radiation resistance. And we design a low delay, non blocking, 5 ports Crossbar Switch which based on virtual channel buffer and Wormhole Routing.
引文
[1] HTTP:// spacewire.esa.int.
[2] IEEE Computer Society.“IEEE Standard for Heterogeneous Interconnect (HIC) (Low Cost,Low Latency Scalable Serial Interconnect for Parallel System Construction)”. IEEE Standard 1355 1995. IEEE.1996.
[3] IEEE Computer Society.“IEEE Standard for Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)”. IEEE Standard 1596.3 1996, IEEE. 1996.
[4] S. M. Parkes,ect.“SpaceWire: Links, Nodes, Routers and Networks”. European Cooperation for Space Standardization Standard ,No.ECSS E50 12A. 2003. Issue 1,
[5]凤雷,鲁文帅,付平。“SpaceWire网络层协议分析与应用研究”。测试技术报。2010年,第24卷,第6期。页码:524 526。
[7] Jan M Rabaey, Anantha Chandarksan, Borivoje Nikolic。“数字集成电路电路,系统与设计”。第二版。北京:电子工业出版社,2004。
[8]杨之廉,申明。“超大规模集成电路设计方法学导论”。第二版。北京:清华大学出版社,1999。
[9]夏宇闻。“Verilog数字系统设计教程”。北京:北京航天航空大学出版社,2008。
[10]王长河。“单粒子效应对卫星空间运行可靠性影响”。半导体情报。第35卷,第1期。1998年2月。页码:1 8。
[11] Jiri Gaisler.“A Portable and Fault Tolerant Microprocessor Based on the SPARC V8 Architecture”. Proceedings of the International Conference on Dependable Systems and Networks (DSN’02). 2002.pp:409 415.
[12] Kenneth A. LaBel, Michele M. Gates.“Single Event Effect Mitigation from a system perspective”. IEEE Transactions On Nuclear Science. 1996. Vol 43, No 2. pp:654 660.
[13] Huang Ye,Cheng Xiulan.“Design and analysis of SEU/SET hardened D flip flop”.Semiconductor Technology.2009. Vol 34, No1. pp: 69 72.
[14] Wesolowski.C.“Error correction with Hamming codes”. Embedded Systems Programming. 2004. pp:28 37.
[15]王爱珍。“扩展汉明码的编解码器设计及其FPGA实现”。现代电子技术。2008年。第19期。页码:187 188。
[16] M. Y. Hsiao.“A Class of Optimal Minimum Odd weight column SEC DED Codes”.IBM J. Res.Develop. July 1970.Vol 14, No 4. pp:395 401.
[17] Shailsh, Niranjan ,James F, ect.“A Comparison of Fault Tolerant State Machine Architectures for Space Borne Electronics”. IEEE TRSACTIQNS ON RELIABILITY. 1996.Vol. 45, No1.pp:109 113.
[18] Jason Zheng, Sunant Katanyoutanant, Martin Le.“Safe and Efficient One Hot State Machine”.Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference,Washington D. C. 2005. pp:1 45.
[19]陈苏鹏,于立新,飞海东等。“基于FPGA的SpaceWire接口容错设计和评估”。机电产品开发与创新。2008。第21卷,第3期。页码:142 144。
[20]王诚,薛小刚,钟信潮。“FPGA/CPLD设计工具—Xilinx ISE使用详解”。北京:人民邮电出版社,2005年。页码:172 192。
[21] Chris McClements, Steve Parkes, Gerald Kempf.“SpW 10X SpaceWire Router User Manual”. 2008. Issue 3.4.pp:22 24.
[22] Saponaras,Fanuccil,Tonatellim,etc.“Radiation Tolerant SpaceWire Router for Satellite On.Board Networking”, IEEE Aero space and Electronic systems Magazine,2007,Vol 22,No 5. pp:3 12.
[23] Parkes S, McClements C, Kempf G, etc.“SpaceWire Router”.International SpaceWire Seminar. 2003, pp:125 132.
[24] Bauer G, Boyer V, ect.“Effects of adaptive wormhole routing in event builder networks”.IEEE Transactions on Nuclear Science.2008.pp:182 189.
[25] Wang Liwei, Cao Yang, Li Xiao hu, etc.“A buffer allocation algorithm for wormhole routing networks on chip”. Journal of Beijing University of Posts and Telecommunications.2008 .Vol. 31, No4. pp:29 32.
[26] Shahrabi, A.“Performance comparison of routing algorithms in wormhole switched networks”. Parallel Computing.2006. Vol. 32, No11.pp:870 885.
[27] Mao ChUunjing.Guan Yong.Jungwirth D.“Research and Design Of On Board SpaceWire Route”.2009 ETP International Conference on Future Computer and Cormnunication. 2009.pp:234 237.
[28]李潇,龚龙庆,田卫等。“一种基于流水线的SpaceWire路山器研究”。现代电子技术。2009。第3期。页码:90 92。
[29]陈国良,吴俊敏,章锋等。“并行计算机体系结构”。北京:高等教育出版社,2002。页码:201 208。
[30]王晓袁,杨银堂。“一种用于片上网络的交换开关结构”。微计算机信息。2008年。第24卷,第9 2期。页码:71 73。
[31] Masoumeh Karimi,Zhuo Sun,Deng Pan,ect.“Packet mode asynchronous scheduling algorithm for partially buffered crossbar switches”. Proceedings of the 28th IEEE conference on Global telecommunications.2009.pp:5144 5149.
[32] Deng Pan, Kia Makki, Niki Pissinou.“Fair queueing based packet scheduling for buffered crossbar switches”. Proceedings of the 28th IEEE conference on Global telecommunications. 2009. pp:1592 1597.
[33]李兴政,杨海钢。“FPGA芯片中的交叉开关设计”。微电子学。2007年。第37卷,第4期。页码:606 609。
[34] Jan, Gene Eu,Leu, Shao Wei, Liou WR,etc.“FPGA implementation of a multicasting crossbar switch”. Proceedings of the International Conference on Microelectronics.2009. pp:177 180.
[35] W. Dally, B. Towles.Route Packets.“Not Wires: On Chip Interconnection Networks”.Proceedings of the 38th Design Automation Conference. 2001. pp:684 689.
[36] Kangmin Lee,Se Joong Lee, Hoi Jun Yo.“A Distributed Crossbar Switch Scheduler For On Chip Networks”. IEEE 21x13C USTOM Integrated Circuits Conference .pp: 671 674.
[37] Karol M, Hluchyj M, Morgan S.“Input versus output queuing on a space division packet Switch”. IEEE Transactions on Communications. 2001. Vol35,No12 .pp:1347 1356.
[38] Mello, Aline Tedesco Leonel,ect. "Virtual channels in networks on chip: Implementation and evaluation on hermes NoC". SBCCI 2005, 18th Symposium on Integrated Circuits and Systems Design. 2005. pp.178一183.
[39] N. Kavaldjiev ,G. J. M. Smit , P. G. Jansen.“A Virtual Channel Router for On chip Network”. IEEE International SOC Conference. California. 2004.pp:289 293.
[40]万书芹,于宗光,黄召军等。“高速SpaceWire路由器的设计研究“。中国电子科学研究院学报。2010年。第5卷,第1期。页码:24 28。
[41]毛春静,关永。“星载SpaceWire路由器的研究与设计”。电子与信息学报。2010年。第32卷,第8期。页码:1904 1909。
[2] IEEE Computer Society.“IEEE Standard for Heterogeneous Interconnect (HIC) (Low Cost,Low Latency Scalable Serial Interconnect for Parallel System Construction)”. IEEE Standard 1355 1995. IEEE.1996.
[3] IEEE Computer Society.“IEEE Standard for Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)”. IEEE Standard 1596.3 1996, IEEE. 1996.
[4] S. M. Parkes,ect.“SpaceWire: Links, Nodes, Routers and Networks”. European Cooperation for Space Standardization Standard ,No.ECSS E50 12A. 2003. Issue 1,
[5]凤雷,鲁文帅,付平。“SpaceWire网络层协议分析与应用研究”。测试技术报。2010年,第24卷,第6期。页码:524 526。
[7] Jan M Rabaey, Anantha Chandarksan, Borivoje Nikolic。“数字集成电路电路,系统与设计”。第二版。北京:电子工业出版社,2004。
[8]杨之廉,申明。“超大规模集成电路设计方法学导论”。第二版。北京:清华大学出版社,1999。
[9]夏宇闻。“Verilog数字系统设计教程”。北京:北京航天航空大学出版社,2008。
[10]王长河。“单粒子效应对卫星空间运行可靠性影响”。半导体情报。第35卷,第1期。1998年2月。页码:1 8。
[11] Jiri Gaisler.“A Portable and Fault Tolerant Microprocessor Based on the SPARC V8 Architecture”. Proceedings of the International Conference on Dependable Systems and Networks (DSN’02). 2002.pp:409 415.
[12] Kenneth A. LaBel, Michele M. Gates.“Single Event Effect Mitigation from a system perspective”. IEEE Transactions On Nuclear Science. 1996. Vol 43, No 2. pp:654 660.
[13] Huang Ye,Cheng Xiulan.“Design and analysis of SEU/SET hardened D flip flop”.Semiconductor Technology.2009. Vol 34, No1. pp: 69 72.
[14] Wesolowski.C.“Error correction with Hamming codes”. Embedded Systems Programming. 2004. pp:28 37.
[15]王爱珍。“扩展汉明码的编解码器设计及其FPGA实现”。现代电子技术。2008年。第19期。页码:187 188。
[16] M. Y. Hsiao.“A Class of Optimal Minimum Odd weight column SEC DED Codes”.IBM J. Res.Develop. July 1970.Vol 14, No 4. pp:395 401.
[17] Shailsh, Niranjan ,James F, ect.“A Comparison of Fault Tolerant State Machine Architectures for Space Borne Electronics”. IEEE TRSACTIQNS ON RELIABILITY. 1996.Vol. 45, No1.pp:109 113.
[18] Jason Zheng, Sunant Katanyoutanant, Martin Le.“Safe and Efficient One Hot State Machine”.Mil/Aero Applications of Programmable Logic Devices (MAPLD) International Conference,Washington D. C. 2005. pp:1 45.
[19]陈苏鹏,于立新,飞海东等。“基于FPGA的SpaceWire接口容错设计和评估”。机电产品开发与创新。2008。第21卷,第3期。页码:142 144。
[20]王诚,薛小刚,钟信潮。“FPGA/CPLD设计工具—Xilinx ISE使用详解”。北京:人民邮电出版社,2005年。页码:172 192。
[21] Chris McClements, Steve Parkes, Gerald Kempf.“SpW 10X SpaceWire Router User Manual”. 2008. Issue 3.4.pp:22 24.
[22] Saponaras,Fanuccil,Tonatellim,etc.“Radiation Tolerant SpaceWire Router for Satellite On.Board Networking”, IEEE Aero space and Electronic systems Magazine,2007,Vol 22,No 5. pp:3 12.
[23] Parkes S, McClements C, Kempf G, etc.“SpaceWire Router”.International SpaceWire Seminar. 2003, pp:125 132.
[24] Bauer G, Boyer V, ect.“Effects of adaptive wormhole routing in event builder networks”.IEEE Transactions on Nuclear Science.2008.pp:182 189.
[25] Wang Liwei, Cao Yang, Li Xiao hu, etc.“A buffer allocation algorithm for wormhole routing networks on chip”. Journal of Beijing University of Posts and Telecommunications.2008 .Vol. 31, No4. pp:29 32.
[26] Shahrabi, A.“Performance comparison of routing algorithms in wormhole switched networks”. Parallel Computing.2006. Vol. 32, No11.pp:870 885.
[27] Mao ChUunjing.Guan Yong.Jungwirth D.“Research and Design Of On Board SpaceWire Route”.2009 ETP International Conference on Future Computer and Cormnunication. 2009.pp:234 237.
[28]李潇,龚龙庆,田卫等。“一种基于流水线的SpaceWire路山器研究”。现代电子技术。2009。第3期。页码:90 92。
[29]陈国良,吴俊敏,章锋等。“并行计算机体系结构”。北京:高等教育出版社,2002。页码:201 208。
[30]王晓袁,杨银堂。“一种用于片上网络的交换开关结构”。微计算机信息。2008年。第24卷,第9 2期。页码:71 73。
[31] Masoumeh Karimi,Zhuo Sun,Deng Pan,ect.“Packet mode asynchronous scheduling algorithm for partially buffered crossbar switches”. Proceedings of the 28th IEEE conference on Global telecommunications.2009.pp:5144 5149.
[32] Deng Pan, Kia Makki, Niki Pissinou.“Fair queueing based packet scheduling for buffered crossbar switches”. Proceedings of the 28th IEEE conference on Global telecommunications. 2009. pp:1592 1597.
[33]李兴政,杨海钢。“FPGA芯片中的交叉开关设计”。微电子学。2007年。第37卷,第4期。页码:606 609。
[34] Jan, Gene Eu,Leu, Shao Wei, Liou WR,etc.“FPGA implementation of a multicasting crossbar switch”. Proceedings of the International Conference on Microelectronics.2009. pp:177 180.
[35] W. Dally, B. Towles.Route Packets.“Not Wires: On Chip Interconnection Networks”.Proceedings of the 38th Design Automation Conference. 2001. pp:684 689.
[36] Kangmin Lee,Se Joong Lee, Hoi Jun Yo.“A Distributed Crossbar Switch Scheduler For On Chip Networks”. IEEE 21x13C USTOM Integrated Circuits Conference .pp: 671 674.
[37] Karol M, Hluchyj M, Morgan S.“Input versus output queuing on a space division packet Switch”. IEEE Transactions on Communications. 2001. Vol35,No12 .pp:1347 1356.
[38] Mello, Aline Tedesco Leonel,ect. "Virtual channels in networks on chip: Implementation and evaluation on hermes NoC". SBCCI 2005, 18th Symposium on Integrated Circuits and Systems Design. 2005. pp.178一183.
[39] N. Kavaldjiev ,G. J. M. Smit , P. G. Jansen.“A Virtual Channel Router for On chip Network”. IEEE International SOC Conference. California. 2004.pp:289 293.
[40]万书芹,于宗光,黄召军等。“高速SpaceWire路由器的设计研究“。中国电子科学研究院学报。2010年。第5卷,第1期。页码:24 28。
[41]毛春静,关永。“星载SpaceWire路由器的研究与设计”。电子与信息学报。2010年。第32卷,第8期。页码:1904 1909。