多通道LVDS接收器数据恢复和Skew消除
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摘要
低压差分信号(LVDS)作为高速、串行视频接口技术,在平板显示中有着广泛的应用,但随着平板显示器向着大尺寸、高分辨率的方向不断发展,图形控制器到显示器的数据量急剧增大,高速LVDS接收器作为LVDS接口的重要模块,其性能往往直接决定着整个接口的性能,因此成为目前高速接口芯片市场的研究热点。
本文主要研究多通道LVDS接收器在每个通道速率为1.2Gbps,并且每个通道有抖动和偏移的情况下,如何对多通道数据进行同步采样。抖动和偏移的影响,会使得眼图的有效采样区间变小。为了能使得多通道数据眼图的采样区间变大,本文在分析传统的时钟数据恢复方法的基础上,针对多通道LVDS数据的特点,提出首先用基于DLL的时钟数据恢复电路对每个通道采样,然后通过Deskew电路消除通道间的偏移,从而实现多通道的同步采样。这样的方法可以有效减小抖动对多通道Deskew的影响。在基于DLL的时钟数据恢复电路中,本文在高速、低电源电压的情况下,设计了一种高精度的电荷泵电路,该电荷泵可以有效的减小电荷共享等非线性效应,也可抑制沟长调制效应对精度的影响。另外,在传统的Hogge时钟数据鉴相器的基础上,本文对D触发器延时造成的误差进行补偿,提高了鉴相精度,并减小了鉴相器对高性能触发器的要求。Deskew电路采用多通道数据和参考时钟进行skew判断,并调整数据延时的方法来减小多通道数据间的偏移。
本文采用TSMC 90nm Mix-Signal Salicide工艺来对CDR和Deskew电路进行设计和仿真,整体仿真结果显示,本文的CDR和Deskew电路在1.2Gbps速率和±250ps抖动和偏移情况下,可以有效的增大多通道数据眼图的采样区间到600ps,并能正确的对多通道数据进行同步采样。
As a high speed, serial video interface, Low Voltage Differential Signal (LVDS) is widely used in flat panel display. However, the demands of large size, high-resolution FPD make the amount of data between graphics controller and display increases rapidly. To some extent, the high speed performance of LVDS receiver determines the whole performance of interface. Therefore, LVDS receiver becomes research focus in high speed interface market.
In this paper, the research interest is how to sample the multi-channel LVDS data Synchronous under the affect of jitter and skew when the speed of signle channel is 1.2Gbps. Jitter and skew will reduce the sampling margin of eye-diagram. With the consideration of multi-channel data, to enlarge the sampling margin, DLL based clock and data recovery (CDR) circuit will sample each data channel respectively, and then Deskew circuit will reduce the skew between each data channel. With this method, the jitter will barely affect the working of multi-channel Deskew circuit. In the design of DLL based CDR, an accuracy charge pump circuit is designed for high speed and low supply voltage application, the charge pump circuit can suppress charge sharing and other nonlinear affect as well as the channel length modulation effect. The delay compensation of DFF in conventional Hogge phase detector in this paper can improve the accuracy of phase detector as well as reduce the requirement of high-performance flip-flop. In Deskew circuit; the delay of each channel data is adjusted to align with the reference clock respectively to reduce the skew between channels.
TSMC 90nm Mix-Signal Salicide (1.2V/3.3V) is employed to verify the performance of CDR and Deskew circuit. The whole simulation results illustrate that the multi-channel data can be aligned with each other and be sampled synchronous when the speed is 1.2Gbps, the eye-dirgram of multi-channel data can be enlarge to 600ps, meanwhile, the toleration of skew and jitter can be up to±250ps.
本文主要研究多通道LVDS接收器在每个通道速率为1.2Gbps,并且每个通道有抖动和偏移的情况下,如何对多通道数据进行同步采样。抖动和偏移的影响,会使得眼图的有效采样区间变小。为了能使得多通道数据眼图的采样区间变大,本文在分析传统的时钟数据恢复方法的基础上,针对多通道LVDS数据的特点,提出首先用基于DLL的时钟数据恢复电路对每个通道采样,然后通过Deskew电路消除通道间的偏移,从而实现多通道的同步采样。这样的方法可以有效减小抖动对多通道Deskew的影响。在基于DLL的时钟数据恢复电路中,本文在高速、低电源电压的情况下,设计了一种高精度的电荷泵电路,该电荷泵可以有效的减小电荷共享等非线性效应,也可抑制沟长调制效应对精度的影响。另外,在传统的Hogge时钟数据鉴相器的基础上,本文对D触发器延时造成的误差进行补偿,提高了鉴相精度,并减小了鉴相器对高性能触发器的要求。Deskew电路采用多通道数据和参考时钟进行skew判断,并调整数据延时的方法来减小多通道数据间的偏移。
本文采用TSMC 90nm Mix-Signal Salicide工艺来对CDR和Deskew电路进行设计和仿真,整体仿真结果显示,本文的CDR和Deskew电路在1.2Gbps速率和±250ps抖动和偏移情况下,可以有效的增大多通道数据眼图的采样区间到600ps,并能正确的对多通道数据进行同步采样。
As a high speed, serial video interface, Low Voltage Differential Signal (LVDS) is widely used in flat panel display. However, the demands of large size, high-resolution FPD make the amount of data between graphics controller and display increases rapidly. To some extent, the high speed performance of LVDS receiver determines the whole performance of interface. Therefore, LVDS receiver becomes research focus in high speed interface market.
In this paper, the research interest is how to sample the multi-channel LVDS data Synchronous under the affect of jitter and skew when the speed of signle channel is 1.2Gbps. Jitter and skew will reduce the sampling margin of eye-diagram. With the consideration of multi-channel data, to enlarge the sampling margin, DLL based clock and data recovery (CDR) circuit will sample each data channel respectively, and then Deskew circuit will reduce the skew between each data channel. With this method, the jitter will barely affect the working of multi-channel Deskew circuit. In the design of DLL based CDR, an accuracy charge pump circuit is designed for high speed and low supply voltage application, the charge pump circuit can suppress charge sharing and other nonlinear affect as well as the channel length modulation effect. The delay compensation of DFF in conventional Hogge phase detector in this paper can improve the accuracy of phase detector as well as reduce the requirement of high-performance flip-flop. In Deskew circuit; the delay of each channel data is adjusted to align with the reference clock respectively to reduce the skew between channels.
TSMC 90nm Mix-Signal Salicide (1.2V/3.3V) is employed to verify the performance of CDR and Deskew circuit. The whole simulation results illustrate that the multi-channel data can be aligned with each other and be sampled synchronous when the speed is 1.2Gbps, the eye-dirgram of multi-channel data can be enlarge to 600ps, meanwhile, the toleration of skew and jitter can be up to±250ps.
引文
[1]赵忠文,曾峦,熊伟. LVDS技术分析和应用设计.装备指挥技术学院学报, 2001, 12(6): 89~93
[2]陈向真.平板显示技术现状和发展趋势.光电子技术, 2008, 28(1):1~6
[3]刘祥远,陈书明. LVDS高速I/O接口单元的设计研究.计算机工程与科学, 2001, 23(4): 52~56
[4] IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard. IEEE Standard. 1596.3, 1996.
[5] MAXIM High-Frequency/Fiber Communications Group. Converting between RMS and Peak-to-Peak Jitter at a Specified BER. Maxim, HFAN-4.0.2. 2003, 4
[6] Ming-Dou Ker, Chien-Hua Wu. Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 2006, 5155~5158
[7] Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, et al. Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006, 53(11): 1318~1322
[8] Koh Chin Yeong, Ma Fan Yung, Koh Tee Peng, et al. 1.2Gbps LVDS interface. IEEE International Symposium on Integrated Circuits, Darling Harbour. Sydney, Australia, 2007, 382~385
[9] Choi Youngdon, Jeong Deog-Kyoon, Kim Wonchan, et al. An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm. IEEE Asian Solid-State Circuits Conference, Hangzhou, China, 2006, 383~386
[10]尹勇生,胡永华,高明伦.过采样技术CDR分析及应用.应用科学学报,2006, 24(3): 240~244
[11] Sang-Hyun Lee, Moon-Sang Hwang, et al. A 5Gbps 0.25-um CMOS Jitter Tolerant Variable Interval Over-sampling Clock and Data Recovery Circuit. IEEEJournal of Solid State Circuit, 2002, 37(12): 1822~1830
[12] Brownlee, M., Hanumolu, P.K., Un-Ku Moon. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. IEEE Custom Integrated Circuits Conference, California, San Jose, US, 2007, 353~356
[13] Yan Ierssel M., Sheikholeslami, A. et al. A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE Journal of Solid-state Circuits, 2007, 42(10):1824~1834
[14]胡建贇,李强,闵昊.一种适用于射频电子标签的时钟数据恢复电路.固体电子学研究与进展, 2006, 26(4): 516~521
[15]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003. 310-320
[16] Jaeha Kim, Horowitz M.A., et al. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003, 50(11): 860~869
[17]王朝钦,萧俊扬.低电压差动信号的时脉数据回复装置及其方法(P).中国,发明专利, 200410062881.6. 2006, 3~9
[18] Adrian Maxim. A 0.16-2.55GHz CMOS Active Clock Deskewing PLL Using Analog Phase Interpolation. IEEE Journal of Solid State Circuit, 2005, 40(1): 110~131
[19]张涛.锁相环频率合成器建模、设计与实现: [博士学位毕业论文].武汉:华中科技大学图书馆,2006
[20] M.-J. Edward Lee, William J. Dally. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques. IEEE Journal of Solid State Circuit, 2003, 38(4): 614~621
[21] Hsiang-Hui Chang, Jyh-Woei Lin. A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle. IEEE Journal of Solid State Circuit, 2002, 37(8): 1021~1027
[22] Maneatis John G.. Low-Jitter Process-Independent DLL and PLL based on self-biased Techniques. IEEE Journal of Solid-state Circuits, 1996, 31(11):1723~1732
[23] S. Sidiropoulos, D. Liu, J. Kim et al. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers. IEEE Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, Hawaii, US , 2000, 124–127
[24] Behzad Razavi. Challenges in the Design of High-Speed Clock and Data Recovery Circuits. IEEE Communications Magazine, 2002, 40(8): 94~101
[25] Kyung-Soo Ha, Lee-Sup Kim. Charge-Pump reducing current mismatch in DLLs and PLLs. IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 2006, 2221~2224
[26] Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee et al. A 66–333-MHz 12-mW Register-Controlled DLL with a Single Delay Line and Adaptive-Duty-Cycle Clock Dividers for Production DDR SDRAMs. IEEE Journal of Solid-state Circuits, 2004, 31(11): 2087~2092
[27] Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, et al. A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM. IEEE Journal of Solid-State Circuits, 2002, 37(6): 726~734
[28] G. Chien, P. Gray. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications. IEEE International Solid-State Circuits Conference, San Francisco, US, 2000, 202–203
[29] Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang. A Low-Power Small-Area±7.28-ps-Jitter 1-GHz DLL-Based Clock Generator. IEEE Journal of Solid State Circuit, 2002, 37(11): 1414~1420
[30] [35]Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, et al. A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications. IEEE Journal of Solid State Circuit, 2000, 35(10): 1430~1436
[31] L. DeVito. A Versatile Clock Recovery Architecture and Monolithic Implementation. In: Monolithic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed., New York: IEEE Press, 1996. 405~420
[32] Hong Yu, Yasuaki Inoue, Yan Han. A New High-Speed Low-Voltage Charge Pump for PLL Applications. International Conference On ASIC, Shanghai, China, 2005, 1: 387~390
[33] Young-Shig Choi, Dae-Hyun Han. Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop. IEEE Journal of Solid State Circuit, 2006, 53(10): 1022~1025
[34] R. Ahola, K. Halonen. A 1.76-GHz 22.6-mWΔ∑Fractional-N Frequency Synthesizer. IEEE Journal of Solid State Circuit, 2003, 38(1): 138~140
[35] Jae-Shin Lee, Min-Sun Keel, Shin-I1 Lim, et al. Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Lettles, 2000, 36(20): 1907~1908
[36] W. Rhee, B.-S. Song, A. Ali. A 1.1 GHz CMOS fractional-N frequency synthesizer a 3-bit third-order modulator. IEEE Journal of Solid State Circuit, 2000, 35(10): 1453~1460Δ∑
[37] I. A. Young, J. K. Greason, K. L. Wong. A PLL clock generator with 5 to 110 MHz of lock range microprocessors. IEEE Journal of Solid State Circuit, 1992, 27(11): 1599~1607
[38] Chi-Nan Chuang, Shen-Iuan Liu. A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump. IEEE Journal of Solid State Circuit, 2007, 54(11): 939~943
[39] Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, et al. A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop. IEEE Journal of Solid State Circuit, 2006, 41(5): 1051~1061
[40] Torralba. G., Angelov. V., Gonzalez. V., et al. A VLSI for deskewing and fault tolerance in LVDS links. IEEE Transactions on Nuclear Science, 2006, 53(3): 801~809
[41] Yuan, J., Svensson, C.. High-speed CMOS circuit technique. IEEE Journal of Solid-State Circuits, 1989, 24(1): 62~70
[42] Mentor Graphics. ADVance MS User’s Manual, Software Version 4.4_1 Release AMS 2006.1
[2]陈向真.平板显示技术现状和发展趋势.光电子技术, 2008, 28(1):1~6
[3]刘祥远,陈书明. LVDS高速I/O接口单元的设计研究.计算机工程与科学, 2001, 23(4): 52~56
[4] IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard. IEEE Standard. 1596.3, 1996.
[5] MAXIM High-Frequency/Fiber Communications Group. Converting between RMS and Peak-to-Peak Jitter at a Specified BER. Maxim, HFAN-4.0.2. 2003, 4
[6] Ming-Dou Ker, Chien-Hua Wu. Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 2006, 5155~5158
[7] Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, et al. Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006, 53(11): 1318~1322
[8] Koh Chin Yeong, Ma Fan Yung, Koh Tee Peng, et al. 1.2Gbps LVDS interface. IEEE International Symposium on Integrated Circuits, Darling Harbour. Sydney, Australia, 2007, 382~385
[9] Choi Youngdon, Jeong Deog-Kyoon, Kim Wonchan, et al. An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm. IEEE Asian Solid-State Circuits Conference, Hangzhou, China, 2006, 383~386
[10]尹勇生,胡永华,高明伦.过采样技术CDR分析及应用.应用科学学报,2006, 24(3): 240~244
[11] Sang-Hyun Lee, Moon-Sang Hwang, et al. A 5Gbps 0.25-um CMOS Jitter Tolerant Variable Interval Over-sampling Clock and Data Recovery Circuit. IEEEJournal of Solid State Circuit, 2002, 37(12): 1822~1830
[12] Brownlee, M., Hanumolu, P.K., Un-Ku Moon. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. IEEE Custom Integrated Circuits Conference, California, San Jose, US, 2007, 353~356
[13] Yan Ierssel M., Sheikholeslami, A. et al. A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE Journal of Solid-state Circuits, 2007, 42(10):1824~1834
[14]胡建贇,李强,闵昊.一种适用于射频电子标签的时钟数据恢复电路.固体电子学研究与进展, 2006, 26(4): 516~521
[15]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003. 310-320
[16] Jaeha Kim, Horowitz M.A., et al. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003, 50(11): 860~869
[17]王朝钦,萧俊扬.低电压差动信号的时脉数据回复装置及其方法(P).中国,发明专利, 200410062881.6. 2006, 3~9
[18] Adrian Maxim. A 0.16-2.55GHz CMOS Active Clock Deskewing PLL Using Analog Phase Interpolation. IEEE Journal of Solid State Circuit, 2005, 40(1): 110~131
[19]张涛.锁相环频率合成器建模、设计与实现: [博士学位毕业论文].武汉:华中科技大学图书馆,2006
[20] M.-J. Edward Lee, William J. Dally. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques. IEEE Journal of Solid State Circuit, 2003, 38(4): 614~621
[21] Hsiang-Hui Chang, Jyh-Woei Lin. A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle. IEEE Journal of Solid State Circuit, 2002, 37(8): 1021~1027
[22] Maneatis John G.. Low-Jitter Process-Independent DLL and PLL based on self-biased Techniques. IEEE Journal of Solid-state Circuits, 1996, 31(11):1723~1732
[23] S. Sidiropoulos, D. Liu, J. Kim et al. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers. IEEE Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, Hawaii, US , 2000, 124–127
[24] Behzad Razavi. Challenges in the Design of High-Speed Clock and Data Recovery Circuits. IEEE Communications Magazine, 2002, 40(8): 94~101
[25] Kyung-Soo Ha, Lee-Sup Kim. Charge-Pump reducing current mismatch in DLLs and PLLs. IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, 2006, 2221~2224
[26] Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee et al. A 66–333-MHz 12-mW Register-Controlled DLL with a Single Delay Line and Adaptive-Duty-Cycle Clock Dividers for Production DDR SDRAMs. IEEE Journal of Solid-state Circuits, 2004, 31(11): 2087~2092
[27] Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, et al. A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM. IEEE Journal of Solid-State Circuits, 2002, 37(6): 726~734
[28] G. Chien, P. Gray. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications. IEEE International Solid-State Circuits Conference, San Francisco, US, 2000, 202–203
[29] Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang. A Low-Power Small-Area±7.28-ps-Jitter 1-GHz DLL-Based Clock Generator. IEEE Journal of Solid State Circuit, 2002, 37(11): 1414~1420
[30] [35]Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, et al. A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications. IEEE Journal of Solid State Circuit, 2000, 35(10): 1430~1436
[31] L. DeVito. A Versatile Clock Recovery Architecture and Monolithic Implementation. In: Monolithic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed., New York: IEEE Press, 1996. 405~420
[32] Hong Yu, Yasuaki Inoue, Yan Han. A New High-Speed Low-Voltage Charge Pump for PLL Applications. International Conference On ASIC, Shanghai, China, 2005, 1: 387~390
[33] Young-Shig Choi, Dae-Hyun Han. Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop. IEEE Journal of Solid State Circuit, 2006, 53(10): 1022~1025
[34] R. Ahola, K. Halonen. A 1.76-GHz 22.6-mWΔ∑Fractional-N Frequency Synthesizer. IEEE Journal of Solid State Circuit, 2003, 38(1): 138~140
[35] Jae-Shin Lee, Min-Sun Keel, Shin-I1 Lim, et al. Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Lettles, 2000, 36(20): 1907~1908
[36] W. Rhee, B.-S. Song, A. Ali. A 1.1 GHz CMOS fractional-N frequency synthesizer a 3-bit third-order modulator. IEEE Journal of Solid State Circuit, 2000, 35(10): 1453~1460Δ∑
[37] I. A. Young, J. K. Greason, K. L. Wong. A PLL clock generator with 5 to 110 MHz of lock range microprocessors. IEEE Journal of Solid State Circuit, 1992, 27(11): 1599~1607
[38] Chi-Nan Chuang, Shen-Iuan Liu. A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump. IEEE Journal of Solid State Circuit, 2007, 54(11): 939~943
[39] Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, et al. A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop. IEEE Journal of Solid State Circuit, 2006, 41(5): 1051~1061
[40] Torralba. G., Angelov. V., Gonzalez. V., et al. A VLSI for deskewing and fault tolerance in LVDS links. IEEE Transactions on Nuclear Science, 2006, 53(3): 801~809
[41] Yuan, J., Svensson, C.. High-speed CMOS circuit technique. IEEE Journal of Solid-State Circuits, 1989, 24(1): 62~70
[42] Mentor Graphics. ADVance MS User’s Manual, Software Version 4.4_1 Release AMS 2006.1