CMOS ΣΔ分数频率综合器的若干关键技术研究
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摘要
频率综合器是射频前端电路中的关键模块之一,在设计中面临着小面积,高性能和低功耗的挑战。本论文研究针对无线射频应用的ΣΔ分数频率综合器,完成了以下工作:
从系统级角度分析了大量的设计问题,这有助于正确地选择合适的电路模块和环路参数,合理地分配各个模块的非线性指标。
提出一套包括模块电路非线性的锁相环电压域verilogA/verilog模型。这种方式使得设计者能控制和评估各个噪声源的影响,预测闭环的锁相环分数频率综合器的静态和动态特性,有助于提高仿真速度和在设计的早期阶段深入了解电路特性并优化。仿真和测量结果验证了这些行为级模型的有效性和灵活性。
设计和实现了一个基于个人移动通信系统(PHS)应用的自适应,自调谐的分数锁相环频率综合器。压控振荡器采用数模混合技术实现,从而在一个小的增益下获得一个大的频率调谐范围。自适应环路用来实现环路的自动调整,有助于提高频谱纯度和减少建立时间。吞脉冲分频器仅需要一个可编程计数器。测试结果表明:频率调谐范围>600MHz、相位噪声<-119dBc/Hz@1MHz、杂散<-70dBc、建立时间<100μs、功耗<34mW、面积<1.7mm×1.5mm。
提出一种基于IEEE 802.11a/b/g WLAN应用的自调谐锁相环结构,它能单独实现锁相环的功能,也能作为锁相环频率锁定的辅助电路。为了使环路迅速收敛到正确的控制字,它引入了自适应控制。测试结果表明它有一个2.5GHz-4.1GHz频率调谐范围、建立时间<500μs、相位噪声<-115dBc/Hz@1MHz、杂散<-90dBc、功耗<36mW、面积<1.7mm×1.5mm。
提出一种基于电荷平均原理的杂散减少技术,它使杂散信号降低30dBc,适合应用在高性能锁相环设计中。
提出一种可变延时缓存器的相位校正结构,这种结构是数字可控的,对温度,工艺变化不敏感。仿真和测试结果表明该方案能正确地工作,可变延时缓存器在L波段消耗的电流小于10mA,正交相移范围<10o。
Frequency synthesizer is a key block in the wireless transceiver. There exist challenges like small layout area, high performance and low power dissipation in the design. In this dissertation, the design and analysis ofΣΔfractional-n frequency synthesizer for RF applications is conducted, and the principal contributions of this dissertation are described in the following.
The dissertation presents a number of system issues and design considerations/tradeoffs that are involved in the design of such a frequency synthesizer from the system point of view. These considerations help to properly select loop parameters and key building blocks, and specify noise and nonlinearity of components used in aΣΔfractional-n frequency synthesizer.
A set of behavioral voltage-domain verilogA/verilog models allowing a systematic design ofΣΔfractional-n frequency synthesizer is presented in the dissertation. The approach allows the designer to predict the dynamic or stable characteristic of the closed loop by including nonlinear effects of building blocks in the models. So it helps to a speed-up over transistor simulation and a grasp of the fundamentals at the early stage of the design and optimization design at the system level. Simulation and measured results show that behavioral modeling is effective and flexible.
A self-adaptive, self-tuning fractional-n PLL based frequency synthesizer is proposed in the dissertation. A combined tuning technique of digital tuning and analog tuning is introduced to effectively enlarge the frequency tuning range in a low gain of VCO. The self-adaptive loop is used to realize automatic adjustment of the loop bandwidth, which can reduce the settling time and improve the spectral purity. Only a programmable counter is needed for the swallow pulse divider. The proposed architecture is implemented in a Personal Handy-phone System (PHS) transceiver, and measured results show that the synthesizer has a <-119dBc/Hz@1MHz phase noise, a <-70dBc spur and a <100μs settling time. The chip consumes 34mW at 1.8V and occupies 1.5mm×1.7mm.
TheΣΔfractional-n frequency synthesizer with adaptive digital tuning techniques is deeply discussed in the dissertation. The proposed one can be independently used as a PLL, and it can also be used as a frequency-lock aid for the conventional PLL. An adaptive control is for fast convergence to a proper control word. The proposed architecture is implemented in an IEEE 802.11a/b/g WLAN transceiver, and measured results show that the synthesizer has a <-115dBc/Hz@1MHz phase noise, a <-90dBc spur, a 2.5GHz-4.1GHz frequency tuning range and a <500μs settling time. The chip consumes 36mW at 1.8V and occupies 1.5mm×1.7mm.
A spur reduction technique based on charge-averaging principle is presented in the dissertation. The proposed technique can reduce the spurious tones over 30dBc, so it can easily be implemented in the high performance PLL.
A new phase self-calibrated scheme for variable delay buffer (VDB) is proposed in the dissertation. The digitally controlled phase calibration removes the disadvantage of conventional analog calibration circuit whose performance is sensitive to process and temperature variations and aging. It is shown that the proposed scheme works properly, and the VDBs consume a 10mA current at L frequency band, and have a <10o quadrature phase shift range.
从系统级角度分析了大量的设计问题,这有助于正确地选择合适的电路模块和环路参数,合理地分配各个模块的非线性指标。
提出一套包括模块电路非线性的锁相环电压域verilogA/verilog模型。这种方式使得设计者能控制和评估各个噪声源的影响,预测闭环的锁相环分数频率综合器的静态和动态特性,有助于提高仿真速度和在设计的早期阶段深入了解电路特性并优化。仿真和测量结果验证了这些行为级模型的有效性和灵活性。
设计和实现了一个基于个人移动通信系统(PHS)应用的自适应,自调谐的分数锁相环频率综合器。压控振荡器采用数模混合技术实现,从而在一个小的增益下获得一个大的频率调谐范围。自适应环路用来实现环路的自动调整,有助于提高频谱纯度和减少建立时间。吞脉冲分频器仅需要一个可编程计数器。测试结果表明:频率调谐范围>600MHz、相位噪声<-119dBc/Hz@1MHz、杂散<-70dBc、建立时间<100μs、功耗<34mW、面积<1.7mm×1.5mm。
提出一种基于IEEE 802.11a/b/g WLAN应用的自调谐锁相环结构,它能单独实现锁相环的功能,也能作为锁相环频率锁定的辅助电路。为了使环路迅速收敛到正确的控制字,它引入了自适应控制。测试结果表明它有一个2.5GHz-4.1GHz频率调谐范围、建立时间<500μs、相位噪声<-115dBc/Hz@1MHz、杂散<-90dBc、功耗<36mW、面积<1.7mm×1.5mm。
提出一种基于电荷平均原理的杂散减少技术,它使杂散信号降低30dBc,适合应用在高性能锁相环设计中。
提出一种可变延时缓存器的相位校正结构,这种结构是数字可控的,对温度,工艺变化不敏感。仿真和测试结果表明该方案能正确地工作,可变延时缓存器在L波段消耗的电流小于10mA,正交相移范围<10o。
Frequency synthesizer is a key block in the wireless transceiver. There exist challenges like small layout area, high performance and low power dissipation in the design. In this dissertation, the design and analysis ofΣΔfractional-n frequency synthesizer for RF applications is conducted, and the principal contributions of this dissertation are described in the following.
The dissertation presents a number of system issues and design considerations/tradeoffs that are involved in the design of such a frequency synthesizer from the system point of view. These considerations help to properly select loop parameters and key building blocks, and specify noise and nonlinearity of components used in aΣΔfractional-n frequency synthesizer.
A set of behavioral voltage-domain verilogA/verilog models allowing a systematic design ofΣΔfractional-n frequency synthesizer is presented in the dissertation. The approach allows the designer to predict the dynamic or stable characteristic of the closed loop by including nonlinear effects of building blocks in the models. So it helps to a speed-up over transistor simulation and a grasp of the fundamentals at the early stage of the design and optimization design at the system level. Simulation and measured results show that behavioral modeling is effective and flexible.
A self-adaptive, self-tuning fractional-n PLL based frequency synthesizer is proposed in the dissertation. A combined tuning technique of digital tuning and analog tuning is introduced to effectively enlarge the frequency tuning range in a low gain of VCO. The self-adaptive loop is used to realize automatic adjustment of the loop bandwidth, which can reduce the settling time and improve the spectral purity. Only a programmable counter is needed for the swallow pulse divider. The proposed architecture is implemented in a Personal Handy-phone System (PHS) transceiver, and measured results show that the synthesizer has a <-119dBc/Hz@1MHz phase noise, a <-70dBc spur and a <100μs settling time. The chip consumes 34mW at 1.8V and occupies 1.5mm×1.7mm.
TheΣΔfractional-n frequency synthesizer with adaptive digital tuning techniques is deeply discussed in the dissertation. The proposed one can be independently used as a PLL, and it can also be used as a frequency-lock aid for the conventional PLL. An adaptive control is for fast convergence to a proper control word. The proposed architecture is implemented in an IEEE 802.11a/b/g WLAN transceiver, and measured results show that the synthesizer has a <-115dBc/Hz@1MHz phase noise, a <-90dBc spur, a 2.5GHz-4.1GHz frequency tuning range and a <500μs settling time. The chip consumes 36mW at 1.8V and occupies 1.5mm×1.7mm.
A spur reduction technique based on charge-averaging principle is presented in the dissertation. The proposed technique can reduce the spurious tones over 30dBc, so it can easily be implemented in the high performance PLL.
A new phase self-calibrated scheme for variable delay buffer (VDB) is proposed in the dissertation. The digitally controlled phase calibration removes the disadvantage of conventional analog calibration circuit whose performance is sensitive to process and temperature variations and aging. It is shown that the proposed scheme works properly, and the VDBs consume a 10mA current at L frequency band, and have a <10o quadrature phase shift range.
引文
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