基于应用的片上网络设计与性能评估
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摘要
随着微电子技术的不断发展,片上系统(System-on-Chip,SoC)成为超大规模集成电路设计的主流,单个芯片上将集成成百甚至上千个IP核。SoC中所包含IP核数目的不断增多,使得以总线结构为通信基础的SoC技术面临着在性能、功耗、面积、系统可靠性和可扩展性等方面的巨大挑战。
片上网络(Network-on-Chip,NoC)被公认为是片上系统IP核互连通信的有效解决方案,是SoC发展的必然趋势。论文在对片上网络关键技术研究的基础之上,着重研究面向特定应用的片上网络设计。课题完成了片上网络高层次建模,从体系结构出发,研究片上网络设计参数的改变以及不同应用任务对片上网络性能的影响,主要包括网络负载、数据通信模式、拓扑结构、交换方式四个方面。为了更精确的研究片上网络性能,进一步设计了4x4 mesh拓扑结构的RTL级片上网络与仿真验证平台,其网络接口服从开放式核协议(Open Core Protocol,OCP),提高网络的通用性。使用synopsys EDA工具完成对所设计片上网络的仿真验证和逻辑综合,通过延时、面积和功耗三项指标来分析网络性能。
最后以H.264解码为实际应用,对应用进行并行性划分,映射到已设计的片上网络中,并对其功能进行验证,完成设计仿真与综合,着重给出芯片面积和功耗两项性能指标的分析结果。
With the development of micro-electronics technology, SoC become mainly technique in very large scale integrated circuit, hunderds of IP cores will be intergrating in a single chip . With the growing number of IP cores in a single chip, bus based SoC are undergoing huge challenges in performance , power, area, system reliability and scalability, restrict the development of SoC.
Network-on-Chip (NoC) is an emerging IC architecture that cope with the increasing complexity and communication requirements of current SoC. Based on the research of key technology in NoC design, In this paper we constructed a NoC high-level model with network simulator OPNET. Simulations and analyses were performed with different combinations of the network parameters including network topologies, router algorithms, switch techniques, traffic patterns, communication loads. Furthermore we constructed Network-on-Chip and verification platform at RTL level with the interface based Open Core Protocol. Then simulations and synthesis were performed with synopsys EDA tools. Detailed comparative analysis of the network performance and cost in terms of latency, area and power dissipation are presented.
We design Application-Specific Network-on-Chip based on H.264/AVC decode Application. First the tasks were divided into some sub-modules. Each sub-module was event-driven and communicated through network. At last, we implemented IP core design of H.264/AVC decoder based NoC. Simulations and synthesis were performed. Analyses were made in term of chip area and power dissipation..
片上网络(Network-on-Chip,NoC)被公认为是片上系统IP核互连通信的有效解决方案,是SoC发展的必然趋势。论文在对片上网络关键技术研究的基础之上,着重研究面向特定应用的片上网络设计。课题完成了片上网络高层次建模,从体系结构出发,研究片上网络设计参数的改变以及不同应用任务对片上网络性能的影响,主要包括网络负载、数据通信模式、拓扑结构、交换方式四个方面。为了更精确的研究片上网络性能,进一步设计了4x4 mesh拓扑结构的RTL级片上网络与仿真验证平台,其网络接口服从开放式核协议(Open Core Protocol,OCP),提高网络的通用性。使用synopsys EDA工具完成对所设计片上网络的仿真验证和逻辑综合,通过延时、面积和功耗三项指标来分析网络性能。
最后以H.264解码为实际应用,对应用进行并行性划分,映射到已设计的片上网络中,并对其功能进行验证,完成设计仿真与综合,着重给出芯片面积和功耗两项性能指标的分析结果。
With the development of micro-electronics technology, SoC become mainly technique in very large scale integrated circuit, hunderds of IP cores will be intergrating in a single chip . With the growing number of IP cores in a single chip, bus based SoC are undergoing huge challenges in performance , power, area, system reliability and scalability, restrict the development of SoC.
Network-on-Chip (NoC) is an emerging IC architecture that cope with the increasing complexity and communication requirements of current SoC. Based on the research of key technology in NoC design, In this paper we constructed a NoC high-level model with network simulator OPNET. Simulations and analyses were performed with different combinations of the network parameters including network topologies, router algorithms, switch techniques, traffic patterns, communication loads. Furthermore we constructed Network-on-Chip and verification platform at RTL level with the interface based Open Core Protocol. Then simulations and synthesis were performed with synopsys EDA tools. Detailed comparative analysis of the network performance and cost in terms of latency, area and power dissipation are presented.
We design Application-Specific Network-on-Chip based on H.264/AVC decode Application. First the tasks were divided into some sub-modules. Each sub-module was event-driven and communicated through network. At last, we implemented IP core design of H.264/AVC decoder based NoC. Simulations and synthesis were performed. Analyses were made in term of chip area and power dissipation..
引文
[1] ITRS 2007 Edition, International Technology Roadmap for Semiconductors 2007 Edition.http://www.itrs.net/Links/2007ITRS/ExecSum2007.pdf.
[2] Tully J, Gordon R, Bruederle S, et al. Hype Cycle for semiconductors, Gartner research’s Technical Report Report. 2004. ID Number: 00120909.
[3] P.Guerrier, A. Greiner. A generic architecture for on-chip packet-switched interconnections[A], in: DATE [C]. Paris, France: March 2000 pp250-256.
[4] M. Sgroi, M.Sheets, A. Mihal, K, et al. A Sangiovanni-Vincentelli. Addressing the system-on-chip interconnect woes through communication-based design [A]. 38th Design Automation Conference. June 2001 pp667-672.
[5] Benini L, Giovanni D M. Networks on chips: a new SoC paradigm [J]. IEEE Computer.2002,35(1):70-78.
[6] Kumar S H, Jantsch A, Soininen J-P, et al. A network on chip architecture and design methodology. Proceedings of IEEE Computer Society Annual Symposium on VLSI. 2002.
[7] Rijpkema, E., Goossens, K., and Radulescu, A.:‘Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip’. Proc. Design Automation and Test in Europe, March .2003, pp. 350-355.
[8]杜高明,NoC-MPSoC多核体系结构及原型芯片实现技术研究,[D]博士学位论文,合肥工业大学,2007年5月。
[9]周干民,NoC基础研究,[D]合肥工业大学博士论文,2005。
[10]荆元利,樊晓桠,张盛兵等。基于片上网络的系统芯片测试研究[J]。微电子学与计算机,2004,21(6):154-159。
[11]荆元利,樊晓桠,网络互连多线程处理器[J]。计算机工程与应用,2005,41(33):51-53,78。
[12]周文彪,张岩,毛志刚.片上网络的低功耗自适应数据保护[J].计算机工程,2006,32(22):28-30.
[13]黎黎,片上网络路由算法研究及路由节点的FPGA设计,电子科技大学, 2007.
[14] Po-Tang Huang, Wei Hwang. 2-Level FIFO Architecture Design for Switch Fabrics in Network-on-Chip. ISCAS 2006, pp: 4863-4866.
[15] Portero, A.; Pla, R.; Rodriguez, A.; Carrabina, J. NoC Design of a Video Encoder in aMultiprocessor System on Chip Solution.
[16] A.Jantsch, H.Tenhunen , Network on chip, Kluwer Academic Publishers, 2003.
[17] P.P.Pande, C.Grecu, A.Ivanov, and R.Saleh,“Design of a Switch for Network on chip Applications,”Proc. Int’l symp. Circuits and Systems (ISCAS), vol.5,pp.217-220,May 2003.
[18] J.Duato, S. Yalamanchili, and L.Ni, Interconnection Networks—An Engineering Approach. Morgan Kaufmann,2002.
[19] David S. Bormann and Peter Y.K.Cheung.:‘Asynchronous wrapper for heterogeneous systems’.In Proc. International Conf. Computer Design (ICCD), October 1997.
[20]Culler D.E, singh J.P, Gupta A.“Parallel Computer Archiecture: A Hardware/Software Approach, Second Edition”, Morgan Kaufmann, August 1998.
[21]王文博,张金文. OPNET Modeler与网络仿真[M].第1版,北京:人民邮电出版社,2003.
[22] Benini, L.“Application Specific NoC Design”Design, Automation and Test in Europe, 2006.. Proceedings. Volume:1 March 2006 Page(s): 1-5
[23] Kees Goossens, John Dielissen, Om Prakash Gangwal.“A Design Flow for Application-Specific Networks on Chip with Guaranteed Performace to Accelerate SoC Design and Verification”Design, Automation and Test in Europe, 2005. Proceedings 7-11 March 2005 Page(s): 1182- 1187
[24]吴飞,片上网络适配单元的设计与实现,南京航空航天大学,2007.
[25]朱晓静,胡伟武,马可等.“Xmesh:一个mesh-like片上网络拓扑结构”.软件学报, Volume:9, 2007
[26]王宏伟,陆俊林,佟冬等.“层次化片上网络结构的簇生成算法”.电子学报, vol:5 2007.
[27] ARM,‘AMBA AXI Protocol Specification,’2003
[28] ALTERA,‘Avalon Interface Specification,’2004
[29] OCP- IP, OCP Specification Release2.1, http://www.ocpip.org
[30] ITRS 2001. http://public.itrs.net/Files/2001ITRS/Home.htm
[31] S.J. Krolikoski et al.:‘Methodology and Technology for Virtual Component Driven Hardware/Software Co-Design on the System-Level’Proc. IEEE Int’l Symp. Circuits and Systems’99 , June 1999. pp: 456-459.
[32] Cong, J., et al. :‘Relaxed Simulated Tempering for VLSI Floorplan Designs’, Proc. of ASP Design Automation Conference, 1999.
[33] Zhuang S, Carlsson J, Li W, et al.:“Asynchronous data communication with power for GALS systems”, The 9th IEEE Proc Int Conference on Electronics,Circuits and System(ICECS2002) .Croatia,Sept 15-18,2002.pp.753-756.
[34] A. Pinto et al. :‘Efficient Synthesis of Networks on Chip,’Proc.Int’l Conf. Computer Design 2003, Oct. 2003,pp.:146-150.
[35] N. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, 1995. pp.187-189.
[36] Chris Rowen复杂SOC设计北京:机械工业出版社2006.7
[37] Ran Ginosar, :‘Fourteen Ways to Fool Your Synchronizer’ProceedinGT of the Ninth International Symposium on Asynchronous Circuits and Systems,2003.
[38] S.W.Moore, G. S. Taylor, P. A. Cunningham, R. D. Mullins, and P. Robinson. Self-calibrating clocks for globally asynchronous locally synchronous systems. In Proc. International Conf. Computer Design (ICCD), September 2000.
[39] ITU-Trec.H.264.“Advanced video coding for generic audio visual services.”[M]. ITU-T, 2005:40-200.
[40] Hari Kalva.The H.264 Video Coding Standard[J].IEEE MultiMedia.2006,13(4):86-90.
[41] Thomas Wiegand,Gary J.Sullivan,Gisle Biontegaard and Ajay Luthra.Overview of the H.264/AVC Video Coding Standard[J].IEEETransaction on Circuits and System for Video Technology,2003.
[42] J.Ostermann,J.Bormans,P.List,D.Marpe.Video coding with H.264/AVC:tools,performance and complexity[C].IEEE Transaction on circuits and systems,2004(1):7-28.
[43]“Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification(ITU-TRec.H.264|ISO/IEC 14496-10 AVC),”in Joint Video Team(JVT)of ISO/IEC MPEG and ITU-T VCEG[M].JVTG050r1,May 2003.
[44]毕厚杰.新一代视频压缩编码标准-H.264/AVC[M].人民邮电出版社,2005:149-230.
[45] Ke Xu, Chiu-sing Choy,Cheong-Fat Chan,“Priority-based Heading One Detector in H.264/AVC Decoding”, EURASIP Journal on Embedded Systems, vol. 2007 pp18-25
[46] Saponara Sergio,Casula Michele,Rovati Fabrizio.Dynamic control of motion estimation search parameter for low complex H264 video coding[J].IEEE Transactions on Consumer Electronics,2006:232-239.
[47] C. C. Su and K. G. Shin.”Adaptive fault-tolerant deadlockfree routing in meshes and hypercubes”. IEEE Transactions on Computers. 45, (6), June 1996, pp.672-683.
[2] Tully J, Gordon R, Bruederle S, et al. Hype Cycle for semiconductors, Gartner research’s Technical Report Report. 2004. ID Number: 00120909.
[3] P.Guerrier, A. Greiner. A generic architecture for on-chip packet-switched interconnections[A], in: DATE [C]. Paris, France: March 2000 pp250-256.
[4] M. Sgroi, M.Sheets, A. Mihal, K, et al. A Sangiovanni-Vincentelli. Addressing the system-on-chip interconnect woes through communication-based design [A]. 38th Design Automation Conference. June 2001 pp667-672.
[5] Benini L, Giovanni D M. Networks on chips: a new SoC paradigm [J]. IEEE Computer.2002,35(1):70-78.
[6] Kumar S H, Jantsch A, Soininen J-P, et al. A network on chip architecture and design methodology. Proceedings of IEEE Computer Society Annual Symposium on VLSI. 2002.
[7] Rijpkema, E., Goossens, K., and Radulescu, A.:‘Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip’. Proc. Design Automation and Test in Europe, March .2003, pp. 350-355.
[8]杜高明,NoC-MPSoC多核体系结构及原型芯片实现技术研究,[D]博士学位论文,合肥工业大学,2007年5月。
[9]周干民,NoC基础研究,[D]合肥工业大学博士论文,2005。
[10]荆元利,樊晓桠,张盛兵等。基于片上网络的系统芯片测试研究[J]。微电子学与计算机,2004,21(6):154-159。
[11]荆元利,樊晓桠,网络互连多线程处理器[J]。计算机工程与应用,2005,41(33):51-53,78。
[12]周文彪,张岩,毛志刚.片上网络的低功耗自适应数据保护[J].计算机工程,2006,32(22):28-30.
[13]黎黎,片上网络路由算法研究及路由节点的FPGA设计,电子科技大学, 2007.
[14] Po-Tang Huang, Wei Hwang. 2-Level FIFO Architecture Design for Switch Fabrics in Network-on-Chip. ISCAS 2006, pp: 4863-4866.
[15] Portero, A.; Pla, R.; Rodriguez, A.; Carrabina, J. NoC Design of a Video Encoder in aMultiprocessor System on Chip Solution.
[16] A.Jantsch, H.Tenhunen , Network on chip, Kluwer Academic Publishers, 2003.
[17] P.P.Pande, C.Grecu, A.Ivanov, and R.Saleh,“Design of a Switch for Network on chip Applications,”Proc. Int’l symp. Circuits and Systems (ISCAS), vol.5,pp.217-220,May 2003.
[18] J.Duato, S. Yalamanchili, and L.Ni, Interconnection Networks—An Engineering Approach. Morgan Kaufmann,2002.
[19] David S. Bormann and Peter Y.K.Cheung.:‘Asynchronous wrapper for heterogeneous systems’.In Proc. International Conf. Computer Design (ICCD), October 1997.
[20]Culler D.E, singh J.P, Gupta A.“Parallel Computer Archiecture: A Hardware/Software Approach, Second Edition”, Morgan Kaufmann, August 1998.
[21]王文博,张金文. OPNET Modeler与网络仿真[M].第1版,北京:人民邮电出版社,2003.
[22] Benini, L.“Application Specific NoC Design”Design, Automation and Test in Europe, 2006.. Proceedings. Volume:1 March 2006 Page(s): 1-5
[23] Kees Goossens, John Dielissen, Om Prakash Gangwal.“A Design Flow for Application-Specific Networks on Chip with Guaranteed Performace to Accelerate SoC Design and Verification”Design, Automation and Test in Europe, 2005. Proceedings 7-11 March 2005 Page(s): 1182- 1187
[24]吴飞,片上网络适配单元的设计与实现,南京航空航天大学,2007.
[25]朱晓静,胡伟武,马可等.“Xmesh:一个mesh-like片上网络拓扑结构”.软件学报, Volume:9, 2007
[26]王宏伟,陆俊林,佟冬等.“层次化片上网络结构的簇生成算法”.电子学报, vol:5 2007.
[27] ARM,‘AMBA AXI Protocol Specification,’2003
[28] ALTERA,‘Avalon Interface Specification,’2004
[29] OCP- IP, OCP Specification Release2.1, http://www.ocpip.org
[30] ITRS 2001. http://public.itrs.net/Files/2001ITRS/Home.htm
[31] S.J. Krolikoski et al.:‘Methodology and Technology for Virtual Component Driven Hardware/Software Co-Design on the System-Level’Proc. IEEE Int’l Symp. Circuits and Systems’99 , June 1999. pp: 456-459.
[32] Cong, J., et al. :‘Relaxed Simulated Tempering for VLSI Floorplan Designs’, Proc. of ASP Design Automation Conference, 1999.
[33] Zhuang S, Carlsson J, Li W, et al.:“Asynchronous data communication with power for GALS systems”, The 9th IEEE Proc Int Conference on Electronics,Circuits and System(ICECS2002) .Croatia,Sept 15-18,2002.pp.753-756.
[34] A. Pinto et al. :‘Efficient Synthesis of Networks on Chip,’Proc.Int’l Conf. Computer Design 2003, Oct. 2003,pp.:146-150.
[35] N. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, 1995. pp.187-189.
[36] Chris Rowen复杂SOC设计北京:机械工业出版社2006.7
[37] Ran Ginosar, :‘Fourteen Ways to Fool Your Synchronizer’ProceedinGT of the Ninth International Symposium on Asynchronous Circuits and Systems,2003.
[38] S.W.Moore, G. S. Taylor, P. A. Cunningham, R. D. Mullins, and P. Robinson. Self-calibrating clocks for globally asynchronous locally synchronous systems. In Proc. International Conf. Computer Design (ICCD), September 2000.
[39] ITU-Trec.H.264.“Advanced video coding for generic audio visual services.”[M]. ITU-T, 2005:40-200.
[40] Hari Kalva.The H.264 Video Coding Standard[J].IEEE MultiMedia.2006,13(4):86-90.
[41] Thomas Wiegand,Gary J.Sullivan,Gisle Biontegaard and Ajay Luthra.Overview of the H.264/AVC Video Coding Standard[J].IEEETransaction on Circuits and System for Video Technology,2003.
[42] J.Ostermann,J.Bormans,P.List,D.Marpe.Video coding with H.264/AVC:tools,performance and complexity[C].IEEE Transaction on circuits and systems,2004(1):7-28.
[43]“Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification(ITU-TRec.H.264|ISO/IEC 14496-10 AVC),”in Joint Video Team(JVT)of ISO/IEC MPEG and ITU-T VCEG[M].JVTG050r1,May 2003.
[44]毕厚杰.新一代视频压缩编码标准-H.264/AVC[M].人民邮电出版社,2005:149-230.
[45] Ke Xu, Chiu-sing Choy,Cheong-Fat Chan,“Priority-based Heading One Detector in H.264/AVC Decoding”, EURASIP Journal on Embedded Systems, vol. 2007 pp18-25
[46] Saponara Sergio,Casula Michele,Rovati Fabrizio.Dynamic control of motion estimation search parameter for low complex H264 video coding[J].IEEE Transactions on Consumer Electronics,2006:232-239.
[47] C. C. Su and K. G. Shin.”Adaptive fault-tolerant deadlockfree routing in meshes and hypercubes”. IEEE Transactions on Computers. 45, (6), June 1996, pp.672-683.