基于性能监测硬件支持的片上缓存资源管理技术
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摘要
如何高效利用片上高速缓存是多核处理器研究的一个重要课题。现有的片上高速缓存管理机制是软件透明的,不能实时感知程序数据集的局部性特征,以及来自多个线程不同的访存请求。一方面,当多个线程同时在多核处理器上运行时,现有的缓存管理策略不仅不能保证每个任务的运行性能,还会导致共享缓存的多个任务之间发生不可预测的缓存竞争,形成相互干扰,降低系统的吞吐量。另一方面,由于软件不能控制缓存空间的分配,仅靠硬件进行管理,使得程序对高速缓存的利用效率不高,尤其对于单线程程序,不能利用多核处理器丰富的片上缓存资源来获得性能加速。
针对以上问题,本文研究如何利用硬件性能监测单元来实时监测程序运行时的访存特征信息,实现对多线程运行时的共享缓存竞争管理,以及对单线程程序运行时的缓存空间分配,从而提高多任务系统的吞吐量和性能稳定性,并为单线程程序执行提供高效的缓存控制手段。本文的研究内容和主要工作成果包括以下几个方面：
(1)研究了能够实时感知程序运行时访存特征的性能监测机制,提出了基于性能监测单元而实现的低代价访存性能监测方案LWM。IWM可以为用户层提供程序运行时访存性能信息的功能,以及为缓存管理器提供系统级的资源使用信息,减少了访存性能监测的代价。在实现过程中,我们在每个任务结构体中加入性能事件成员、提供事件配置的系统调用接口,并且对计数器溢出和上下文切换过程中出现的错误计数进行了处理。此外,我们还优化了性能计数器的分时复用机制,提高了多事件监测过程中的事件监测精度以及性能计数器的利用率。
(2)研究了多个任务对共享缓存资源的竞争问题,提出了访存负载概念并设计了访存负载平衡调度算法,提高了多任务系统吞吐量和程序的性能稳定性。本文提出了一种访存负载平衡调度技术来解决多任务共享缓存竞争问题。访存负载平衡调度算法参照了操作系统计算负载平衡调度算法的设计,可以作为操作系统负载平衡系统的扩展。由于本文将访存负载平衡调度实现为一个用户层的负载调度系统,所以不需要对操作系统内核进行改动。通过与其它调度算法进行实验比较后,证明本文提出的访存负载平衡调度算法在程序加权加速,以及提升系统整体吞吐量方面都有较大改进,降低了多任务对共享缓存的竞争强度,减少了系统整体的片外访存请求数量。得益于算法的稳定性能,访存负载平衡调度降低了程序多次运行之间的性能差异性,可以为操作系统实现公平可靠的任务调度算法提供支持。
(3)研究了单线程程序运行于多核处理器平台时的缓存空间利用率不高的问题,提出了一种新型缓存控制机制VSCP,提高了单线程程序的缓存利用率并加速了程序执行。本文提出的新型缓存控制方法VSCP可以有效提升单线程程序对多核处理器片上缓存空间的利用率,VSCP联合了整个系统上的缓存资源并为程序员提供显式的缓存控制接口,物理分布的缓存空间被虚拟化成用户可控的集中式缓存。与通过程序并行化来最大化计算资源的使用不同,VSCP试图去最大化缓存资源的利用率。VSCP保持单线程程序一段时间内只使用一个处理器核的状态,减少多核同时工作的功耗。另外,在片上缓存不能存放一个程序的所有工作集时,可以利用VSCP选择部分具有强局部性的数据集驻留缓存以确保这些数据不被替换或污染,降低缓存缺失率并最终加速程序。
通过对本课题的研究,我们得到了以下重要认识：
(1)访存性能对于单个程序以及系统整体性能都非常重要,在“存储墙”现象日益严重的背景下,对于提升单个程序以及系统整体性能来说,降低缓存缺失率比减少执行指令数都要更加有效。
(2)现有的缓存管理策略(包括操作系统任务调度和缓存替换策略的实现)都无法感知到线程间缓存竞争与共享关系的存在,导致低效的缓存管理。缓存资源管理必须实现线程感知的策略,否则无法为系统性能、公平性和服务质量等指标提供支持。
(3)解决多核处理器缓存资源管理最终还是需要软硬件协同配合才能完成,这需要对程序运行时和缓存管理器之间的接口进行重新设计,包括建立更好的性能监测基础设施(软、硬件)以便观察系统内部运行时情况,以及细粒度的缓存资源分配机制,这些问题的解决需要操作系统设计者、硬件架构师和程序开发人员的共同努力。
本文针对缓存资源管理而提出的关键问题解决方案,都是基于真实硬件平台进行设计实现的,是相对实际的解决方法,并且这些实现方案具有一般通用性,可以为未来处理器体系结构上的缓存资源管理机制的实现提供参考。
Utilizing on-chip cache resources efficiently is a critical issue in Chip Multiprocessor research. Software transparent feature is a main advantage of hardware cache memory, but also means unaware of program's memory accessing behaviors and different requests from multiple threads. On one hand, it brings inter-thread cache interferences while multiple threads running on a multi-core system; existing cache management schemes could not ensure performance of each program and will lead to unpredictable cache contention and poor system throughputs. On the other hand, it results in caching inefficiency of running programs especially single-threaded programs because software could not control cache space allocation, wasting plenty of on-chip cache space.
This dissertation will focus on three aspects of cache resources management, including information monitoring of running programs, cache contention management of multi-threads and cache space allocation in software manner. We implemented a scheme for monitoring programs running behavior with low cost; improved system throughputs and performance stability while running multiple threads; provided cache controlling measures for single-threaded programs execution. The major research contributions of this dissertation include:
(1) Based on performance monitoring units that embedded in modern processors, a low cost performance monitoring tool named LWM is implemented. The underlying information of running programs could be accessed at user level with the help of LWM. Performance event records are added in each task structure; providing system calling interface for events configuration. Besides, performance-counter overflows and error counting situation are properly handled in context-switches. Events monitoring precision and performance counter utilization are improved through an optimized hardware counter multiplexing mechanism.
(2) Proposed the memory load concept and designed memory load balance scheduling algorithm to improve system throughputs and performance stability of running programs. With reference to load balance scheduling in operating system, memory load balance scheduling algorithm is implemented at user level, and doesn't require modifying operating system kernel space; therefore, it could be implemented as an auxiliary facility of process scheduling mechanism. Comparing with other scheduling algorithms, MLB algorithm has better performance in weighted speedup and system throughputs; reducing a large number of off-chip memory requests. More importantly, the MLB algorithm has good stability, reducing performance deviation between different runs. It offers the possibility for implementing a task scheduling algorithm with fairness and reliability features.
(3) Designed a cache controlling mechanism named VSCP, improved caching efficiency of single-threaded program. VSCP unifies whole system cache space and provides programmers with cache space allocation interface. Physically distributed caches are virtualized as a block of centralized controllable cache. Instead of parallelizing single-threaded program to maximize computing resources, VSCP avoids reprogramming efforts with highly utilization of cache resources. Besides, it has power-saving advantage because it enables a single thread running in a period of time. We got some important understandings through cache management research:
(1) In the background of increasingly serious situation of "memory wall", memory accessing performance is very important for a single program execution and whole system throughputs. Reducing cache miss rate is becoming more importantly than instruction counts decrease.
(2) Existing cache management schemes, including task scheduling of operating system and cache replacement policy, could not get information of inter-thread cache contention, which results in inefficient cache management. Cache management schemes should be implemented in thread-aware manner; otherwise, it could not provide assurance such as performance, fairness and quality of service features.
(3) Software and hardware co-design should be the best choice for solving cache resources contention problem. We need to design new interfaces between application runtimes and the cache management, create better performance monitoring infrastructures (both in hardware and in software) that will permit better "observability" of what is happening inside the system, as well as create better mechanisms for fine-grained resource allocation in hardware. Addressing
these problems will require inter-disciplinary effort of operating system designers, hardware architects and application developers.
Cache management schemes proposed in our work are practical and implemented on real system. These solutions have general versatility and could be referred to future system architectures.
针对以上问题,本文研究如何利用硬件性能监测单元来实时监测程序运行时的访存特征信息,实现对多线程运行时的共享缓存竞争管理,以及对单线程程序运行时的缓存空间分配,从而提高多任务系统的吞吐量和性能稳定性,并为单线程程序执行提供高效的缓存控制手段。本文的研究内容和主要工作成果包括以下几个方面：
(1)研究了能够实时感知程序运行时访存特征的性能监测机制,提出了基于性能监测单元而实现的低代价访存性能监测方案LWM。IWM可以为用户层提供程序运行时访存性能信息的功能,以及为缓存管理器提供系统级的资源使用信息,减少了访存性能监测的代价。在实现过程中,我们在每个任务结构体中加入性能事件成员、提供事件配置的系统调用接口,并且对计数器溢出和上下文切换过程中出现的错误计数进行了处理。此外,我们还优化了性能计数器的分时复用机制,提高了多事件监测过程中的事件监测精度以及性能计数器的利用率。
(2)研究了多个任务对共享缓存资源的竞争问题,提出了访存负载概念并设计了访存负载平衡调度算法,提高了多任务系统吞吐量和程序的性能稳定性。本文提出了一种访存负载平衡调度技术来解决多任务共享缓存竞争问题。访存负载平衡调度算法参照了操作系统计算负载平衡调度算法的设计,可以作为操作系统负载平衡系统的扩展。由于本文将访存负载平衡调度实现为一个用户层的负载调度系统,所以不需要对操作系统内核进行改动。通过与其它调度算法进行实验比较后,证明本文提出的访存负载平衡调度算法在程序加权加速,以及提升系统整体吞吐量方面都有较大改进,降低了多任务对共享缓存的竞争强度,减少了系统整体的片外访存请求数量。得益于算法的稳定性能,访存负载平衡调度降低了程序多次运行之间的性能差异性,可以为操作系统实现公平可靠的任务调度算法提供支持。
(3)研究了单线程程序运行于多核处理器平台时的缓存空间利用率不高的问题,提出了一种新型缓存控制机制VSCP,提高了单线程程序的缓存利用率并加速了程序执行。本文提出的新型缓存控制方法VSCP可以有效提升单线程程序对多核处理器片上缓存空间的利用率,VSCP联合了整个系统上的缓存资源并为程序员提供显式的缓存控制接口,物理分布的缓存空间被虚拟化成用户可控的集中式缓存。与通过程序并行化来最大化计算资源的使用不同,VSCP试图去最大化缓存资源的利用率。VSCP保持单线程程序一段时间内只使用一个处理器核的状态,减少多核同时工作的功耗。另外,在片上缓存不能存放一个程序的所有工作集时,可以利用VSCP选择部分具有强局部性的数据集驻留缓存以确保这些数据不被替换或污染,降低缓存缺失率并最终加速程序。
通过对本课题的研究,我们得到了以下重要认识：
(1)访存性能对于单个程序以及系统整体性能都非常重要,在“存储墙”现象日益严重的背景下,对于提升单个程序以及系统整体性能来说,降低缓存缺失率比减少执行指令数都要更加有效。
(2)现有的缓存管理策略(包括操作系统任务调度和缓存替换策略的实现)都无法感知到线程间缓存竞争与共享关系的存在,导致低效的缓存管理。缓存资源管理必须实现线程感知的策略,否则无法为系统性能、公平性和服务质量等指标提供支持。
(3)解决多核处理器缓存资源管理最终还是需要软硬件协同配合才能完成,这需要对程序运行时和缓存管理器之间的接口进行重新设计,包括建立更好的性能监测基础设施(软、硬件)以便观察系统内部运行时情况,以及细粒度的缓存资源分配机制,这些问题的解决需要操作系统设计者、硬件架构师和程序开发人员的共同努力。
本文针对缓存资源管理而提出的关键问题解决方案,都是基于真实硬件平台进行设计实现的,是相对实际的解决方法,并且这些实现方案具有一般通用性,可以为未来处理器体系结构上的缓存资源管理机制的实现提供参考。
Utilizing on-chip cache resources efficiently is a critical issue in Chip Multiprocessor research. Software transparent feature is a main advantage of hardware cache memory, but also means unaware of program's memory accessing behaviors and different requests from multiple threads. On one hand, it brings inter-thread cache interferences while multiple threads running on a multi-core system; existing cache management schemes could not ensure performance of each program and will lead to unpredictable cache contention and poor system throughputs. On the other hand, it results in caching inefficiency of running programs especially single-threaded programs because software could not control cache space allocation, wasting plenty of on-chip cache space.
This dissertation will focus on three aspects of cache resources management, including information monitoring of running programs, cache contention management of multi-threads and cache space allocation in software manner. We implemented a scheme for monitoring programs running behavior with low cost; improved system throughputs and performance stability while running multiple threads; provided cache controlling measures for single-threaded programs execution. The major research contributions of this dissertation include:
(1) Based on performance monitoring units that embedded in modern processors, a low cost performance monitoring tool named LWM is implemented. The underlying information of running programs could be accessed at user level with the help of LWM. Performance event records are added in each task structure; providing system calling interface for events configuration. Besides, performance-counter overflows and error counting situation are properly handled in context-switches. Events monitoring precision and performance counter utilization are improved through an optimized hardware counter multiplexing mechanism.
(2) Proposed the memory load concept and designed memory load balance scheduling algorithm to improve system throughputs and performance stability of running programs. With reference to load balance scheduling in operating system, memory load balance scheduling algorithm is implemented at user level, and doesn't require modifying operating system kernel space; therefore, it could be implemented as an auxiliary facility of process scheduling mechanism. Comparing with other scheduling algorithms, MLB algorithm has better performance in weighted speedup and system throughputs; reducing a large number of off-chip memory requests. More importantly, the MLB algorithm has good stability, reducing performance deviation between different runs. It offers the possibility for implementing a task scheduling algorithm with fairness and reliability features.
(3) Designed a cache controlling mechanism named VSCP, improved caching efficiency of single-threaded program. VSCP unifies whole system cache space and provides programmers with cache space allocation interface. Physically distributed caches are virtualized as a block of centralized controllable cache. Instead of parallelizing single-threaded program to maximize computing resources, VSCP avoids reprogramming efforts with highly utilization of cache resources. Besides, it has power-saving advantage because it enables a single thread running in a period of time. We got some important understandings through cache management research:
(1) In the background of increasingly serious situation of "memory wall", memory accessing performance is very important for a single program execution and whole system throughputs. Reducing cache miss rate is becoming more importantly than instruction counts decrease.
(2) Existing cache management schemes, including task scheduling of operating system and cache replacement policy, could not get information of inter-thread cache contention, which results in inefficient cache management. Cache management schemes should be implemented in thread-aware manner; otherwise, it could not provide assurance such as performance, fairness and quality of service features.
(3) Software and hardware co-design should be the best choice for solving cache resources contention problem. We need to design new interfaces between application runtimes and the cache management, create better performance monitoring infrastructures (both in hardware and in software) that will permit better "observability" of what is happening inside the system, as well as create better mechanisms for fine-grained resource allocation in hardware. Addressing
these problems will require inter-disciplinary effort of operating system designers, hardware architects and application developers.
Cache management schemes proposed in our work are practical and implemented on real system. These solutions have general versatility and could be referred to future system architectures.
引文
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