用于无线传感网络的逐次逼近型模数转换器研究与实现
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摘要
随着CMOS工艺的快速发展,片上系统(System on Chip, SoC)设计逐渐成为集成电路设计的重要发展方向,单个芯片内可以集成大量的IP核如数字信号处理器、数据转换器、滤波器、存储器等。由于数字信号具有可靠性高、灵活、成本低等优点,数字信号处理已经逐步取代了传统的模拟信号处理。然而自然界的力、热、电、光、声、温度等物理信号都是模拟量,因此需要模数转换器(Analog to Digital Converter, ADC)将模拟信号转化成数字信号。
ADC是无线传感网络中的重要模块之一。无线传感网络包含大量的无线传感节点,通常给这些节点更换电池较为困难,因此低功耗无线传感网络设计是一个重要的研究课题。在众多不同结构的ADC中,基于逐次逼近(Successive Approximation Register, SAR)型ADC因其具有结构简单、功耗较低、面积较小、与数字CMOS工艺兼容等优点而获得广泛的应用。本文的主要目标是设计一款能够工作于0.6V、超低功耗的10位1MS/s采样频率的SAR ADC。本文的主要贡献和创新点如下：
1.SAR ADC中的主要模块包括数模转换器(DAC)、比较器和数字逻辑电路等。本文详细分析了这三部分电路在精度、速度和功耗这三方面的表现,并将其运用到SAR ADC的设计中。
2.在DAC电路的设计中,由于电源电压较低,基于Vcm-based开关切换方式无法采用。本文采用了单调(monotonic)开关切换方式,因为其具有较低的功耗以及简单的数字逻辑。但随之带来的问题是转换过程中共模电压的变化,导致比较器的失调电压动态变化,产生积分非线性误差。传统的解决方式是在比较器中采用固定尾电流偏置,但是这种方式不适用于低电源电压的情况,因为电压余量有限。另一种方法是将比较器的电源电压提高1倍,但是功耗却大大增加。因此本文提出并发表了一种共模稳定(common mode stabilizer)电路结构,用于解决低电源电压下单调开关切换方式带来的共模电压下降的问题。仿真结果表明加入共模稳定电路后,静态和动态性能都有显著提高,同时测试结果也验证了这种方法的有效性。
3.在比较器电路的设计中,本文采用了动态预放大再生比较器。通过预放大级降低比较器的失调电压和回馈噪声,进而提高比较器的精度。通过采用动态电路降低比较器的功耗。另外采用正反馈工作的再生锁存器来提高比较器的速度。
4.在数字逻辑电路的设计中,本文采用了异步逻辑结构而非同步逻辑结构,降低功耗的同时提高了数字逻辑电路的速度。
5.在低电源电压下开关管的设计中,采样开关管采用了自举(bootstrapping)技术,增大输入信号范围的同时,提高了采样开关管的线性度。但是自举技术需要消耗较大的功耗和面积,因此本文通过采用顶板采样技术,将需要采用自举技术的采样开关管个数减小为两个,大大降低了开关管部分的功耗。
6.本文详细分析并计算了SAR ADC中每一个电路的功耗,同时总结了一套通用的SARADC设计方法。该方法可以根据精度和速度的要求计算出SAR ADC中每一个电路模块所需的功耗值,进而可以确定SAR ADC电路中管子的参数。
基于TSMC0.13μmCMOS工艺设计并实现了一个0.6V10位1MS/s SAR ADC,芯片核心面积只有0.04mm2。本文对ADC的测试方法(主要包括静态测试和动态测试)进行了研究与分析后,对本文设计的SAR ADC进行了详细的测试。测试结果显示,SAR ADC在0.6V电源电压和Nyquist输入信号频率下具有51.25dB信号噪声失真比,在1MS/s采样频率下功耗仅为6.3μW,品质因数FOM(figure of merit)为21fJ/(conversion.Fs),静态特性的微分非线性和积分非线性误差分别为-0.91/+1.58LSB和-1.15/+1.99LSB,较好地满足了无线传感网络的应用要求。
With the fast development of CMOS technology, system on chip (SOC) design has become an important developing trend of the integrated circuit. A large number of IP cores have been integrated on a single chip, such as digital signal processor (DSP), data converter, filter, memory, et al. Digital signal processing is gradually taking the place of the traditional analog signal processing due to its high reliability, strong flexibility, and low cost. As physical signals such as force, heat, electricity, light, sound and temperature are all analog signals, analog-to-digital converter (ADC) is required which converts the analog signal into the digital signal.
ADC is a fundamental block for wireless sensor networks (WSN). WSN contains multiple sensor nodes. In most cases, changing their batteries is impractical, therefore, low power design of the WSN has become an important research issue. Among different conversion topologies, Successive Approximation Register (SAR) ADC has been widely used for its simple structure, low power, small area and compatibility with standard digital CMOS technology. The main aim of this thesis is designing a low power10bit1MS/s SAR ADC which can work at0.6V supply voltage. The main contributions and innovation are as follows:
1. The SAR ADC is mainly composed of digital to analog converter (DAC), comparator, and digital control logic, etc. In this thesis, a detailed analysis of the performance of these circuits in terms of accuracy, speed, and power consumption is presented, and then it is applied in the design of the SAR ADC.
2. In the DAC, the Vcm-based switching schemes are not employed, due to the low supply voltage. In this thesis, monotonic switching scheme is employed in the DAC due to its power efficiency and simplified digital logic. While the main drawback of monotonic switching scheme is its large common mode shift and the associated comparator offset dynamic variation. The varying offset is the major source of integral nonlinearity (INL). To solve this problem, the conventional constant current biasing technique can't be applied to the dynamic comparator due to the limited headroom. Another method uses a supply-boost technique to increase the supply voltage of the comparator to2×VDD, which allows constant current biasing but significantly increased the power consumption. Common mode stabilizer (CMS) is proposed for the first time to address this issue in low-voltage design. Simulation results show that with the proposed common mode stabilizer applied, the performance of the static and dynamic is greatly improved. The effectiveness of this method is also verified through the measurement results.
3. In the comparator, a preamplifier with dynamic latch is adopted in this thesis. The offset voltage and kickback noise can both be reduced with the preamplifier applied. Therefore, the accuracy of the comparator can be improved. In order to reduce the power consumption, dynamic circuit is used. Furthermore, the speed of the comparator can be increased by using the regenerative latch.
4. In the digital logic circuit, the asynchronous logic is adopted for the low power and high speed.
5. In the switches with low voltage supply, boostrapping technique is used in the sampling switch which can increase the range of the input signal and improve the linearity of the sampling switch. While the boostrapping technique consumes large area and power consumption, top plate sampling technique is employed so that the number of switches which should treat the input signal ranging from supply voltage to ground is reduced to two. The power consumption of the switches is greatly reduced.
6. This thesis details and calculates the power consumption of every building block in the SAR ADC, and summarizes a general design method about SAR ADC. The power consumption can be calculated under the accuracy and the speed requirement. Therefore, the size of the transistors in the SAR ADC can be chosen.
A10-bit1MS/s SAR ADC is implemented based on TSMC0.13μm CMOS technology. The core area is only0.04mm2. This thesis also discusses the test of ADC, which is including static and dynamic parameter test. The measurement results show that the proposed SAR ADC consumes6.3μW at1MS/s from0.6V supply, and achieves51.25dB SNDR at Nyquist frequency and FOM of21fJ/conversion-step. The measured peak DNL and INL are-0.91/+1.58LSB and-1.15/+1.99LSB, respectively. The proposed SAR ADC meets the requirements of the WSN.
ADC是无线传感网络中的重要模块之一。无线传感网络包含大量的无线传感节点,通常给这些节点更换电池较为困难,因此低功耗无线传感网络设计是一个重要的研究课题。在众多不同结构的ADC中,基于逐次逼近(Successive Approximation Register, SAR)型ADC因其具有结构简单、功耗较低、面积较小、与数字CMOS工艺兼容等优点而获得广泛的应用。本文的主要目标是设计一款能够工作于0.6V、超低功耗的10位1MS/s采样频率的SAR ADC。本文的主要贡献和创新点如下：
1.SAR ADC中的主要模块包括数模转换器(DAC)、比较器和数字逻辑电路等。本文详细分析了这三部分电路在精度、速度和功耗这三方面的表现,并将其运用到SAR ADC的设计中。
2.在DAC电路的设计中,由于电源电压较低,基于Vcm-based开关切换方式无法采用。本文采用了单调(monotonic)开关切换方式,因为其具有较低的功耗以及简单的数字逻辑。但随之带来的问题是转换过程中共模电压的变化,导致比较器的失调电压动态变化,产生积分非线性误差。传统的解决方式是在比较器中采用固定尾电流偏置,但是这种方式不适用于低电源电压的情况,因为电压余量有限。另一种方法是将比较器的电源电压提高1倍,但是功耗却大大增加。因此本文提出并发表了一种共模稳定(common mode stabilizer)电路结构,用于解决低电源电压下单调开关切换方式带来的共模电压下降的问题。仿真结果表明加入共模稳定电路后,静态和动态性能都有显著提高,同时测试结果也验证了这种方法的有效性。
3.在比较器电路的设计中,本文采用了动态预放大再生比较器。通过预放大级降低比较器的失调电压和回馈噪声,进而提高比较器的精度。通过采用动态电路降低比较器的功耗。另外采用正反馈工作的再生锁存器来提高比较器的速度。
4.在数字逻辑电路的设计中,本文采用了异步逻辑结构而非同步逻辑结构,降低功耗的同时提高了数字逻辑电路的速度。
5.在低电源电压下开关管的设计中,采样开关管采用了自举(bootstrapping)技术,增大输入信号范围的同时,提高了采样开关管的线性度。但是自举技术需要消耗较大的功耗和面积,因此本文通过采用顶板采样技术,将需要采用自举技术的采样开关管个数减小为两个,大大降低了开关管部分的功耗。
6.本文详细分析并计算了SAR ADC中每一个电路的功耗,同时总结了一套通用的SARADC设计方法。该方法可以根据精度和速度的要求计算出SAR ADC中每一个电路模块所需的功耗值,进而可以确定SAR ADC电路中管子的参数。
基于TSMC0.13μmCMOS工艺设计并实现了一个0.6V10位1MS/s SAR ADC,芯片核心面积只有0.04mm2。本文对ADC的测试方法(主要包括静态测试和动态测试)进行了研究与分析后,对本文设计的SAR ADC进行了详细的测试。测试结果显示,SAR ADC在0.6V电源电压和Nyquist输入信号频率下具有51.25dB信号噪声失真比,在1MS/s采样频率下功耗仅为6.3μW,品质因数FOM(figure of merit)为21fJ/(conversion.Fs),静态特性的微分非线性和积分非线性误差分别为-0.91/+1.58LSB和-1.15/+1.99LSB,较好地满足了无线传感网络的应用要求。
With the fast development of CMOS technology, system on chip (SOC) design has become an important developing trend of the integrated circuit. A large number of IP cores have been integrated on a single chip, such as digital signal processor (DSP), data converter, filter, memory, et al. Digital signal processing is gradually taking the place of the traditional analog signal processing due to its high reliability, strong flexibility, and low cost. As physical signals such as force, heat, electricity, light, sound and temperature are all analog signals, analog-to-digital converter (ADC) is required which converts the analog signal into the digital signal.
ADC is a fundamental block for wireless sensor networks (WSN). WSN contains multiple sensor nodes. In most cases, changing their batteries is impractical, therefore, low power design of the WSN has become an important research issue. Among different conversion topologies, Successive Approximation Register (SAR) ADC has been widely used for its simple structure, low power, small area and compatibility with standard digital CMOS technology. The main aim of this thesis is designing a low power10bit1MS/s SAR ADC which can work at0.6V supply voltage. The main contributions and innovation are as follows:
1. The SAR ADC is mainly composed of digital to analog converter (DAC), comparator, and digital control logic, etc. In this thesis, a detailed analysis of the performance of these circuits in terms of accuracy, speed, and power consumption is presented, and then it is applied in the design of the SAR ADC.
2. In the DAC, the Vcm-based switching schemes are not employed, due to the low supply voltage. In this thesis, monotonic switching scheme is employed in the DAC due to its power efficiency and simplified digital logic. While the main drawback of monotonic switching scheme is its large common mode shift and the associated comparator offset dynamic variation. The varying offset is the major source of integral nonlinearity (INL). To solve this problem, the conventional constant current biasing technique can't be applied to the dynamic comparator due to the limited headroom. Another method uses a supply-boost technique to increase the supply voltage of the comparator to2×VDD, which allows constant current biasing but significantly increased the power consumption. Common mode stabilizer (CMS) is proposed for the first time to address this issue in low-voltage design. Simulation results show that with the proposed common mode stabilizer applied, the performance of the static and dynamic is greatly improved. The effectiveness of this method is also verified through the measurement results.
3. In the comparator, a preamplifier with dynamic latch is adopted in this thesis. The offset voltage and kickback noise can both be reduced with the preamplifier applied. Therefore, the accuracy of the comparator can be improved. In order to reduce the power consumption, dynamic circuit is used. Furthermore, the speed of the comparator can be increased by using the regenerative latch.
4. In the digital logic circuit, the asynchronous logic is adopted for the low power and high speed.
5. In the switches with low voltage supply, boostrapping technique is used in the sampling switch which can increase the range of the input signal and improve the linearity of the sampling switch. While the boostrapping technique consumes large area and power consumption, top plate sampling technique is employed so that the number of switches which should treat the input signal ranging from supply voltage to ground is reduced to two. The power consumption of the switches is greatly reduced.
6. This thesis details and calculates the power consumption of every building block in the SAR ADC, and summarizes a general design method about SAR ADC. The power consumption can be calculated under the accuracy and the speed requirement. Therefore, the size of the transistors in the SAR ADC can be chosen.
A10-bit1MS/s SAR ADC is implemented based on TSMC0.13μm CMOS technology. The core area is only0.04mm2. This thesis also discusses the test of ADC, which is including static and dynamic parameter test. The measurement results show that the proposed SAR ADC consumes6.3μW at1MS/s from0.6V supply, and achieves51.25dB SNDR at Nyquist frequency and FOM of21fJ/conversion-step. The measured peak DNL and INL are-0.91/+1.58LSB and-1.15/+1.99LSB, respectively. The proposed SAR ADC meets the requirements of the WSN.
引文
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