部分绝缘键合SOI新结构及应用基础研究
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摘要
基于SOI相关基础理论和技术实践,源自光机电新器件开发需求,在综合Si良好导热导电与SOI优良隔离特性基础上,本文提出了一种兼具硅和SOI优势的新型部分绝缘键合SOI结构,并就其所面临的预键合量化微观作用机理、应用基础理论和关键工艺技术进行了探讨与分析讨论。
     首先,通过对部分绝缘键合SOI预键合3种主要微观作用力的比较研究,获得了平板间Van der Waals作用力模型及其计算方法。结果指出,亲水性硅片键合中氢键作用力是主要因素,而疏水性硅片键合中主要因素为Van der Waals作用力,毛细作用和大气压作用则是可忽略的次要因素。
     计算表明,疏水性硅片预键合Van derWaals作用能约为124mJ/m~2,对于4英寸硅片,相应键合吸引力是9.73×10~6N;亲水性硅片预键合氢键作用能约为193.3mJ/m~2;毛细作用力约2.55×10~(-3)~8.49×10~(-1) N,毛细作用相关的大气压力系7.93×10~2N。
     考虑实际情况中存在颗粒、台阶情况下,硅片预键合时封闭的微量气体是键合不可忽视的不利因素。预键合过程是实际硅片键合面非理想平整性所占百分比引起的硅片弹性形变与键合面微观作用力博弈结果。此过程与预键合实际接触面百分比和硅片间距两个主要因素有关。对4英寸硅片,预键合硅片间距小于5nm时,键合面微观吸引力占优势,并导致动态正反馈,引起所谓“键合波”,使硅片能够键合。在100mJ/m~2预键合能假设下,键合硅片接触面间距约为0.22nm。通过比较分析,发现键合硅片采用接触面积来计算毛细作用力是不适合的,而把这种毛细作用力看作边缘曲线而不是面积作用力则更为合理。
     其次,大电流功率集成电路广泛存在埋层结构的比导通电阻优化是所述部分绝缘键合SOI面临的另一基本问题。对此,提出了简化二维和三维模型。得到的结论是在二维情况下,该结构的电阻具有自限制特性,比电阻具有近似的随尺寸增加而线性增加特性;在三维情况下,其埋层电阻不再具有自限制特性,但比电阻仍然有同样近似线性增加的特性。实验和仿真分析表明,该模型在导通电阻变化的拐点预测上有较高精度,而此结构电阻实验数据较模型预测值约小28%。
     再者,基于兼容部分绝缘键合SOI工艺的VDMOS和X射线的不同负载功率情况下辐射实验,进行了部分绝缘键合SOI在功率集成领域所面临的抗总剂量辐射应用探索。据器件X射线辐射亚阈值Ⅰ-Ⅴ曲线,观察到了器件大负载功率在自热退火情况下与经典文献不一致特征,且结合经典理论,提出了界面陷阱的导电假设;并构建了与实验数据相吻合的器件模型,导出了新增氧化物陷阱正电荷与强反型前最大界面陷阱负电荷近似相等约为6.78×10~(11)cm~(-2),强反型后最大界面陷阱负电荷减小到1.54×10~(11)cm~(-2)的结果。
     鉴于实验研究与可行性验证的考虑,提出了LPCVD和外延多晶作为键合界面过渡层方法,从而使该结构的键合完整率大于85%,键合界面电阻小于5×10~(-4)Ω.cm~2。同时,开展了部分绝缘键合SOI集成垂直导电VDMOS的BCD工艺和器件研究;实验结果显示,其VDMOS击穿电压为160V,导通电阻0.3Ω,比导通电阻26mΩ.cm~2,NPN、PMOS、NMOS击穿电压分别是50V、35V、30V,NPN电流增益120,截止频率700MHz。
     预计部分绝缘键合SOI结构及相关技术可望用于新型集成器件,尤其是需厚硅膜的汽车电子、抗辐射、强电磁脉冲环境下单片集成器件、微电子机械系统MEMS和光集成电路OEIC等领域,并希就此主题引起相应的关注与交流讨论。
From basic theory and technology practice of SOI for new optoelectronic andMicro-Electro-Mechanical Systems application requirement,a novel Partial InsulationBonding SOI (PIB/SOI) structure is proposed due to its good thermal and electricalconductivity of silicon without losing normal SOI's good isolation property.Severalinterrelated basic microcosmic forces mechanism of wafer pro-bond and application keytechnical problems are diccussed and researched.
     The first problem interrelated with PIB/SOI stucture is how microcosmic forces orintermolecular forces affect pro-bond of silicon wafer.Three type microcosmic forceshave been compared and analysed.Three main conclusions have been drawn:microcosmic forces of hydrophilic silicon wafer bonding attribute to hydroen bond,hydrophobic silicon wafer bonding attribute to Van der Waals forces,capillaryimmersion forces and interrelated atmospheric pressure forces are neglectable.Analysiscalculation indicate that,for 4 inch wafer,Van der Waals interplay energy is about124mJ/m~2,corresponding forces 9.73×10~6 N,and,hydroen bond interplay energy about193.3mJ/m~2 to hydrophilic bonding,capillary immersion forces about 2.55×10~(-3)~8.49×10~(-1) N,and corresponding atmospheric pressure forces 7.93×10~2 N.
     Also,the micro volume gas sealed by tiny grain caused by actually clean roomentironment and micro-step caused by silicon process is a signify disbenefit factor forwafer pro-bond.The successful or not of wafer bonding is a zero sum game caused byhow much area percent of wafer surface is absolute flatness which increase pro-bondforces against elastic deflection which decrease pro-bond forces.This process has twofactor,most important one is how close the two wafer bonding surface gap can be,another is how many percent area of two wafer bonding surface can close with a givenminimum distance.Calculation indicate that this given minimum distance is about 5nmfor 4 inch wafer.When the gap of two wafer bonding surface is less than 5nm,microcosmic attraction is dominance,which cause to positive feedback and thephenomenon which is called“bonding wave”,then,the wafer bond at a given percentcontact surface area of two wafer finally.On supposition 100mJ/m~2 pro-bond energy,gap distance of two wafer surface is 0.22nm.Viewpoint of capillary immersion forces can only be calculated as beeline or curve line or point rather than a plane or curvedsurface is presented.
     Secondly,resistance optimization of IC with bury layer,especially for big currentpower IC is another basic problem interrelated with PIB/SOI stucture.Simplification2-D and 3-D model are proposed to solve it.The 2-D model indicate that integrateddevice structure with bury layer has self-limitation resistance property and specificresistance increase almost linearly with device area.The 3-D model has no property ofself-limitation resistance,while the result is the same as that for specific resistance of2-D structure.Experiment and simulation indicate that,experiment value is smaller thanmodel predicted value almost 28%,while inflection point prediction of resistance curveis accurate.
     Thirdly,problem interrelated with PIB/SOI stucture is total dose radiationcharacter of PIB/SOI device,especially for VDMOS with different load powerdissipation case.Based on measurement of VDMOS I-V curve after X-ray radiationunder diverse power dissipation,it is found that,property of new interface traps inducedby X-ray radiation with self annealing VDMOS sample,i.e.with big power dissipation,does not conform to existing theory commendably.For explaining this characters,combined with traditional theory,a assumption of interface trap current conductiveproperty is proposed and a model is exported,which gives a more exact result.Newoxide charges,maximum interface trap negative charges before and after stronginvention is 6.78×10~(11)cm~(-2),-6.78×10~(11)cm~(-2),-1.54×10~(11)cm~(-2) according to model.
     For experiment and realization,a method of LPCVD and epitaxy transitionpolysilicon layer is introduced,which make integrality percentage of this new waferstructure more than 85% and contact specific resistance of Si-Si bonding interface lessthan 5×10~(-4)Ω.cm~2.BCD process with integrated vertical conductive VDMOS has beenmade,and breakdown voltage of this BCD structure VDMOS is 160V,on-resistance0.3Ω,specific on-resistance 26mΩ·cm~2,breakdown voltage of NPN/PMOS/NMOS50V/35V/30V respectively,NPN current gain and cut-off frequency 120 and 700MHzrespectively.
     This PIB/SOI stucture may be an useful technique in application of automotiveelectronics,radiation hardened and strong Electromagnetic Pulse (EMP),high voltageIC,high reliability IC,MEMS and OEIC.
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