非单一SiO_2埋层的SOI新结构研究
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摘要
探索研究新的SOI结构成为SOI研究领域新的热点。传统SOI结构是以SiO_2作为绝缘埋层，由于氧化硅的低热导率而使SOI器件／电路存在自加热效应，在SOI结构中引入新的埋层成为了解决这些问题的有效途径。本论文结合我们承担的973、国家自然科学基金项目等国家任务，开展了以Si_3N_4、SiO_2/Si_3N_4、SiO_2／Si_3N_4／SiO_2等为埋层的新型SOI结构等材料的制备、性能及其应用的研究。获得了以下主要结果：
采用X射线四晶衍射仪定量测试ELTRAN技术制备的SOI材料的顶层硅应变，分析了ELTRAN SOI顶层硅应变产生原因。
采用超高真空电子束蒸发技术，以Fe为催化剂，成功的在硅和多孔硅衬底上生长纳米硅锥阵列，结果表明这些纳米硅锥阵列具有良好的场发射性能。
为减轻传统SOI器件／电路的自加热效应，首次采用多孔硅外延转移技术制备出以氮化硅为埋层的SOI新结构。测试结果表明制备的新SOI样品具有较好的结构性能，但由于热应力的不匹配，顶层硅与氮化硅界面处有损伤存在。这种新结构的电阻率分布均匀，绝缘埋层具有很好的绝缘性能。
为避免顶层Si／Si_3N_4界面处存在的高界面态，成功的采用多孔硅外延转移技术制备出以SiO_2／Si_3N_4为双埋层的SOIM新结构，其中二氧化硅作为过渡层。结果表明制备的SOIM样品具有很好的结构性能，顶层硅电阻率分布均匀，绝缘埋层具有很好的绝缘性能。由于二氧化硅过渡层的引入，大大减轻了氮化硅与硅直接接触而引入的缺陷和高界面态。
采用Medici软件模拟以SiO_2／Si_3N_4为埋层的SOIM MOSFET在抑制自加热效应方面的所表现的优越性。
为减少双埋层SOIM片的翘曲度及减少这种结构中由于硅衬底与氮化硅直接接触引入的高界面态，首次采用智能剥离技术成功制备出以SiO_2／Si_3N_4／SiO_2为三埋层SOIM新结构，其中的两个二氧化硅埋层均为过渡层；实验结果表明三埋层的SOIM结构具有优良的结构性能和电学特性。
摘要
采用Smart一cut技术制备了单晶硅SOG材料，实验结果表明该结构具有良
好的性能
Due to the poor thermal conductivity of buried oxide layer, self-heating effect in SOI devices limits the applicability of standard SOI materials. In order to resolve the question and meet the demand of special device/circuit, there has been a strong interest in the development new SOI structures. Replacement of the buried silicon dioxide by a better thermal conductor could minimize the effect effectively. Based on the demands and supports of special Funds for Major State Basic Research projects and the national natural science foundation of china, we have made a series of investigations on fabrication and characterization of new SOI structures (Si-Si3N4-Si substrate, Si-SiO2-Si3N4-Si substrate and Si-SiO2-Si3N4 -Si02-Si substrate), SOG (Silicon-On-Glass) and other new materials. Main new
results are drawn as follows:
The properties of SOI materials fabricated by epitaxial layer transfer technology were investigated. Silicon nanorods (about 10-35nm height) on silicon and porous silicon substrates were synthesized using Ultra-high vacuum electron beam evaporation in the present of a Fe catalyst. AFM is used to estimate the dimension and check the morphology of the silicon nanoclusters. The electron field emission is used to reveals the property of silicon nanorods grown on different substrates.
SOI structures with Si3N4 film as buried insulator were successfully formed using epitaxial layer transfer technology for the first time. The structural and electrical properties of the new SOI structures were investigated by XTEM and SRP. Due to high stress between the Si/Si3N4 there is a high interface defect
Abstract
density inherent to silicon nitride interface.
We have successfully fabricated SOIM structures with SiO2-Si3N4 as buried insulating films using epitaxial layer transfer technology. XTEM and SRP results show the formed SOIM sample has good structural and electrical properties. The oxide layer underneath the thin silicon film can avoid a high interface defect density inherent to silicon nitride interface. The SOIM structures fabricated by this method is a good candidate to be used in micro-electronic and micro-technology applications where thermal effects are to be taken into account, specially when thermal dissipation is needed.
The devices based on new SOIM structure has been verified in two-dimensional device simulation and indicated that the new structures reduce device self-heating effect and increase the drain of the SOI MOSFET.
It is the first time that we fabricated SOIM structures with SiO2-Si3N4-SiO2 as buried insulating films using Smart-cut technology. XTEM and SRP results show the sample has good structural and electrical properties. The oxide layer between the Si and Si3N4 can avoid a high interface defect density inherent to silicon nitride interface and decrease the bow the wafer.
Fabricated monocrystalline SOG (Silicon On Glass) structures by field-assisted bonding technology. The experience results the top silicon has good electrical properties. The integration process of Si and LiTaO3 by Smart-cut technology was created.
采用X射线四晶衍射仪定量测试ELTRAN技术制备的SOI材料的顶层硅应变，分析了ELTRAN SOI顶层硅应变产生原因。
采用超高真空电子束蒸发技术，以Fe为催化剂，成功的在硅和多孔硅衬底上生长纳米硅锥阵列，结果表明这些纳米硅锥阵列具有良好的场发射性能。
为减轻传统SOI器件／电路的自加热效应，首次采用多孔硅外延转移技术制备出以氮化硅为埋层的SOI新结构。测试结果表明制备的新SOI样品具有较好的结构性能，但由于热应力的不匹配，顶层硅与氮化硅界面处有损伤存在。这种新结构的电阻率分布均匀，绝缘埋层具有很好的绝缘性能。
为避免顶层Si／Si_3N_4界面处存在的高界面态，成功的采用多孔硅外延转移技术制备出以SiO_2／Si_3N_4为双埋层的SOIM新结构，其中二氧化硅作为过渡层。结果表明制备的SOIM样品具有很好的结构性能，顶层硅电阻率分布均匀，绝缘埋层具有很好的绝缘性能。由于二氧化硅过渡层的引入，大大减轻了氮化硅与硅直接接触而引入的缺陷和高界面态。
采用Medici软件模拟以SiO_2／Si_3N_4为埋层的SOIM MOSFET在抑制自加热效应方面的所表现的优越性。
为减少双埋层SOIM片的翘曲度及减少这种结构中由于硅衬底与氮化硅直接接触引入的高界面态，首次采用智能剥离技术成功制备出以SiO_2／Si_3N_4／SiO_2为三埋层SOIM新结构，其中的两个二氧化硅埋层均为过渡层；实验结果表明三埋层的SOIM结构具有优良的结构性能和电学特性。
摘要
采用Smart一cut技术制备了单晶硅SOG材料，实验结果表明该结构具有良
好的性能
Due to the poor thermal conductivity of buried oxide layer, self-heating effect in SOI devices limits the applicability of standard SOI materials. In order to resolve the question and meet the demand of special device/circuit, there has been a strong interest in the development new SOI structures. Replacement of the buried silicon dioxide by a better thermal conductor could minimize the effect effectively. Based on the demands and supports of special Funds for Major State Basic Research projects and the national natural science foundation of china, we have made a series of investigations on fabrication and characterization of new SOI structures (Si-Si3N4-Si substrate, Si-SiO2-Si3N4-Si substrate and Si-SiO2-Si3N4 -Si02-Si substrate), SOG (Silicon-On-Glass) and other new materials. Main new
results are drawn as follows:
The properties of SOI materials fabricated by epitaxial layer transfer technology were investigated. Silicon nanorods (about 10-35nm height) on silicon and porous silicon substrates were synthesized using Ultra-high vacuum electron beam evaporation in the present of a Fe catalyst. AFM is used to estimate the dimension and check the morphology of the silicon nanoclusters. The electron field emission is used to reveals the property of silicon nanorods grown on different substrates.
SOI structures with Si3N4 film as buried insulator were successfully formed using epitaxial layer transfer technology for the first time. The structural and electrical properties of the new SOI structures were investigated by XTEM and SRP. Due to high stress between the Si/Si3N4 there is a high interface defect
Abstract
density inherent to silicon nitride interface.
We have successfully fabricated SOIM structures with SiO2-Si3N4 as buried insulating films using epitaxial layer transfer technology. XTEM and SRP results show the formed SOIM sample has good structural and electrical properties. The oxide layer underneath the thin silicon film can avoid a high interface defect density inherent to silicon nitride interface. The SOIM structures fabricated by this method is a good candidate to be used in micro-electronic and micro-technology applications where thermal effects are to be taken into account, specially when thermal dissipation is needed.
The devices based on new SOIM structure has been verified in two-dimensional device simulation and indicated that the new structures reduce device self-heating effect and increase the drain of the SOI MOSFET.
It is the first time that we fabricated SOIM structures with SiO2-Si3N4-SiO2 as buried insulating films using Smart-cut technology. XTEM and SRP results show the sample has good structural and electrical properties. The oxide layer between the Si and Si3N4 can avoid a high interface defect density inherent to silicon nitride interface and decrease the bow the wafer.
Fabricated monocrystalline SOG (Silicon On Glass) structures by field-assisted bonding technology. The experience results the top silicon has good electrical properties. The integration process of Si and LiTaO3 by Smart-cut technology was created.
引文
[1] J.P.Collinge, SOI Technology: Materials to VISL, Kluwer Academic Pub.1991: 84
[2] SILICON-ON-INSULATOR TECHNOLOGY AND DEVICESX, S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 43
[3] 林成鲁、张苗，SOI—二十一世纪的微电子技术，功能材料与器件学报， 5，1999：1．
[4] A. O. Adan, T. Naka, A. Kagisawa, H. Shimizu, SOI as a Mainstream IC Technology Proceedings, 1998 IEEE International SOI Conference, Oct. 1998: 9.
[5] R. F. Service, Science, Vol.14, 1998: 281.
[6] http://www.Bookham.com
[7] 《今日电子》，2002年第2期。
[8] C.Maleville, T.Barge, B.Ghyselen and A.J.Auberton. 2000 IEEE International SOI Conference, Oct.2000: 36.
[9] Rutger Vrijen, Eli Yablononitch, et al, Physical Review A, Vol.62, 2000: 012306
[10] A.Uhlir, Bell System Tech.,J., 36, 1956: 333
[11] UT.Unagami, M.Seki., J. Electrochem. Soc., 1978, 125: 1339
[12] K.Imai, Solid State Electron., 24, 1981: 59
[13] Nobuhiko Sato, Kiyofumi Sakaguchi, et al., J. Electrochem. Soc., 142, 1995: 3116
[14] T. Yonehara, K. Sakaguchi and N. Sato, Appl. Phys. Lett., 64, 1994: 2108
[15] T.Yonehara: "SOI-Epi Wafers", Break Through, April 1999 edition, Realize Inc., Tokyo, 1999: 15-18.
[16] Edited by L.Canham: "Properties of Porous Si", INSPEC, United Kingdom, 1997: 41.
[17] ELTRAN(?)(SOI-Epi WaferTM) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 4.
[18] N.Sato, K.Sakaguchi, K.Yamagata, Y.Fujiyama, J.Nakayama, and T.Yonehara: "Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si", Ext. Abst. 1995 Int. Conf. SSDM, The Japan Society of Applied Physics, Osaka, 1995: 845-847.
[19] N.Sato, K.Sakaguchi, K.Yamagata, Y.Fujiyama, J.Nakayama, and T.Yonehara: "Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si", Jpn. J. Appl. Phys., 35, 1996: 842-847.
[20] ELTRAN(?)(SOI-Epi WaferTM) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 7.
[21] ELTRAN(?)(SOI-Epi Wafer~(TM)) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 13.
[22] O.Rayssac, H.Moriceau, M.Olivier, I.Stoemenos, A.M.Cartier and B.Q.Aspar. SILICON-ON-INSULATOR TECHNOLOGY AND DEVICESX,
S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142.
[23] 门传玲，郑志宏，多新中，林成鲁，中国电子学会论文集，第十二届全国半导体集成电路／硅材料学术会论文集，2001．4：292。
[24] Professor H S Gamble SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES X. S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142-146.
[25] J.Raskin, A.Viviani, D.Flandre, J.Colinge, IEEE Transactions on Electron Devices, vol.44, December 1997:2252-2261.
[26] C.P.Yue, and S.S.Wong, IEEE Transactions of Solid-State Circuits, vol.33, no.5, May 1998: 145-148.
[27] P.T.Baine, D.L.Gay, B.M.Armstrong and H.S.Gamble,J.Electrochem. Soc, vol. 145, No.5, May 1998: 1738-1743.
[28] T.Ernst and S.Cristolovemeau, ECS SOI Technology and Devices Ⅸ, Seattle 1999
[29] Thomas Skotnicki, SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES, X.S.Cristoloveanu, RL.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142.
[30] C.Fiegna, H.lwai, T.Saito, E.Sangiorgi, B.Ricco, A new scaling methodology for the 0.1-0.0025um MOSFET, Symp.VLSI Techn.Dig, 1993: 33-34.
[31] R.H.Yan, A.Ourmazd, K.F.Lee, Scaling the Si MOSFET: From Bulk to SOI to Bulk, IEEE Trans. Electron Devices, vol.39,no.7, 1992: 1704-1710.
[32] W.L.Goh, D.L.Gampbell, B.M.Armstrong, and H.S.Gamble, Proc.of the Third International Symposium on Semiconductor Wafer Bonding Science, Technology and Applications, The Electrochemical Society, Reno, May1995. vol. 95-7: 553-560.
[33] Philips and SOITEC, European Semiconductor, February 2002: 20.
[34] C.Serre, A.Pere-Rodriguez, A.Romano-Rodriguez, J.R.Morante, SILICON-ON-INSU LATOR TECHNOLOGY AND DEVICES X, S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K. Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 148.
[35] Gianni Taraschi, Zhi-Yuan Cheng, SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES,X. S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 46.
[36] 安正华，张苗，沈勤我，林成鲁，中国电子学会论文集，第十二届全国半导体集成电路／硅材料学术会论文集，2001．4，P348。
[2] SILICON-ON-INSULATOR TECHNOLOGY AND DEVICESX, S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 43
[3] 林成鲁、张苗，SOI—二十一世纪的微电子技术，功能材料与器件学报， 5，1999：1．
[4] A. O. Adan, T. Naka, A. Kagisawa, H. Shimizu, SOI as a Mainstream IC Technology Proceedings, 1998 IEEE International SOI Conference, Oct. 1998: 9.
[5] R. F. Service, Science, Vol.14, 1998: 281.
[6] http://www.Bookham.com
[7] 《今日电子》，2002年第2期。
[8] C.Maleville, T.Barge, B.Ghyselen and A.J.Auberton. 2000 IEEE International SOI Conference, Oct.2000: 36.
[9] Rutger Vrijen, Eli Yablononitch, et al, Physical Review A, Vol.62, 2000: 012306
[10] A.Uhlir, Bell System Tech.,J., 36, 1956: 333
[11] UT.Unagami, M.Seki., J. Electrochem. Soc., 1978, 125: 1339
[12] K.Imai, Solid State Electron., 24, 1981: 59
[13] Nobuhiko Sato, Kiyofumi Sakaguchi, et al., J. Electrochem. Soc., 142, 1995: 3116
[14] T. Yonehara, K. Sakaguchi and N. Sato, Appl. Phys. Lett., 64, 1994: 2108
[15] T.Yonehara: "SOI-Epi Wafers", Break Through, April 1999 edition, Realize Inc., Tokyo, 1999: 15-18.
[16] Edited by L.Canham: "Properties of Porous Si", INSPEC, United Kingdom, 1997: 41.
[17] ELTRAN(?)(SOI-Epi WaferTM) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 4.
[18] N.Sato, K.Sakaguchi, K.Yamagata, Y.Fujiyama, J.Nakayama, and T.Yonehara: "Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si", Ext. Abst. 1995 Int. Conf. SSDM, The Japan Society of Applied Physics, Osaka, 1995: 845-847.
[19] N.Sato, K.Sakaguchi, K.Yamagata, Y.Fujiyama, J.Nakayama, and T.Yonehara: "Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si", Jpn. J. Appl. Phys., 35, 1996: 842-847.
[20] ELTRAN(?)(SOI-Epi WaferTM) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 7.
[21] ELTRAN(?)(SOI-Epi Wafer~(TM)) Technology, Takao Yonehara and Kiyofumi Sakaguchi, ELTRAN Business Center, Canon Inc., 2000: 13.
[22] O.Rayssac, H.Moriceau, M.Olivier, I.Stoemenos, A.M.Cartier and B.Q.Aspar. SILICON-ON-INSULATOR TECHNOLOGY AND DEVICESX,
S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142.
[23] 门传玲，郑志宏，多新中，林成鲁，中国电子学会论文集，第十二届全国半导体集成电路／硅材料学术会论文集，2001．4：292。
[24] Professor H S Gamble SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES X. S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142-146.
[25] J.Raskin, A.Viviani, D.Flandre, J.Colinge, IEEE Transactions on Electron Devices, vol.44, December 1997:2252-2261.
[26] C.P.Yue, and S.S.Wong, IEEE Transactions of Solid-State Circuits, vol.33, no.5, May 1998: 145-148.
[27] P.T.Baine, D.L.Gay, B.M.Armstrong and H.S.Gamble,J.Electrochem. Soc, vol. 145, No.5, May 1998: 1738-1743.
[28] T.Ernst and S.Cristolovemeau, ECS SOI Technology and Devices Ⅸ, Seattle 1999
[29] Thomas Skotnicki, SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES, X.S.Cristoloveanu, RL.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 142.
[30] C.Fiegna, H.lwai, T.Saito, E.Sangiorgi, B.Ricco, A new scaling methodology for the 0.1-0.0025um MOSFET, Symp.VLSI Techn.Dig, 1993: 33-34.
[31] R.H.Yan, A.Ourmazd, K.F.Lee, Scaling the Si MOSFET: From Bulk to SOI to Bulk, IEEE Trans. Electron Devices, vol.39,no.7, 1992: 1704-1710.
[32] W.L.Goh, D.L.Gampbell, B.M.Armstrong, and H.S.Gamble, Proc.of the Third International Symposium on Semiconductor Wafer Bonding Science, Technology and Applications, The Electrochemical Society, Reno, May1995. vol. 95-7: 553-560.
[33] Philips and SOITEC, European Semiconductor, February 2002: 20.
[34] C.Serre, A.Pere-Rodriguez, A.Romano-Rodriguez, J.R.Morante, SILICON-ON-INSU LATOR TECHNOLOGY AND DEVICES X, S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K. Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 148.
[35] Gianni Taraschi, Zhi-Yuan Cheng, SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES,X. S.Cristoloveanu, P.L.F.Hemment, K.Izumi, G.K.Celler, F.Assaderaghi, Y.W.Kim, 2001-3: 46.
[36] 安正华，张苗，沈勤我，林成鲁，中国电子学会论文集，第十二届全国半导体集成电路／硅材料学术会论文集，2001．4，P348。