面向FPGA设计及应用的EDA关键技术研究
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摘要
在过去的半个世纪里，现场可编程门阵列FPGA逐渐成为数字电路实现的一种主流设计方法。与专用集成电路ASIC设计方法不同，FPGA设计有着可以避免一次性工程费用NRE以及上市时间短的优点，但是它所实现电路的规模、速度、和功耗受限于FPGA芯片本身，因而通常采用先进工艺和增加规模的方式弥补其与ASIC设计之间的差异。这些方法在带来性能提升的同时也对FPGA芯片的设计实现、制造和应用带来了新的挑战。因此，如何有效地设计实现FPGA芯片、改进芯片可制造性以及改善设计工具的使用体验成为了工业和学术界研究的热点。
本文从FPGA芯片的版图设计，可制造性设计和并行化布线三个方面进行了研究，通过对EDA关键技术的改进，改善了版图设计速度、可制造特性以及设计工具的使用体验。同时，本文采用测试电路实验分析和定量建模分析的手段对所做的改进进行了评估。本文的创新点如下：
1.针对FPGA芯片设计实现技术问题，本文改进了已有的FPGA版图自动生成流程，缩短了设计时间，节省了设计成本。经典的FPGA版图自动生成流程中，用于构建FPGA版图的基本单元是采用手工方式设计实现的，本文将基本单元的版图生成过程进行了自动化设计，并对小规模晶体管组的版图自动生成算法中的链接算法进行了改进，提出了基于子网络置换的链接算法，优化了单元级版图链接结果。
2.针对FPGA芯片可制造性设计问题，本文通过约束FPGA版图的样式来改进版图的可印刷特性，进而对芯片制造过程中的工艺偏差和失效率进行控制。定量分析显示在9%的面积开销下,本文所采用的规则化版图式样能够获得33%的工艺偏差改进和21.2%的失效率改进，如果还能允许有另外9%的面积开销，规则化版图将能够获得93.8%的工艺偏差缩减和16.2%的失效率改进。
3.针对FPGA布线算法优化问题，本文通过并行化方法对布线算法进行设计提速，提出了一种基于几何划分的并行化布线方法，其主要思想是对FPGA布线区域进行划分。不同划分内的信号线布线不存在数据相关，被分配到不同处理核中进行布线。现有并行布线算法在加速时会影响布线质量，而本文提出的布线算法能在获得较高布线加速的情况下不损失布线精度。
During the past50years, Filed-Programmable Gate Arrays (FPGAs) have becomeone of the most popular implementation media for digital circuits. Compared withApplication Specific Integrated Circuits (ASICs), FPGAs allow designers to achievelower Non-Recurring Engineering (NRE) costs and short time to markets for theirdesigns. But scale, speed and power of the designs implemented in FPGA are limited,So, FPGA can compete with ASIC by using newly developed technology and increasingsize. While, these methods not only enhance the performance but also increase thedesign, manufacture and application challenge for FPGA. So, how to efficientlyimplement FPGAs, improve the manufacturability and change the design experiencebecomes a hot topic in industry and academic.
In this paper, our researches mainly focus on the design, manufacturability anddesign tools. Through improving the Electronic Design Automation (EDA) algorithm,we optimized the FPGA implementation method and design tools. To verify ourimprovement, we involved the testbench analyzing method and modeling method. Wemade three innovations in this paper:
1. For the problem of FPGA chip implementation, we cut down the time for FPGAlayout design. Classic FPGA layout design automation flow is based on the manuallydesigned building cells, and we automated their layout design, with the keyimprovement of the chaining algorithm for the small transistor group layout automation.
2. For the manufacture problem of FPGA chip design, we improved the printabilityof FPGA chip by limiting the layout style which can also improve the process variationand Probability of Failure (PoF). Quantitative analysis shows that our new layout stylecan achieve33%variation improvement and21.2%PoF improvement with only9%area penalty, which could be potentially recovered by process window optimizationthanks to its superior printability.
3. For the problem of FPGA design tool optimization, we changed designer’s usingexperience through speeding up the compiling time of FPGA design, which indeedoptimized the application cost. After analyzing compile tool chain, we found thecompiling time could be shrinked through the parallelization of the routing algorithm.We proposed a parallel routing algorithm based on geometric partition. The algorithmpartitions the routing region into several parts, and the nets which belong to differentparts can be routed concurrently because there is no data dependency between them. So,our parallelization method can achieve good speedup without compromising the qualityof routing result.
本文从FPGA芯片的版图设计，可制造性设计和并行化布线三个方面进行了研究，通过对EDA关键技术的改进，改善了版图设计速度、可制造特性以及设计工具的使用体验。同时，本文采用测试电路实验分析和定量建模分析的手段对所做的改进进行了评估。本文的创新点如下：
1.针对FPGA芯片设计实现技术问题，本文改进了已有的FPGA版图自动生成流程，缩短了设计时间，节省了设计成本。经典的FPGA版图自动生成流程中，用于构建FPGA版图的基本单元是采用手工方式设计实现的，本文将基本单元的版图生成过程进行了自动化设计，并对小规模晶体管组的版图自动生成算法中的链接算法进行了改进，提出了基于子网络置换的链接算法，优化了单元级版图链接结果。
2.针对FPGA芯片可制造性设计问题，本文通过约束FPGA版图的样式来改进版图的可印刷特性，进而对芯片制造过程中的工艺偏差和失效率进行控制。定量分析显示在9%的面积开销下,本文所采用的规则化版图式样能够获得33%的工艺偏差改进和21.2%的失效率改进，如果还能允许有另外9%的面积开销，规则化版图将能够获得93.8%的工艺偏差缩减和16.2%的失效率改进。
3.针对FPGA布线算法优化问题，本文通过并行化方法对布线算法进行设计提速，提出了一种基于几何划分的并行化布线方法，其主要思想是对FPGA布线区域进行划分。不同划分内的信号线布线不存在数据相关，被分配到不同处理核中进行布线。现有并行布线算法在加速时会影响布线质量，而本文提出的布线算法能在获得较高布线加速的情况下不损失布线精度。
During the past50years, Filed-Programmable Gate Arrays (FPGAs) have becomeone of the most popular implementation media for digital circuits. Compared withApplication Specific Integrated Circuits (ASICs), FPGAs allow designers to achievelower Non-Recurring Engineering (NRE) costs and short time to markets for theirdesigns. But scale, speed and power of the designs implemented in FPGA are limited,So, FPGA can compete with ASIC by using newly developed technology and increasingsize. While, these methods not only enhance the performance but also increase thedesign, manufacture and application challenge for FPGA. So, how to efficientlyimplement FPGAs, improve the manufacturability and change the design experiencebecomes a hot topic in industry and academic.
In this paper, our researches mainly focus on the design, manufacturability anddesign tools. Through improving the Electronic Design Automation (EDA) algorithm,we optimized the FPGA implementation method and design tools. To verify ourimprovement, we involved the testbench analyzing method and modeling method. Wemade three innovations in this paper:
1. For the problem of FPGA chip implementation, we cut down the time for FPGAlayout design. Classic FPGA layout design automation flow is based on the manuallydesigned building cells, and we automated their layout design, with the keyimprovement of the chaining algorithm for the small transistor group layout automation.
2. For the manufacture problem of FPGA chip design, we improved the printabilityof FPGA chip by limiting the layout style which can also improve the process variationand Probability of Failure (PoF). Quantitative analysis shows that our new layout stylecan achieve33%variation improvement and21.2%PoF improvement with only9%area penalty, which could be potentially recovered by process window optimizationthanks to its superior printability.
3. For the problem of FPGA design tool optimization, we changed designer’s usingexperience through speeding up the compiling time of FPGA design, which indeedoptimized the application cost. After analyzing compile tool chain, we found thecompiling time could be shrinked through the parallelization of the routing algorithm.We proposed a parallel routing algorithm based on geometric partition. The algorithmpartitions the routing region into several parts, and the nets which belong to differentparts can be routed concurrently because there is no data dependency between them. So,our parallelization method can achieve good speedup without compromising the qualityof routing result.
引文
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