新型ESD防护器件与电路的结构设计及特性分析
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摘要
随着半导体制造工艺的进步,器件的特征尺寸越来越小,静电放电(ESD, Electro-Static Discharge)已经成为集成电路中最重要的可靠性问题之一。许多应用成熟的ESD防护器件与电路结构的防护能力也不断地降低,因此,为了有效地提高纳米级集成电路中的ESD防护能力,改进与设计新型的ESD防护器件与电路结构就显得尤为重要了。
在对现有ESD防护研究的基础上,本论文重点对新型ESD防护器件与电路结构进行了较深入地研究。首先详细阐述了闩锁效应的理论模型,这将为最新出现的系统级ESD防护和可控硅(SCR, Silicon Controlled Rectifier)器件结构统一理论提供理论支持,同时也据此得出了更全面的预防闩锁效应防护措施。接着对最新出现的系统级ESD防护进行了系统分析,根据系统级ESD失效机理,提出了软硬件协同设计的解决方案并有效地解决系统级ESD失效引起的闩锁效应。最后介绍分析了不同ESD箝位电路对系统级ESD的免疫能力,同时给出了能有效改善箝位电路的抗系统级ESD防护能力的新电路结构。
新型ESD防护器件方面,本论文重点研究了各种SCR器件,通过分析其基本结构,得出了SCR器件理论模型,从理论上系统地指导研究SCR器件的工作特性。通过对比各种不同的SCR器件结构,提出了SCR类器件的统一模块形式,并创新性提出了SCR类器件的标准模块化设计工程理论。通过分析T、M模块的功能,指导了ESD器件防护研究者如何根据不同的需求设计出新的SCR器件。最后创新性地设计与分析了新型SCR器件—DBTSCR,它不仅具有SCR类器件的共同优点,还具有触发电压动态可调的优良特性,并且寄生电容小,反应速度快,以及抗闩锁能力强的优点。该器件在高速及射频集成电路中的ESD防护有广泛的应用前景。
新型ESD防护电路方面,本论文着重研究了ESD箝位电路。首先详细介绍了箝位电路的设计准则,并通过分析箝位电路的结构,创新性地提出了新型ESD防护箝位电路。该ESD电源箝位电路,利用具有良好特性、边沿触发的动态TSPCL D触发器,进行检测、延迟,能有效解决电源快速上拉误触发问题,同时具有电源噪声免疫能力。该新型电路结构,不仅具有低功耗、低成本的优点,还普遍适用于不同工艺条件下(包括纳米级)的集成电路。研究与验证结果表明,该电路特别适合于高速集成电路中的ESD防护。
With the development of semiconductor manufacturing process, device feature size is scaled down constantly. ESD (Electro-static Discharge) has become one of the most important reliability problems in IC (Integrated Circuit). Many ESD protection devices and circuits are no longer widely used in nanometer-scale ESD protection application. Therefore, in order to improve the ESD protection ability effectively, analysis and design of novel structure of ESD protection device and circuit become more important.
Based on the current study of ESD protection, an in-depth research about the novel structure of ESD protection device and circuit is proposed in this paper. Firstly, a detailed theoretical model of latch-up effect is presented, which not only provides theoretical support for the latest system-level ESD protection and the unified theory of SCR device structure, but also acquires more comprehensive protective measures in case of latch-up. Secondly, the latest system-level ESD protection were analyzed, According to system-level ESD failure mechanism, a hardware and software co-design solution is proposed, which can effectively solve the system-level ESD failures due to latch-up effect. Finally, by analyzing the different system-level ESD immunity for clamp circuits, a new structure modified circuit is proposed to effectively improve the system-level ESD protection capability.
For novel ESD protection device, this paper focuses on a variety of SCR devices, through theoretical analysis of the basic structure of the SCR device, a basic SCR device theory model is presented, which guides the research of SCR device characteristics. By comparing with many types of SCR devices structure, this paper obtains a unified SCR devices module and has put forward an innovative standard modular design engineering theory of SCR type devices. By analyzing the T and M module’s features, this theory guides the ESD protection device design engineer how to design the new SCR devices according to the different needs. Finally an innovative design and analysis of a novel SCR device-DBTSCR is presented, which not only has the common advantages of SCR device, but also has excellent characteristics, such as dynamic adjustable trigger voltage, smaller parasitic capacitance, fast reaction speed, and excellent immunity of latch-up. This device has a wide range of application prospect in high-speed and RF integrated circuits for ESD protection.
For novel ESD protection circuit, this paper focused on studying ESD clamp circuit. First of all, a detailed design guideline of clamp circuit is given. Then, by analyzing the whole structure, a novel innovative ESD protection clamp circuit is proposed, which adopts rising-edge triggering TSPCL D flip-flop to turn on and time delay. The novel structure prevents false triggering even if it is applied in the faster power events. It also has excellent immunity to power noise. The novel circuit not only has the advantages of low power and low cost. But also can be applied in different process conditions (including nanometer) of integrated circuit. Research and verification results show that the circuit is particularly suitable for the ESD protection in high-speed integrated circuits.
在对现有ESD防护研究的基础上,本论文重点对新型ESD防护器件与电路结构进行了较深入地研究。首先详细阐述了闩锁效应的理论模型,这将为最新出现的系统级ESD防护和可控硅(SCR, Silicon Controlled Rectifier)器件结构统一理论提供理论支持,同时也据此得出了更全面的预防闩锁效应防护措施。接着对最新出现的系统级ESD防护进行了系统分析,根据系统级ESD失效机理,提出了软硬件协同设计的解决方案并有效地解决系统级ESD失效引起的闩锁效应。最后介绍分析了不同ESD箝位电路对系统级ESD的免疫能力,同时给出了能有效改善箝位电路的抗系统级ESD防护能力的新电路结构。
新型ESD防护器件方面,本论文重点研究了各种SCR器件,通过分析其基本结构,得出了SCR器件理论模型,从理论上系统地指导研究SCR器件的工作特性。通过对比各种不同的SCR器件结构,提出了SCR类器件的统一模块形式,并创新性提出了SCR类器件的标准模块化设计工程理论。通过分析T、M模块的功能,指导了ESD器件防护研究者如何根据不同的需求设计出新的SCR器件。最后创新性地设计与分析了新型SCR器件—DBTSCR,它不仅具有SCR类器件的共同优点,还具有触发电压动态可调的优良特性,并且寄生电容小,反应速度快,以及抗闩锁能力强的优点。该器件在高速及射频集成电路中的ESD防护有广泛的应用前景。
新型ESD防护电路方面,本论文着重研究了ESD箝位电路。首先详细介绍了箝位电路的设计准则,并通过分析箝位电路的结构,创新性地提出了新型ESD防护箝位电路。该ESD电源箝位电路,利用具有良好特性、边沿触发的动态TSPCL D触发器,进行检测、延迟,能有效解决电源快速上拉误触发问题,同时具有电源噪声免疫能力。该新型电路结构,不仅具有低功耗、低成本的优点,还普遍适用于不同工艺条件下(包括纳米级)的集成电路。研究与验证结果表明,该电路特别适合于高速集成电路中的ESD防护。
With the development of semiconductor manufacturing process, device feature size is scaled down constantly. ESD (Electro-static Discharge) has become one of the most important reliability problems in IC (Integrated Circuit). Many ESD protection devices and circuits are no longer widely used in nanometer-scale ESD protection application. Therefore, in order to improve the ESD protection ability effectively, analysis and design of novel structure of ESD protection device and circuit become more important.
Based on the current study of ESD protection, an in-depth research about the novel structure of ESD protection device and circuit is proposed in this paper. Firstly, a detailed theoretical model of latch-up effect is presented, which not only provides theoretical support for the latest system-level ESD protection and the unified theory of SCR device structure, but also acquires more comprehensive protective measures in case of latch-up. Secondly, the latest system-level ESD protection were analyzed, According to system-level ESD failure mechanism, a hardware and software co-design solution is proposed, which can effectively solve the system-level ESD failures due to latch-up effect. Finally, by analyzing the different system-level ESD immunity for clamp circuits, a new structure modified circuit is proposed to effectively improve the system-level ESD protection capability.
For novel ESD protection device, this paper focuses on a variety of SCR devices, through theoretical analysis of the basic structure of the SCR device, a basic SCR device theory model is presented, which guides the research of SCR device characteristics. By comparing with many types of SCR devices structure, this paper obtains a unified SCR devices module and has put forward an innovative standard modular design engineering theory of SCR type devices. By analyzing the T and M module’s features, this theory guides the ESD protection device design engineer how to design the new SCR devices according to the different needs. Finally an innovative design and analysis of a novel SCR device-DBTSCR is presented, which not only has the common advantages of SCR device, but also has excellent characteristics, such as dynamic adjustable trigger voltage, smaller parasitic capacitance, fast reaction speed, and excellent immunity of latch-up. This device has a wide range of application prospect in high-speed and RF integrated circuits for ESD protection.
For novel ESD protection circuit, this paper focused on studying ESD clamp circuit. First of all, a detailed design guideline of clamp circuit is given. Then, by analyzing the whole structure, a novel innovative ESD protection clamp circuit is proposed, which adopts rising-edge triggering TSPCL D flip-flop to turn on and time delay. The novel structure prevents false triggering even if it is applied in the faster power events. It also has excellent immunity to power noise. The novel circuit not only has the advantages of low power and low cost. But also can be applied in different process conditions (including nanometer) of integrated circuit. Research and verification results show that the circuit is particularly suitable for the ESD protection in high-speed integrated circuits.
引文
[1] GlennWagner, R., Soden, J.M., and Hawkins, C.F., Extent and Cost of EOS/ESD Damage in an IC Manufacturing Process, Proc. EOS/ESD symp.,1993, pp.49-55.
[2] J. B. Huang and G. Wang. ESD protection design for advanced CMOS.SPIE proceedings series, Nanjing, 2001: 123-131.
[3] A. Ortiz-Conde, F. J. Carcia-Sanchez, J. Muci. A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs. Electron Devices, IEEE Transactions on, 2007, vol. 54, pp.131-140.
[4] R. L. Minear and G. A. Dodson. Effects of Electrostatic Discharge on Linear Bipolar Integrated Circuits. Reliability Physics Symposium, 1977.15th Annual, pp.138-143.
[5] J. J. Liou, J. A. Salcedo, and Z. Liu. Robust ESD Protection Solutions in CMOS/BiCMOS Technologies. Electron Devices and Semiconductor Technology. Proceeding of 2007 International Workshop on, 2007, pp. 138-143.
[6] C. Duvvury. ESD On-chip Protection in Advanced Technologies, Tutorial in EOS/ESD Symp. 2003.
[7] M-D Ker. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Transaction on Electronic Devices. 1999, 46(1). 173-183.
[8] M-D Ker, W-J Chang. ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers. IEEE Solid-State Circuit. 2008, 55(6). 1409-1416.
[9] C Diaz, S-M Kang, C Duvvury. Tutorial electrical overstress and Electrostatic discharge. IEEE Trans. Reliability. 1995, Vol. 44. 2-5.
[10] S-U Kim. ESD induced gate oxide damage during wafer fabrication process. Proc. EOS/ESD Symp. 1992, 99-105.
[11] E-R Knight, P-P Budenstein. Effect of junction spikes and doping level on the second breakdown susceptibility of silicon-on-sapphire diodes. Proceedings of the second EOS/ESD Symposium. 1980, 122-129.
[12] MIL-STD-883E. Method 3015.7. Electrostatic Discharge Sensitivity Classification. Dept of Defence, Test Method Standard, Microcircuits. 1989.
[13] EIAJ-Standard. IC-121-1988. Testing Method 20: Electrostatic Discharge Test. AEC-Q100-03 Rev E. 2001.
[14] P. Bossard, R Chemlli and B. Unger. ESD damage from Triboelectrically Charge IC Pins. Proc. EOS/ESD Symp. 1980. 17-22.
[15] ESD Association. ESD STM5.3.1-1999: Standard Test Method for Electrostatic Discharge Sensitivity Testing-Charged Device Model (CDM) Component Level. 1999.
[16] EDEC Solid State Technology Association. JESD22-C101-A:Field-induced Charged Device Model Test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components. 2000.
[17] Automotive Electronics Council. Charged Device Model Electrostatic Discharge Test. AEC-Q100-011 Rev A. 2001.
[18] Morris, Wesley. Latch-up in CMOS. IEEE IRPS 2003: 76-84.
[19] R. R. Troutman and H. P. Zappe. A Transient Analysis of Latch-up in Bulk CMOS. IEEE Trans. Electron Devices. 1983, vol. 30, pp. 170–179.
[20] K. Y. Fu. Transient Latch-up in Bulk CMOS with a Voltage-dependent Well-substrate Junction Capacitance. IEEE Trans. Electron Devices, 1985, vol. 32, pp. 717–720.
[21] E. Hamdy and A. Mohsen. Characterization and modeling of transient latch-up in CMOS technology. IEDM Tech. Dig., 1983, pp. 172–175.
[22] G. Goto, H. Takahashi, and T. Nakamura. Latch-up immunity against noise pulses in a CMOS double well structure. IEDM Tech. Dig., 1983, pp. 168–171.
[23] S. Bargst?td-Franke, W. Stadler, K. Esmark, M. Streibl. Transient latch-up: experimental analysis and device simulation. Proc. EOS/ESD Symp., 2003, pp. 70-78
[24] ANSI/ESD SP5.4-2004: Transient Latch-up Testing―Component Level Supply Transient Stimulation, 2004. ESD Association Standard Practice.
[25] K. Chatty, P. Cottrell, R. Gauthier. Model-based guidelines to suppress cable discharge event (CDE) induced latch-up in CMOS ICs. Proc. IRPS, 2004, pp. 130–134
[26] M. D. Ker and S. F. Hsu. Transient-induced latch-up in CMOS technology: physical mechanism and device simulation. IEDM Tech. Dig., 2004, pp. 937–940.
[27] M. D. Ker and S. F. Hsu. Physical mechanism and device simulation on transient-induced latch-up in CMOS ICs under system-level ESD test. IEEE Trans. Electron Devices. 2005,vol. 52, no. 8, pp. 1821–1831.
[28] IEC 61000-4-2 Standard. EMC– Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test. IEC, 2001.
[29] M. D. Ker and S. F. Hsu. Evaluation on board-level noise filter networks to suppress transient-induced latch-up in CMOS ICs under system-level ESD test. IEEE Trans. on Electromagnetic Compatibility. 2006, vol. 48, no. 1, pp. 161–171.
[30] C. C. Yen. M. D. Ker. P. C. Shih. On-Chip Transient Detection Circuit for System Level ESD Protection in CMOS ICs. IEEE 2006 Custom Integrated Circuits Conference. 2006, pp361–364
[31] Ming-Dou Ker, Cheng-Cheng Yen. Investigation and design of on-chip power-rail ESD clamp circuits without suffering latch-up-like failure during system-level ESD test. IEEE Journal of solid-state circuits. 2008, 43(11):2533-2545
[32] Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang. Complementary-LVTSCR ESD Protection Circuit for Submicron CMOS VLSI/ULSI. IEEE Transactions on Electron Devices, 1996, Vol.43, pp588-598
[33] M. P. J. Mergens, C. C. Russ, K. G. Verhaege, J. Armer, P. C. Jozwiak, R. Mohn, High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC operation. Proc EOS/ESD Symp, 2002, pp. 14-21
[34] C. Russ et al. GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes. EOS/ESD Symp, 2001, pp. 22
[35] Markus P. J. Mergens, Olivier Marichal, Steven Thijs. Advanced SCR ESD Protection Circuit for CMOS/SOI Nanotechnologies. IEEE 2005 Custom Integrated Circuits Conference. 2005, pp.481-488
[36] M. Mergens et al. Speed Optimized Diode-Triggered SCR (DTSCR) for RF-ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies. IEEE Transactions on Device and Materials Reliability. 2005, Vol. 5, pp.532-542
[37] Ming-Dou Ker, Kuo-Chun Hsu. Substrate-Triggered SCR Device for On-Chip ESD Protection in Fully Silicided Sub-0.25-μm CMOS Process. IEEE Transactions on Electron Devices. 2003, Vol. 50, pp. 397-405
[38] Ming-Dou Ker, Zi-Ping Chen. SCR Device with Dynamic Holding Voltage for On-chip ESD Protection in a 0.25-μm Fully Salicided CMOS Process. IEEE Transactions on Electron Devices. 2005, Vol.51, pp. 1731-1733
[39] S. Voldman. ESD Circuits and Devices. John Wiley & Sons. 2006, pp. 241-275
[40] Ming-Dou Ker. Whole-chip ESD protection design with efficient VDD to VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Transactions on electron devices, 1999, 46 (1) :173–183
[41] S. S. Poon, Timothy. J. Maloney. New considerations for MOSFET power clamps. Microelectronics Reliability,2003,43: 987–991
[42] Jeremy C. Smith, Gianluca Boselli. A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. Microelectronics Reliability, 2005,45:201–210
[43] H,Sarbishaei,O.Semenov, M.Sachdev. A transient power supply ESD clamp with CMOS thyristor delay element. Proceeding of in the EOS/ESD Symposium, Anaheim, 2007:396-402
[44] Shih-Hung Chen, Ming-Dou Ker. Optimization on NMOS-Based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13μm CMOS technology. Proceedings of IEEE international conference on electronics, circuits and systems, ICECS, St.Julian’s, 2008:666-669
[45] Mohamed Elgamel, Tarek Darwish. Noise tolerant low power dynamic TSPCL D Flip-Flops. Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002:80-85
[46] R. Merrill and E. Issaq. ESD design methodology. Proceeding of the EOS/ESD Symposium. 1993:223–237.
[47] M. Stockinger, J.W. Miller, M. G. Khazhinsky. Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies. EOS/ESD Symposium. 2003:17–26
[48] Jan M. Rabaey, Anantha Chandrakasan. Digital integrated circuits: A design perspective. Second Editon. Beijing: Publishing House of Electronics Industry 2003:252-258
[49] Ming-Dou Ker, and Yu-Yu. Sung. Hardware/firmware co-design in a 8-bits microcontroller to solve the system-level ESD issue on keyboard. Microelectronic Reliability 2001,41(3): 417-429
[50] Cheng-Cheng Yen, Ming-Dou Ker. The effect of IEC-like fast transients on RC-triggered ESD power clamps. IEEE Transactions on electron devices. 2009,56(6):1204-1210
[2] J. B. Huang and G. Wang. ESD protection design for advanced CMOS.SPIE proceedings series, Nanjing, 2001: 123-131.
[3] A. Ortiz-Conde, F. J. Carcia-Sanchez, J. Muci. A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs. Electron Devices, IEEE Transactions on, 2007, vol. 54, pp.131-140.
[4] R. L. Minear and G. A. Dodson. Effects of Electrostatic Discharge on Linear Bipolar Integrated Circuits. Reliability Physics Symposium, 1977.15th Annual, pp.138-143.
[5] J. J. Liou, J. A. Salcedo, and Z. Liu. Robust ESD Protection Solutions in CMOS/BiCMOS Technologies. Electron Devices and Semiconductor Technology. Proceeding of 2007 International Workshop on, 2007, pp. 138-143.
[6] C. Duvvury. ESD On-chip Protection in Advanced Technologies, Tutorial in EOS/ESD Symp. 2003.
[7] M-D Ker. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Transaction on Electronic Devices. 1999, 46(1). 173-183.
[8] M-D Ker, W-J Chang. ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers. IEEE Solid-State Circuit. 2008, 55(6). 1409-1416.
[9] C Diaz, S-M Kang, C Duvvury. Tutorial electrical overstress and Electrostatic discharge. IEEE Trans. Reliability. 1995, Vol. 44. 2-5.
[10] S-U Kim. ESD induced gate oxide damage during wafer fabrication process. Proc. EOS/ESD Symp. 1992, 99-105.
[11] E-R Knight, P-P Budenstein. Effect of junction spikes and doping level on the second breakdown susceptibility of silicon-on-sapphire diodes. Proceedings of the second EOS/ESD Symposium. 1980, 122-129.
[12] MIL-STD-883E. Method 3015.7. Electrostatic Discharge Sensitivity Classification. Dept of Defence, Test Method Standard, Microcircuits. 1989.
[13] EIAJ-Standard. IC-121-1988. Testing Method 20: Electrostatic Discharge Test. AEC-Q100-03 Rev E. 2001.
[14] P. Bossard, R Chemlli and B. Unger. ESD damage from Triboelectrically Charge IC Pins. Proc. EOS/ESD Symp. 1980. 17-22.
[15] ESD Association. ESD STM5.3.1-1999: Standard Test Method for Electrostatic Discharge Sensitivity Testing-Charged Device Model (CDM) Component Level. 1999.
[16] EDEC Solid State Technology Association. JESD22-C101-A:Field-induced Charged Device Model Test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components. 2000.
[17] Automotive Electronics Council. Charged Device Model Electrostatic Discharge Test. AEC-Q100-011 Rev A. 2001.
[18] Morris, Wesley. Latch-up in CMOS. IEEE IRPS 2003: 76-84.
[19] R. R. Troutman and H. P. Zappe. A Transient Analysis of Latch-up in Bulk CMOS. IEEE Trans. Electron Devices. 1983, vol. 30, pp. 170–179.
[20] K. Y. Fu. Transient Latch-up in Bulk CMOS with a Voltage-dependent Well-substrate Junction Capacitance. IEEE Trans. Electron Devices, 1985, vol. 32, pp. 717–720.
[21] E. Hamdy and A. Mohsen. Characterization and modeling of transient latch-up in CMOS technology. IEDM Tech. Dig., 1983, pp. 172–175.
[22] G. Goto, H. Takahashi, and T. Nakamura. Latch-up immunity against noise pulses in a CMOS double well structure. IEDM Tech. Dig., 1983, pp. 168–171.
[23] S. Bargst?td-Franke, W. Stadler, K. Esmark, M. Streibl. Transient latch-up: experimental analysis and device simulation. Proc. EOS/ESD Symp., 2003, pp. 70-78
[24] ANSI/ESD SP5.4-2004: Transient Latch-up Testing―Component Level Supply Transient Stimulation, 2004. ESD Association Standard Practice.
[25] K. Chatty, P. Cottrell, R. Gauthier. Model-based guidelines to suppress cable discharge event (CDE) induced latch-up in CMOS ICs. Proc. IRPS, 2004, pp. 130–134
[26] M. D. Ker and S. F. Hsu. Transient-induced latch-up in CMOS technology: physical mechanism and device simulation. IEDM Tech. Dig., 2004, pp. 937–940.
[27] M. D. Ker and S. F. Hsu. Physical mechanism and device simulation on transient-induced latch-up in CMOS ICs under system-level ESD test. IEEE Trans. Electron Devices. 2005,vol. 52, no. 8, pp. 1821–1831.
[28] IEC 61000-4-2 Standard. EMC– Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test. IEC, 2001.
[29] M. D. Ker and S. F. Hsu. Evaluation on board-level noise filter networks to suppress transient-induced latch-up in CMOS ICs under system-level ESD test. IEEE Trans. on Electromagnetic Compatibility. 2006, vol. 48, no. 1, pp. 161–171.
[30] C. C. Yen. M. D. Ker. P. C. Shih. On-Chip Transient Detection Circuit for System Level ESD Protection in CMOS ICs. IEEE 2006 Custom Integrated Circuits Conference. 2006, pp361–364
[31] Ming-Dou Ker, Cheng-Cheng Yen. Investigation and design of on-chip power-rail ESD clamp circuits without suffering latch-up-like failure during system-level ESD test. IEEE Journal of solid-state circuits. 2008, 43(11):2533-2545
[32] Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang. Complementary-LVTSCR ESD Protection Circuit for Submicron CMOS VLSI/ULSI. IEEE Transactions on Electron Devices, 1996, Vol.43, pp588-598
[33] M. P. J. Mergens, C. C. Russ, K. G. Verhaege, J. Armer, P. C. Jozwiak, R. Mohn, High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC operation. Proc EOS/ESD Symp, 2002, pp. 14-21
[34] C. Russ et al. GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes. EOS/ESD Symp, 2001, pp. 22
[35] Markus P. J. Mergens, Olivier Marichal, Steven Thijs. Advanced SCR ESD Protection Circuit for CMOS/SOI Nanotechnologies. IEEE 2005 Custom Integrated Circuits Conference. 2005, pp.481-488
[36] M. Mergens et al. Speed Optimized Diode-Triggered SCR (DTSCR) for RF-ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies. IEEE Transactions on Device and Materials Reliability. 2005, Vol. 5, pp.532-542
[37] Ming-Dou Ker, Kuo-Chun Hsu. Substrate-Triggered SCR Device for On-Chip ESD Protection in Fully Silicided Sub-0.25-μm CMOS Process. IEEE Transactions on Electron Devices. 2003, Vol. 50, pp. 397-405
[38] Ming-Dou Ker, Zi-Ping Chen. SCR Device with Dynamic Holding Voltage for On-chip ESD Protection in a 0.25-μm Fully Salicided CMOS Process. IEEE Transactions on Electron Devices. 2005, Vol.51, pp. 1731-1733
[39] S. Voldman. ESD Circuits and Devices. John Wiley & Sons. 2006, pp. 241-275
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