多晶硅薄膜晶体管的衬底端表征方法研究
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摘要
多晶硅薄膜晶体管(TFT: Thin Film Transistor)在液晶显示中的广泛应用,使其越来越受到重视。但是,目前多晶硅TFT的表征方法还主要集中在源漏端和栅极端。本文成功将通用的MOSFET的衬底端表征方法——电荷泵技术(CP: Charge Pumping)和衬底电流(Isub)引入到多晶硅TFT的研究中。
首先,通过调整栅脉冲的上升沿和下降沿时间的方式首次消除了CP电流(Icp)中的几何因素,从而达到优化CP的目的。采用优化的CP,在多晶硅TFT中获得了和MOSFET中类似的帽子型Elliot曲线。然后,基于通用的CP模型,建立了TFT中Elliot曲线的模型。另外,利用优化的CP获得了缺陷态密度(Dt: Trap Density)的典型能级分布,并用多种方法可靠地提取了Dt的平均值。更进一步,首次提出了一种能够自动规避几何效应影响的新型Dt提取方法。另外,还利用CP研究了TFT的退化。
另一方面,本文首次研究了多晶硅TFT中的Isub。当衬底偏压(Vsub)较小时,Isub来源于发生在沟道内的复合过程,因而和Dt直接相关。并且,在Vg的调控下,复合区可以从整个沟道变化到靠近源漏端或者衬底端附近的局部区域。基于Isub的这种机制,建立了Isub-Vg曲线的模型。最后,利用Isub-Vg曲线精确地探测了热载流子应力造成的损伤区的位置及其内部的Dt的变化。
As polysilicon thin film transistors (TFTs) have been widely used in liquid crystal display, it becomes more and more important to study polysilicon TFTs. However, up to the present, the evaluation approaches in polysilicon TFTs are mainly at the source and drain terminals. In this paper, as general approaches at substrate terminal in MOSFETs, the charge pumping (CP) and substrate current (Isub) are applied to polysilicon TFTs.
At first, CP is firstly optimized by adjusting the gate pulse transition times to eliminate the geometric component of the CP current (Icp). Improved Elliot curves similar to those in MOSFETs are obtained for polysilicon TFTs. Then, according to the general CP model, the model for Elliot curves of polysilicon TFTs is proposed. Besides, based on the improved CP, typical trap state density (Dt) energy distribution within upper part of the band-gap and mean Dt value ( Dt ) are reliably extracted in different approaches. Furthermore, a modified Dt extraction approach, where the influence of the CP geometric component is inherently avoided, is first proposed. In addition, CP is employed to investigate the degradation of TFTs.
On the other hand, Isub in polysilicon TFTs is first studied. When the substrate voltage (Vsub) is very small, Isub is found to be driven by the recombination process and therefore relevant to Dt. Furthermore, controlled by Vg, the recombination area can vary from the whole channel area to the local region near drain, source or substrate terminal. Based on the mechanism, the model for the Isub-Vg curve is built. Finally, the Isub-Vg curve is applied to sensitively locate the hot carrier damage region and detect the locally increased Dt in this area.
首先,通过调整栅脉冲的上升沿和下降沿时间的方式首次消除了CP电流(Icp)中的几何因素,从而达到优化CP的目的。采用优化的CP,在多晶硅TFT中获得了和MOSFET中类似的帽子型Elliot曲线。然后,基于通用的CP模型,建立了TFT中Elliot曲线的模型。另外,利用优化的CP获得了缺陷态密度(Dt: Trap Density)的典型能级分布,并用多种方法可靠地提取了Dt的平均值。更进一步,首次提出了一种能够自动规避几何效应影响的新型Dt提取方法。另外,还利用CP研究了TFT的退化。
另一方面,本文首次研究了多晶硅TFT中的Isub。当衬底偏压(Vsub)较小时,Isub来源于发生在沟道内的复合过程,因而和Dt直接相关。并且,在Vg的调控下,复合区可以从整个沟道变化到靠近源漏端或者衬底端附近的局部区域。基于Isub的这种机制,建立了Isub-Vg曲线的模型。最后,利用Isub-Vg曲线精确地探测了热载流子应力造成的损伤区的位置及其内部的Dt的变化。
As polysilicon thin film transistors (TFTs) have been widely used in liquid crystal display, it becomes more and more important to study polysilicon TFTs. However, up to the present, the evaluation approaches in polysilicon TFTs are mainly at the source and drain terminals. In this paper, as general approaches at substrate terminal in MOSFETs, the charge pumping (CP) and substrate current (Isub) are applied to polysilicon TFTs.
At first, CP is firstly optimized by adjusting the gate pulse transition times to eliminate the geometric component of the CP current (Icp). Improved Elliot curves similar to those in MOSFETs are obtained for polysilicon TFTs. Then, according to the general CP model, the model for Elliot curves of polysilicon TFTs is proposed. Besides, based on the improved CP, typical trap state density (Dt) energy distribution within upper part of the band-gap and mean Dt value ( Dt ) are reliably extracted in different approaches. Furthermore, a modified Dt extraction approach, where the influence of the CP geometric component is inherently avoided, is first proposed. In addition, CP is employed to investigate the degradation of TFTs.
On the other hand, Isub in polysilicon TFTs is first studied. When the substrate voltage (Vsub) is very small, Isub is found to be driven by the recombination process and therefore relevant to Dt. Furthermore, controlled by Vg, the recombination area can vary from the whole channel area to the local region near drain, source or substrate terminal. Based on the mechanism, the model for the Isub-Vg curve is built. Finally, the Isub-Vg curve is applied to sensitively locate the hot carrier damage region and detect the locally increased Dt in this area.
引文
[1] S.D. Brotherton, Polycrystalline silicon thin film transistors, Semicond. Sci. Technol., 1995, vol.10, no. 6, pp.721-738.
[2] Zhiguo Meng, Cathy Li, Hoi S. Kwok, Man Wong, Application of Re-Crystallized Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistor Technology to Reflective Liquid-Crystal Display, Journal of the Society for Information Display, 2001, vol. 9, no. 4, pp.319-323.
[3] Zhiguo Meng and Man Wong, Active-Matrix Organic Light-Emitting Diode Displays Realized Using Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistors, IEEE Transactions on Electron Devices, 2002, vol. 49, no. 6, pp.991-996.
[4]张明杰,李继东,陈建设,太阳能电池及多晶硅的生产,材料与冶金学报,2007,vol.6,no.1,33-38。
[5] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[6] D. Bauza, Rigorguos Analysis of Two-Level Charge Pumping: Application to theExtraction of Interface Trap Concentration Versus Energy Profiles in Metal-Oxide-Semiconductor Transistor, Journal of Applied Physics, 2003, vol.94, pp.3229-3248.
[7] D. Bauza, A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms, IEEE Transactions on Electron Devices, 2009, vol. 56, pp. 70-77.
[8] P. Heremans, J. Witters, G. Groeseneken and H.E. Maes, Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation, IEEE Transactions on Electron Devices, 1989, vol. 36, pp. 1381-1395.
[9] C. Bergonzoni, G.D. Libera, Physical Characterization of Hot-Electron-Induced MOSFET Degradation Through an Improved Approach to the Charge-Puming Technique, IEEE Transactions on Electron Devices, 1992, vol.39, pp.1895-1901.
[10] CHENMING HU, SIMON C. TAM, FU CHIEH HSU, PING KEUNG KO, TUNG YI CHAN, KYLE W. TERRILL, Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement, IEEE Transactions on Electron Devices, 1985, vol. ED-32, pp. 375-385.
[11] Heng-Sheng Huang, Mu-Chun Wang, Zhen-Ying Hsieh, Shuang-Yuan Chen, Ai-Erh Chuang, Chuan-Hsi Liu, Substrate current verifying lateral electrical field under forward substrate biases for nMOSFETs, Solid-State Electronics, 2010.
[12] Yamauchi. Noriyoshi, Reif. Rafael, Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications, Journal of Applied Physics, 1994, vol. 75, no. 7, pp. 3235-57
[13] Kubo. Nobuo, Kusumoto. Naoto, Inushima. Takashi, Yamazaki. Shumpei, Characteristics of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method, IEEE Transactions on Electron Devices, 1994, vol. 41, no. 10, pp. 1876-1879.
[14] T. YOSHIDA, Y. EBIKO, M. TAKEI, N. SASAKI, T. TSUCHIYA, Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film Transistors, 2003, Journal of Applied Physics, vol. 42, pp.1993-2003.
[15] F.V. Farmakis, J. Brini, G.Kamarinos, C.T .Angelis, C.A. Dimitriadis, M. Miyasaka, T. Ouisse, Grain and grain-boundary control of the transfer characteristics of large-grain polycrystalline silicon thin-film transistors, Solid-State Electronics, 2000,vol. 44, pp. 913-16.
[16] Man Wong, Hoi S. Kwok, High-performance polycrystalline silicon thin-film transistor technology using low-temperature metal-induced unilateral crystallization, Microelectronics Journal, 2004, vol. 35, pp. 337-341.
[17] Seok-Woon Lee, Seung-Ki Joo, Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization IEEE ELECTRON DEVICE Letter, 1996, vol.17, no. 4, pp.160-162.
[18] Bo Zhang, Zhiguo Meng, Shuyun Zhao, Man Wong and Hoi-Sing Kwok,“Poly silicon thin-film transistors with uniform and reliable performance using solution-based metal-induced crystallization,”IEEE Transactions on Electron Devices, 2007, vol. 54, pp. 1244-1248.
[1] E.H. Poindexter, Mos Interface States: Overview and Physicochemical Perspective, Semicond. Sci. Technol., 1989, vol.4, pp.961-969.
[2] A. Neugroschel, C.T. Sah, M. Han, M.S. Carroll, T. Nishida, J.T. Kavalieros and Y. Lu, Direct-Current Measurements of Oxide and Interface Traps on Oxidized Silicon, Appl. Phys. Lett., 1995, vol. 42, pp.1657-1662.
[3] N. Saks, Comparison of Interface Trap Densities Measured by the Jenq and Charge Pumping, Journal of Applied Physics, 1993, vol. 74, pp.3303-3306.
[4] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[5] D.Bauza, Rigorguos Analysis of Two-Level Charge Pumping: Application to the Extraction of Interface Trap Concentration Versus Energy Profiles in Metal-Oxide-Semiconductor Transistor, Journal of Applied Physics, 2003, vol.94, pp.3229-3248.
[6] D. Bauza,“A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms,”IEEE Trans. on Electron Devices, vol. 56, 2009, p. 70-77.
[7] Bauza D., A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms, IEEE Transactions on Electron Devices, 2009, vol. 56, pp. 70-77.
[8] P. Heremans, J. Witters, G. Groeseneken and H.E. Maes, Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation, IEEE Transactions on Electron Devices, 1989, vol. 36, pp. 1381-1395.
[9] Koyanagi M., Baba Y., Hata K., Wu I.-W., Lewis A.G., Fuse M. and Bruce R., The charge-pumping technique for grain boundary trap evaluation in polysilicon TFT, IEEE Electron Device Letters, 1992,vol. 13, pp. 152-154.
[10] Ga-Won Lee, Jin-Woo Lee and Chui-Hi Han, Substrate resistance effect on charge-pumping current in polycrystalline silicon thin film transistors, Japanese Journal of Applied Physics, 1999, vol. 38, pp. 2656-2659.
[11] Kee-Jong Kim and Ohyun Kim, Identification of grain-boundary trap properties using three-level charge-pumping technique in polysilicon thin-film transistors, Japanese Journal of Applied Physics, 1997, vol. 36, pp. 1394-1397.
[12] Saks N.S., Batra S. and Manning M., Charge pumping in thin film transistors, Microelectronic Engineering, 1995, vol. 28, pp. 379-382.
[13] Kee-Jong Kim, Won-Kyu Park, Seong-Gyun Kim, Keong-Mun Lim, In-Gon Lim and Ohyun Kim, A new charge pumping model considering bulk trap states in polysilicon thin film transistor, Solid-State Electronics, 1998, vol. 42, pp. 1897-1903.
[14] Kim Ohyun and Kim Klee-Jong, Charge pumping investigations on parasitic regions in polysilicon TFT, Electronics Letters, 1998, vol. 34, pp. 809-811.
[15] D.K. Schroder and J.A. Babcock, Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing, Journal of Applied Physics, 2003, vol. 94, pp. 1-18.
[16] A. Balasinski, J. Worley, M. Zamanian, and F. T. Liou, Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping, IEDM Tech. Dig., 1995, pp. 529–532.
[17] C. Y. Chen, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang and T. F. Lei, Analysis of negative bias temperature instability in bodytied low-temperature polycrystalline silicon thin-film transistors, IEEE Electron Device Letters, 2008, vol. 29, no. 2, pp. 165–167.
[18] G. Van den Bosch, G. Groeseneken, and H. E. Maes, On the geometric component of charge-pumping current in OSFETs, IEEE Electron Device Letters, 1993, vol. 14, no. 3, pp. 107–109.
[19] C.R. Viswanathan and Rao V. Ramgopal, Application of Charge pumping Technique for Sub-micron MOSFET Characterization, Microelectronic Engineering, 1998, vol. 40, n 3-4, pp. 131-46.
[20] T. Aichinger and M. Nelhiebel, Advanced energetic and lateral sensitive charge pumping profiling methods for MOSFET device characterization - analytical discussion and case studies, IEEE Transactions on Device and Materials Reliability,2008, vol. 8, pp. 509-518.
[21] Han Hao, Mingxiang Wang, Bo Zhang, Xuejie Shi, Man Wong, A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility, Journal of Applied Physics, 2008, vol. 103, p. 094513-1-10.
[22] Mark D. Jacunski, Michael S. Shur, Michael Hack, Threshold Voltage, Field Effect Mobility, and Gate-to-Channel Capacitance in Polysilicon TFT’s, IEEE Trans. on Electron Devices, vol. 43, 1996, p. 1433-1439.
[23] Huaisheng Wang, Mingxiang Wang, Zhenyu Yang and Han Hao, Stress Power Dependent Self-Heating Degradation of Metal Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin Film Transistors, IEEE Trans. on Electron Devices, 2007, vol.54, pp.3276-84.
[24] Min Xue, Mingxiang Wang, Zhen Zhu, Dongli Zhang and Man Wong, Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses, IEEE Trans. on Electron Devices, 2007, vol.54, pp.225-32.
[1] Hu C., Tam S.C., Hsu F.C., Ko P.K., Chan T.Y. and Terrill K.W., Hot-electron-induced MOSFET degradation-Model, monitor, and improvement, IEEE Trans. on Electron Devices, 1985, vol.32, pp.375-85.
[2] N.A. Hastas, Archontas N., Dimitriadis C. A., Kamarinos G., Nikolaidis T., Georgoulas N. and Thanailakis A, Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors, Microelectronics Reliability, 2005, vol.41, pp. 341-8.
[3] M. A. Kroon, Van Swaaij and R.A.C.M.M., Spatial effects on ideality factor of amorphous silicon pin diodes, Journal of Applied Physics, 2001, vol.90, pp. 994-1000.
[4] Mark Stewart and Miltiadis K. Hatalis, High performance gated lateral polysilicon PIN diodes, Solid-State Electron., 2000, vol.44, pp. 1613-9.
[5] Camara N., Bano E. and Zekentes K., Current transport mechanisms in 4H-SiC pin diodes, 2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003, vol. 2, pp. 249-52 .
[6] Ruzin A. And Marunko S., Current mechanisms in silicon PIN structures processed with various technologies, Nuclear Instruments & Methods in Physics Research, Section A (Accelerators, Spectrometers, Detectors and Associated Equipment), 2002, vol. 492, n 3, pp. 411-22.
[7] Badila M., Tudor B., Brezeanu G., Locatelli M.L., Chante J.P., Millan J., Godignon P.,Lebedev A. and Banu, V., Current-voltage characteristics of large area 6H-SiC pin diodes, Materials Science & Engineering B (Solid-State Materials for Advanced Technology), 1999, vol. B61-B62, pp. 433-6,.
[8] C. Van Berkel, Powell M.J., Franklin A.R. and French I.D., Quality factor in a-SiH nip and pin diodes, Journal of Applied Physics, 1993, vol.73, pp. 5264-8.
[9] Han Hao, Mingxiang Wang, Bo Zhang, Xuejie Shi, Man Wong, A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility, Journal of Applied Physics, 2008, vol. 103, pp. 094513-1-10.
[10] Min Xue, Mingxiang Wang, Zhen Zhu, Dongli Zhang and Man Wong, Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses, IEEE Trans. on Electron Devices, 2007, vol.54, pp.225-32.
[11] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[12] Lei LU, Mingxiang Wang and Man Wong, Geometric effect elimination and reliable trap state density extraction in charge pumping of polysilicon thin-film transistors, IEEE Electron Device Letters, 2009, vol.30, pp.517-9.
[13] Xiaowei Lu, Mingxiang WANG, Kai SUN, and Lei LU,Evaluation of Self-Heating and Hot Carrier Degradation of Poly-Si Thin-Film Transistors using Charge Pumping technique, IEEE International Reliability Physics Symposium, Montreal, Canada, 2010, pp. 1040-1043.
[2] Zhiguo Meng, Cathy Li, Hoi S. Kwok, Man Wong, Application of Re-Crystallized Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistor Technology to Reflective Liquid-Crystal Display, Journal of the Society for Information Display, 2001, vol. 9, no. 4, pp.319-323.
[3] Zhiguo Meng and Man Wong, Active-Matrix Organic Light-Emitting Diode Displays Realized Using Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistors, IEEE Transactions on Electron Devices, 2002, vol. 49, no. 6, pp.991-996.
[4]张明杰,李继东,陈建设,太阳能电池及多晶硅的生产,材料与冶金学报,2007,vol.6,no.1,33-38。
[5] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[6] D. Bauza, Rigorguos Analysis of Two-Level Charge Pumping: Application to theExtraction of Interface Trap Concentration Versus Energy Profiles in Metal-Oxide-Semiconductor Transistor, Journal of Applied Physics, 2003, vol.94, pp.3229-3248.
[7] D. Bauza, A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms, IEEE Transactions on Electron Devices, 2009, vol. 56, pp. 70-77.
[8] P. Heremans, J. Witters, G. Groeseneken and H.E. Maes, Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation, IEEE Transactions on Electron Devices, 1989, vol. 36, pp. 1381-1395.
[9] C. Bergonzoni, G.D. Libera, Physical Characterization of Hot-Electron-Induced MOSFET Degradation Through an Improved Approach to the Charge-Puming Technique, IEEE Transactions on Electron Devices, 1992, vol.39, pp.1895-1901.
[10] CHENMING HU, SIMON C. TAM, FU CHIEH HSU, PING KEUNG KO, TUNG YI CHAN, KYLE W. TERRILL, Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement, IEEE Transactions on Electron Devices, 1985, vol. ED-32, pp. 375-385.
[11] Heng-Sheng Huang, Mu-Chun Wang, Zhen-Ying Hsieh, Shuang-Yuan Chen, Ai-Erh Chuang, Chuan-Hsi Liu, Substrate current verifying lateral electrical field under forward substrate biases for nMOSFETs, Solid-State Electronics, 2010.
[12] Yamauchi. Noriyoshi, Reif. Rafael, Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications, Journal of Applied Physics, 1994, vol. 75, no. 7, pp. 3235-57
[13] Kubo. Nobuo, Kusumoto. Naoto, Inushima. Takashi, Yamazaki. Shumpei, Characteristics of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method, IEEE Transactions on Electron Devices, 1994, vol. 41, no. 10, pp. 1876-1879.
[14] T. YOSHIDA, Y. EBIKO, M. TAKEI, N. SASAKI, T. TSUCHIYA, Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film Transistors, 2003, Journal of Applied Physics, vol. 42, pp.1993-2003.
[15] F.V. Farmakis, J. Brini, G.Kamarinos, C.T .Angelis, C.A. Dimitriadis, M. Miyasaka, T. Ouisse, Grain and grain-boundary control of the transfer characteristics of large-grain polycrystalline silicon thin-film transistors, Solid-State Electronics, 2000,vol. 44, pp. 913-16.
[16] Man Wong, Hoi S. Kwok, High-performance polycrystalline silicon thin-film transistor technology using low-temperature metal-induced unilateral crystallization, Microelectronics Journal, 2004, vol. 35, pp. 337-341.
[17] Seok-Woon Lee, Seung-Ki Joo, Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization IEEE ELECTRON DEVICE Letter, 1996, vol.17, no. 4, pp.160-162.
[18] Bo Zhang, Zhiguo Meng, Shuyun Zhao, Man Wong and Hoi-Sing Kwok,“Poly silicon thin-film transistors with uniform and reliable performance using solution-based metal-induced crystallization,”IEEE Transactions on Electron Devices, 2007, vol. 54, pp. 1244-1248.
[1] E.H. Poindexter, Mos Interface States: Overview and Physicochemical Perspective, Semicond. Sci. Technol., 1989, vol.4, pp.961-969.
[2] A. Neugroschel, C.T. Sah, M. Han, M.S. Carroll, T. Nishida, J.T. Kavalieros and Y. Lu, Direct-Current Measurements of Oxide and Interface Traps on Oxidized Silicon, Appl. Phys. Lett., 1995, vol. 42, pp.1657-1662.
[3] N. Saks, Comparison of Interface Trap Densities Measured by the Jenq and Charge Pumping, Journal of Applied Physics, 1993, vol. 74, pp.3303-3306.
[4] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[5] D.Bauza, Rigorguos Analysis of Two-Level Charge Pumping: Application to the Extraction of Interface Trap Concentration Versus Energy Profiles in Metal-Oxide-Semiconductor Transistor, Journal of Applied Physics, 2003, vol.94, pp.3229-3248.
[6] D. Bauza,“A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms,”IEEE Trans. on Electron Devices, vol. 56, 2009, p. 70-77.
[7] Bauza D., A general and reliable model for charge pumping-Part I: model and basic charge-pumping mechanisms, IEEE Transactions on Electron Devices, 2009, vol. 56, pp. 70-77.
[8] P. Heremans, J. Witters, G. Groeseneken and H.E. Maes, Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation, IEEE Transactions on Electron Devices, 1989, vol. 36, pp. 1381-1395.
[9] Koyanagi M., Baba Y., Hata K., Wu I.-W., Lewis A.G., Fuse M. and Bruce R., The charge-pumping technique for grain boundary trap evaluation in polysilicon TFT, IEEE Electron Device Letters, 1992,vol. 13, pp. 152-154.
[10] Ga-Won Lee, Jin-Woo Lee and Chui-Hi Han, Substrate resistance effect on charge-pumping current in polycrystalline silicon thin film transistors, Japanese Journal of Applied Physics, 1999, vol. 38, pp. 2656-2659.
[11] Kee-Jong Kim and Ohyun Kim, Identification of grain-boundary trap properties using three-level charge-pumping technique in polysilicon thin-film transistors, Japanese Journal of Applied Physics, 1997, vol. 36, pp. 1394-1397.
[12] Saks N.S., Batra S. and Manning M., Charge pumping in thin film transistors, Microelectronic Engineering, 1995, vol. 28, pp. 379-382.
[13] Kee-Jong Kim, Won-Kyu Park, Seong-Gyun Kim, Keong-Mun Lim, In-Gon Lim and Ohyun Kim, A new charge pumping model considering bulk trap states in polysilicon thin film transistor, Solid-State Electronics, 1998, vol. 42, pp. 1897-1903.
[14] Kim Ohyun and Kim Klee-Jong, Charge pumping investigations on parasitic regions in polysilicon TFT, Electronics Letters, 1998, vol. 34, pp. 809-811.
[15] D.K. Schroder and J.A. Babcock, Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing, Journal of Applied Physics, 2003, vol. 94, pp. 1-18.
[16] A. Balasinski, J. Worley, M. Zamanian, and F. T. Liou, Reference voltages and their stress-induced changes in thin film transistors as determined by charge pumping, IEDM Tech. Dig., 1995, pp. 529–532.
[17] C. Y. Chen, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang and T. F. Lei, Analysis of negative bias temperature instability in bodytied low-temperature polycrystalline silicon thin-film transistors, IEEE Electron Device Letters, 2008, vol. 29, no. 2, pp. 165–167.
[18] G. Van den Bosch, G. Groeseneken, and H. E. Maes, On the geometric component of charge-pumping current in OSFETs, IEEE Electron Device Letters, 1993, vol. 14, no. 3, pp. 107–109.
[19] C.R. Viswanathan and Rao V. Ramgopal, Application of Charge pumping Technique for Sub-micron MOSFET Characterization, Microelectronic Engineering, 1998, vol. 40, n 3-4, pp. 131-46.
[20] T. Aichinger and M. Nelhiebel, Advanced energetic and lateral sensitive charge pumping profiling methods for MOSFET device characterization - analytical discussion and case studies, IEEE Transactions on Device and Materials Reliability,2008, vol. 8, pp. 509-518.
[21] Han Hao, Mingxiang Wang, Bo Zhang, Xuejie Shi, Man Wong, A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility, Journal of Applied Physics, 2008, vol. 103, p. 094513-1-10.
[22] Mark D. Jacunski, Michael S. Shur, Michael Hack, Threshold Voltage, Field Effect Mobility, and Gate-to-Channel Capacitance in Polysilicon TFT’s, IEEE Trans. on Electron Devices, vol. 43, 1996, p. 1433-1439.
[23] Huaisheng Wang, Mingxiang Wang, Zhenyu Yang and Han Hao, Stress Power Dependent Self-Heating Degradation of Metal Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin Film Transistors, IEEE Trans. on Electron Devices, 2007, vol.54, pp.3276-84.
[24] Min Xue, Mingxiang Wang, Zhen Zhu, Dongli Zhang and Man Wong, Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses, IEEE Trans. on Electron Devices, 2007, vol.54, pp.225-32.
[1] Hu C., Tam S.C., Hsu F.C., Ko P.K., Chan T.Y. and Terrill K.W., Hot-electron-induced MOSFET degradation-Model, monitor, and improvement, IEEE Trans. on Electron Devices, 1985, vol.32, pp.375-85.
[2] N.A. Hastas, Archontas N., Dimitriadis C. A., Kamarinos G., Nikolaidis T., Georgoulas N. and Thanailakis A, Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors, Microelectronics Reliability, 2005, vol.41, pp. 341-8.
[3] M. A. Kroon, Van Swaaij and R.A.C.M.M., Spatial effects on ideality factor of amorphous silicon pin diodes, Journal of Applied Physics, 2001, vol.90, pp. 994-1000.
[4] Mark Stewart and Miltiadis K. Hatalis, High performance gated lateral polysilicon PIN diodes, Solid-State Electron., 2000, vol.44, pp. 1613-9.
[5] Camara N., Bano E. and Zekentes K., Current transport mechanisms in 4H-SiC pin diodes, 2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003, vol. 2, pp. 249-52 .
[6] Ruzin A. And Marunko S., Current mechanisms in silicon PIN structures processed with various technologies, Nuclear Instruments & Methods in Physics Research, Section A (Accelerators, Spectrometers, Detectors and Associated Equipment), 2002, vol. 492, n 3, pp. 411-22.
[7] Badila M., Tudor B., Brezeanu G., Locatelli M.L., Chante J.P., Millan J., Godignon P.,Lebedev A. and Banu, V., Current-voltage characteristics of large area 6H-SiC pin diodes, Materials Science & Engineering B (Solid-State Materials for Advanced Technology), 1999, vol. B61-B62, pp. 433-6,.
[8] C. Van Berkel, Powell M.J., Franklin A.R. and French I.D., Quality factor in a-SiH nip and pin diodes, Journal of Applied Physics, 1993, vol.73, pp. 5264-8.
[9] Han Hao, Mingxiang Wang, Bo Zhang, Xuejie Shi, Man Wong, A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility, Journal of Applied Physics, 2008, vol. 103, pp. 094513-1-10.
[10] Min Xue, Mingxiang Wang, Zhen Zhu, Dongli Zhang and Man Wong, Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses, IEEE Trans. on Electron Devices, 2007, vol.54, pp.225-32.
[11] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A Reliable Approach to Charge-Pumping Measurements in MOS Transistors, IEEE Transactions on Electron Devices, 1984, vol. ED-31, pp.42-53.
[12] Lei LU, Mingxiang Wang and Man Wong, Geometric effect elimination and reliable trap state density extraction in charge pumping of polysilicon thin-film transistors, IEEE Electron Device Letters, 2009, vol.30, pp.517-9.
[13] Xiaowei Lu, Mingxiang WANG, Kai SUN, and Lei LU,Evaluation of Self-Heating and Hot Carrier Degradation of Poly-Si Thin-Film Transistors using Charge Pumping technique, IEEE International Reliability Physics Symposium, Montreal, Canada, 2010, pp. 1040-1043.