一个大容量片上系统集成电路的研究、设计和实现
摘要
本文研究了大容量存储(Mass-Storage)控制片上系统(SOC)芯片的基本原理、功能、结构及设计技术，取得了如下新的研究成果：
1．基于硬件和软件协同仿真平台的片上系统全新的设计方法，创建了本文所研究的大容量存储控制片上系统芯片的硬件和软件协同仿真平台。完成了包括安全数码(SD)测试向量生成模块、串行电可擦除可编程只读存储器(EEPROM)和闪速存储器(FLASH)在内的多个仿真模型的具体实现。本平台具有软硬件可并行协同设计、仿真及验证等优点，使本文片上系统芯片的整体功能最优化并加快了开发进度。
2．研究并设计成功一种先进的可下载固件(Firmware)架构的高速精简指令系统计算机(RISC)CPU知识产权(Intellectual Property，简称IP)核，本CPU核是传统的单片机PIC微控制器处理速度的4倍，并且可以实现固件的升级和更新。具有完整的知识产权。
3．完成了适合于大容量存储产品的纠错算法(Reed-Solomon算法和BCH算法)的研究，并且完成了硬件代价小、处理速度快的电路实现，研究的算法已经申请发明专利。
4．实现了符合SD协议标准的接口知识产权(Intellectual Property，简称IP)模块的设计。采用分层设计方法，将整个SD接口划分为物理层和数据链路层分别实现，功能清晰，扩展容易。
5．研究并实现了闪速存储器的直接存储访问(DMA)控制技术，极大地提高了数据存取速度。
6．完成了大容量存储控制芯片中固件的关键技术的研究，如启动(boot)只读存储器(ROM)的编写和固件的仿真技术。
7．完成了芯片实际制造用的测试向量生成，测试向量符合Faraday公司的规范，并为芯片实际测试数据所验证。
8．本文的片上系统芯片是一个包含29万门的大规模单片集成系统，采用0.25微米国际标准CMOS生产工艺完成了芯片的实际制造。全面实测参数的数据表明：本片上系统芯片性能十分优良，达到当前国际同类产品的先进水平，并且在软件、算法、硬件代价、速度、成本等方面具有较好的竞争力。
The design technique of Mass-Storage SOC controller and its principle, function and architecture are discussed in this dissertation. The contributions of this work are summarized as follows:
1. By using hardware/software co-design platform-based SOC design method, a Mass-Storage memory controller SOC design platform is built. Thus, hardware and software development can work in a concurrent, co-design, co-simulation and co-verification way on this design platform, this helps to optimize the performance of this SOC chip and reduces the time-to-market.
2. A firmware downloadable high-speed architecture of RISC CPU IP core has been designed. The instruction executing speed of this RISC CPU is 4 times fast than classical PIC MCU. Firmware update is supported in this CPU core, too.
3. Reed-Solomon and BCH error control coding algorithms have been studied in this thesis. The CODEC circuits are realized by using low-cost and high-speed hardware. Both of the algorithms have been applicated for Chinese Invention Patents.
4. The Secure Digital memory card interface IP module is built by using hierarchy design method. The SD interface circuit is implemented by dividing the functions into two individual layers—physical layer and data link layer.
5. A FLASH Direct Memory Access (DMA) technique has been adopt for high-speed data transport between FLASH memory and data buffer.
6. The know-how to firmware of Mass-Storage controller SOC chip is discussed in detail. The boot ROM programming and firmware simulation technique are also described.
7. In this dissertation, we also finished the testbench generation for manufacture testing. The testbench meets the design rule of Faraday Technology Corporation, and passed on-wafer and package testing procedure at UMC foundry.
8. The Mass-Storage SOC chip is manufactured in UMC's 0.25-micron CMOS process, the gates of this chip around 290,000. From the test results, we observed that the performance of this Mass-Storage SOC chip is comparable to similar international productions or even surpassing. It is a competitive production that has efficient ECC algorithms, high data transport speed and low cost.
1．基于硬件和软件协同仿真平台的片上系统全新的设计方法，创建了本文所研究的大容量存储控制片上系统芯片的硬件和软件协同仿真平台。完成了包括安全数码(SD)测试向量生成模块、串行电可擦除可编程只读存储器(EEPROM)和闪速存储器(FLASH)在内的多个仿真模型的具体实现。本平台具有软硬件可并行协同设计、仿真及验证等优点，使本文片上系统芯片的整体功能最优化并加快了开发进度。
2．研究并设计成功一种先进的可下载固件(Firmware)架构的高速精简指令系统计算机(RISC)CPU知识产权(Intellectual Property，简称IP)核，本CPU核是传统的单片机PIC微控制器处理速度的4倍，并且可以实现固件的升级和更新。具有完整的知识产权。
3．完成了适合于大容量存储产品的纠错算法(Reed-Solomon算法和BCH算法)的研究，并且完成了硬件代价小、处理速度快的电路实现，研究的算法已经申请发明专利。
4．实现了符合SD协议标准的接口知识产权(Intellectual Property，简称IP)模块的设计。采用分层设计方法，将整个SD接口划分为物理层和数据链路层分别实现，功能清晰，扩展容易。
5．研究并实现了闪速存储器的直接存储访问(DMA)控制技术，极大地提高了数据存取速度。
6．完成了大容量存储控制芯片中固件的关键技术的研究，如启动(boot)只读存储器(ROM)的编写和固件的仿真技术。
7．完成了芯片实际制造用的测试向量生成，测试向量符合Faraday公司的规范，并为芯片实际测试数据所验证。
8．本文的片上系统芯片是一个包含29万门的大规模单片集成系统，采用0.25微米国际标准CMOS生产工艺完成了芯片的实际制造。全面实测参数的数据表明：本片上系统芯片性能十分优良，达到当前国际同类产品的先进水平，并且在软件、算法、硬件代价、速度、成本等方面具有较好的竞争力。
The design technique of Mass-Storage SOC controller and its principle, function and architecture are discussed in this dissertation. The contributions of this work are summarized as follows:
1. By using hardware/software co-design platform-based SOC design method, a Mass-Storage memory controller SOC design platform is built. Thus, hardware and software development can work in a concurrent, co-design, co-simulation and co-verification way on this design platform, this helps to optimize the performance of this SOC chip and reduces the time-to-market.
2. A firmware downloadable high-speed architecture of RISC CPU IP core has been designed. The instruction executing speed of this RISC CPU is 4 times fast than classical PIC MCU. Firmware update is supported in this CPU core, too.
3. Reed-Solomon and BCH error control coding algorithms have been studied in this thesis. The CODEC circuits are realized by using low-cost and high-speed hardware. Both of the algorithms have been applicated for Chinese Invention Patents.
4. The Secure Digital memory card interface IP module is built by using hierarchy design method. The SD interface circuit is implemented by dividing the functions into two individual layers—physical layer and data link layer.
5. A FLASH Direct Memory Access (DMA) technique has been adopt for high-speed data transport between FLASH memory and data buffer.
6. The know-how to firmware of Mass-Storage controller SOC chip is discussed in detail. The boot ROM programming and firmware simulation technique are also described.
7. In this dissertation, we also finished the testbench generation for manufacture testing. The testbench meets the design rule of Faraday Technology Corporation, and passed on-wafer and package testing procedure at UMC foundry.
8. The Mass-Storage SOC chip is manufactured in UMC's 0.25-micron CMOS process, the gates of this chip around 290,000. From the test results, we observed that the performance of this Mass-Storage SOC chip is comparable to similar international productions or even surpassing. It is a competitive production that has efficient ECC algorithms, high data transport speed and low cost.
引文
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[12] Klapproth, P., General architectural concepts for IP core re-use[C], Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings. 2002:325.
[13] Zhao Junchao, Chen Weiliang, Wei Shaojun, Parameterized IP core design [C], 2001. Proceedings. 4th International Conference on ASIC, 2001:744 - 747.
[14] McLoone, M., McCanny, J.V., Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography[C], Computers and Digital Techniques, IEE Proceedings-, 2003, vol.150(4):239 - 244.
[15] Youngchul Cho, Ganghee Lee, Sungjoo Yoo et al. Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design Design[C], Automation and Test in Europe Conference and Exhibition, 2003, 2003:132 - 137 suppl.
[16] Mooney, V. J., III, Blough, D.M., A hardware-software real-time operating system framework for SoCs[J], Design & Test of Computers, IEEE , 2002, vol. 19(6):44 - 51.
[17] Lie, D.Y.C., Xiaojuen Yuan, Larson, L. E. et al. "RF-SoC": low-power single-chip radio design using Si/SiGe BiCMOS technology [C], Microwave and Millimeter Wave Technology, 2002. Proceedings. ICMMT 2002. 2002 3rd International Conference on, 2002:30 - 37.
[18] Buss, D., Evans, B. L., Bellay, J. et al. SOC CMOS technology for personal Internet products[J], IEEE Transactions on Electron Devices, 2003, vol.50(3):546 - 556.
[19] Stabernack, B., von Colin, G., An MPEG-4 video codec SOC for mobile multimedia applications [C], Consumer Electronics, 2003. ICCE. 2003 IEEE International Conference on, 2003:248 - 249.
[20] Fang, W.-C., A system-on-chip design of a low-power smart vision system[C], 1998 IEEE Workshop on Signal Processing Systems, 1998:63 - 72.
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[22] Yosbikawa, K., Mori, S., Sakagami, E. et al. Flash EEPROM Cell scaling based on tunnel oxide thinning limitations[C], VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on ,1991:79 - 80.
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