数字化变电站合并单元硬件设计与实现
|
摘要
随着近年来电力产量的持续增加和电力系统规模的不断扩大,传统变电站综合自动化技术已经不能满足目前电力系统智能化发展的要求,推广和建立基于IEC61850标准的数字化变电站是电力系统技术发展的未来走向,也是目前我国电力系统研究和发展的热点和重点之一。
论文的设计任务围绕合并单元需要实现的功能展开,而整体思路则是以合并单元的硬件设计为出发点。首先介绍了数字化变电站的系统结构,并简述了合并单元的研究意义。在分析比较IEC60048-7/8和IEC61850-9标准后,采用IEC61850标准作为本合并单元的设计依据。其次分析了合并单元的各种同步方案,提出了由IRIG-B码和PPS秒脉冲作为同步信号的基准,利用ADSP和FPGA双处理器架构的合并单元硬件设计方案。合并单元以BF536和EP2C8为核心处理器,在最小运行系统的基础上,利用AD7606、MT48LC4M16A2、SST39VF和88E6060等芯片,进行必要插件和系统电路的扩展,从而完成数据同步接收、数据处理和数据发送等工作。本文根据模块化设计思路,分析了各个插件和所需模块的功能和原理,并按照器件选型、原理分析和PCB设计的顺序展开论述。
本文对合并单元整体硬件原理设计的同时,还进行了PCB板电路的设计,并通过信号完整性仿真软件对所设计的印刷电路板进行信号仿真。最后,本文根据ADSP和FPGA的集成开发环境,简述了对合并单元的调试。
Recently, with the increasing of electrical production and the expansion of power system's scale, automation technology of traditional substation can't meet the digital and intelligent development demands of power grid. Then the popularizing and establishing of digital substation which is duo to IEC61850standards will be the developing trend of power system, it is also the hot spot and emphasize of power system's research and development in our country. Therefore, researching and developing Merging Unit of the digital substation has great importance and engineering value.
The design task of this issue is to revolve the function needs to achieve of Merging Unit, and the hardware design of MU is staring point of the whole idea in this article.Firstly, this paper introduces system structure of digital substation, then descripts the implications for research of MU. After analyzing and contrasting IEC60048-7/8standards and IEC61850standards, this paper puts forward using IEC61850standards as the design's basis. Secondly, this paper analyzes some synchronous plans of MU, putting forward uses IRIG-B and PPS as the datum of synchronous signal. The design is based on ADSP and FPGA structure.BF536chip and EP2C8chip are the core processors in MU. Based on the minimum operating system, the expansions in the necessary plug-in and system circuit are according to some chips such as AD7606, MT48LC4M16A2, SST39VF,88E6060and so on, thus the MU completes the task of data synchronous reception, data process and data transmission. According to modular design ideas, this paper analyses the function and principle of all plug-ins. Each section has been discussed according to the order of choosing devices, principle analysis and circuit design.
When designing the MU's hardware and principle, this paper also designs PCB of MU, and using signal integrity simulation tools to emulate the signal of PCB. At last, according to the development circumstance of ADSP and FPGA, this paper introduces the commissioning of MU.
论文的设计任务围绕合并单元需要实现的功能展开,而整体思路则是以合并单元的硬件设计为出发点。首先介绍了数字化变电站的系统结构,并简述了合并单元的研究意义。在分析比较IEC60048-7/8和IEC61850-9标准后,采用IEC61850标准作为本合并单元的设计依据。其次分析了合并单元的各种同步方案,提出了由IRIG-B码和PPS秒脉冲作为同步信号的基准,利用ADSP和FPGA双处理器架构的合并单元硬件设计方案。合并单元以BF536和EP2C8为核心处理器,在最小运行系统的基础上,利用AD7606、MT48LC4M16A2、SST39VF和88E6060等芯片,进行必要插件和系统电路的扩展,从而完成数据同步接收、数据处理和数据发送等工作。本文根据模块化设计思路,分析了各个插件和所需模块的功能和原理,并按照器件选型、原理分析和PCB设计的顺序展开论述。
本文对合并单元整体硬件原理设计的同时,还进行了PCB板电路的设计,并通过信号完整性仿真软件对所设计的印刷电路板进行信号仿真。最后,本文根据ADSP和FPGA的集成开发环境,简述了对合并单元的调试。
Recently, with the increasing of electrical production and the expansion of power system's scale, automation technology of traditional substation can't meet the digital and intelligent development demands of power grid. Then the popularizing and establishing of digital substation which is duo to IEC61850standards will be the developing trend of power system, it is also the hot spot and emphasize of power system's research and development in our country. Therefore, researching and developing Merging Unit of the digital substation has great importance and engineering value.
The design task of this issue is to revolve the function needs to achieve of Merging Unit, and the hardware design of MU is staring point of the whole idea in this article.Firstly, this paper introduces system structure of digital substation, then descripts the implications for research of MU. After analyzing and contrasting IEC60048-7/8standards and IEC61850standards, this paper puts forward using IEC61850standards as the design's basis. Secondly, this paper analyzes some synchronous plans of MU, putting forward uses IRIG-B and PPS as the datum of synchronous signal. The design is based on ADSP and FPGA structure.BF536chip and EP2C8chip are the core processors in MU. Based on the minimum operating system, the expansions in the necessary plug-in and system circuit are according to some chips such as AD7606, MT48LC4M16A2, SST39VF,88E6060and so on, thus the MU completes the task of data synchronous reception, data process and data transmission. According to modular design ideas, this paper analyses the function and principle of all plug-ins. Each section has been discussed according to the order of choosing devices, principle analysis and circuit design.
When designing the MU's hardware and principle, this paper also designs PCB of MU, and using signal integrity simulation tools to emulate the signal of PCB. At last, according to the development circumstance of ADSP and FPGA, this paper introduces the commissioning of MU.
引文
[1]高翔,张沛超.数字化变电站的主要特征和关键技术[J].电网技术.2006(23)：67-71.
[2]汪秀丽.数字化变电站综述[J].水利电力科技.2007(2)：7-15.
[3]高翔.数字化变电站应用技术[M].北京：中国电力出版社,2008.
[4]党晓勇.基于IEC61850电子式互感器数字接口硬件方案研究[D].西南交通大学,2010.
[5]罗承沐.电子式互感器与数字化变电站[M].北京：中国电力出版社,2012.
[6]谭春雷.变电站综合自动化应用中的技术问题分析[M].北京：中国科技信息,2006.
[7]张振洋.35kV智能变电站合并单元的硬件开发研究[D].东北电力大学,2012.
[8]Xia X, Yan X, Feng P, et al. Synchronization method based on FPGA for merging unit of the electronic transformers[C].2009.
[9]Jianfeng L, Kaicheng L, Huayun Y. The design of a merging unit of electronic transformer based on arm[C].2007.
[10]张丹.光电混合式电流互感器低压侧单元的研究[D].沈阳工业大学,2009.
[11]Iec. IEC 60044-7 Instrument transformer-part 7:electrial voltage transducers[Z].2002.
[12]Iec. IEC 60044-8 Instrument transformer-part 8:electrial current transducers[Z].2002.
[13]黄灿英.基于IEC61850标准的合并单元的研究[D].西安科技大学,2008.
[14]田云杰.基于IEC61850标准的嵌入式合并单元控制器的研究[D].广东工业大学,2008.
[15]吴旻,刘进进,王红光.高精度IRIG-B码对时解码模块的设计与实现[J].工业控制计算机.2012(1)：88-91.
[16]邴志光,束坤,顾燕飞.IRIG-B码在时间同步系统中的应用[J].现代电子技术.2012(7)：16-18.
[17]谢仁祥IRIG-B码解码及网络校时的实现[D].四川大学,2006.
[18]王莉.IEEE1588协议测试方法[J].电信网技术.2010(5)：71-76.
[19]汪祺航,吴在军,赵上林,等.IEEE1588时钟同步技术在数字化变电站中的应用[J].电力系统保护与控制.2010(19)：137-141.
[20]樊陈,倪益民,沈健,等.IEEE1588在基于IEC 61850-9-2标准的合并单元中的应用[J].电力系统自动化.2011(6)：55-59.
[21]Yin Z L, Liu W S. A novel FPGA-based method to design the merging unit following IEC 61850[C]. 2004.
[22]王芸,杨彬.IEEE1588(?)寸钟同步实现方式研究[Z].中国天津：20099-12.
[23]胡春江.基于IEC61850标准的电子式互感器方案研究[D].西南交通大学,2009.
[24]Chen L, Jehng Y, Chiueh T. Pipeline interleaving design for FIR, IIR, and FFT array processors[J]. Journal of VLSI Signal Processing.1995(3).
[25]李群湛,贺建闽.牵引供电系统分析[M].成都：西南交通大学出版社,2007.
[26]陈峰.Blackfin系列DSP原理与系统设计[M].北京：电子工业出版社,2010.
[27]Blackfin Processor and SDRAM Technology[Z]. Analog Devices,2008.
[28]ADSP-BF534/ADSP-BF536/ADSP-BF537:Blackfin Embedded Processor Data Sheet[Z]. Analog Devices,2010.
[29]Interfacing Blackfin Processors to the Intellon INT5200 HomePlug PHY [Z]. Analog Devices,2008.
[30]Cyclone Ⅱ Device Family Data Sheet[Z]. Altera,2008.
[31]吴剑斌.接触网定点监测系统的硬件设计[D].西南交通大学,2011.
[32]8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC[Z]. Analog Devices, 2010.
[33]SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS[Z]. TEXAS INSTRUMENTS,2005.
[34]Dual-Output, Low Dropout Volt Regs Integrated SVS for Split Voltage Systems[Z]. TEXAS INSTRUMENTS,2010.
[35]Processor Supervisory Circuits TPS382x-xx[Z]. TEXAS INSTRUMENTS,1998.
[36]Cyclone Ⅱ Clock Management[Z]. Altera,2007.
[37]PLLs in Cyclone Ⅱ Devices[Z]. Altera,2008.
[38]External Memory Interfaces[Z]. Altera,2007.
[39]IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone Ⅱ Devices[Z]. Altera,2007.
[40]林倩.Flash闪存技术浅析[J].产业与科技论坛.2007(9)：143-144.
[41]程飞龙刘冬焦明华.基于可编程逻辑器件的高速SDRAM控制器的实现[J].电脑知识与技术.2012(32).
[42]6-Port Fast Ethernet Switch 88E6060[Z]. Marvell Semiconductor,2002.
[43]周润景,苏良碧.Cadence高速电路板设计与仿真：信号与电源完整性分析[M].北京：电子工业出版社,2011.
[44]张海风HyperLynx仿真与PCB设计[M].北京：机械工业出版社,2005.
[45]周润景,赵建凯,任冠中.OrCAD & PADS高速电路板设计与仿真[M].北京：电子工业出版社,2011.
[46]Bogatin Eric. Signal integrity:simplified信号完整性分析[M].北京：北京电子工业出版社,2007.
[47]覃婕,阎波,林水生.基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真[J].现代电子技术.2011(10)：169-171.
[48]周润景.Cadence高速电路板设计与仿真[M].北京：电子工业出版社,2009.
[49]周路.高速电路信号完整性分析与设计[D].电子科技大学,2011.
[50]厉科立,景占荣,严会会.基于HyperLynx的FPGA系统信号完整性仿真分析[J].现代电子技术. 2011(8)：144-146.
[51]李成,程晓宇,毕笃彦,等.基于HyperLynx的高速DSP系统信号完整性仿真研究[J].电子器件.2009(2)：445-451.
[52]熊青松,吴兆华,陈品,等.基于Hyperlynx的高速互连信号串扰分析[J].桂林电子科技大学学报.2010(6)：537-540.
[2]汪秀丽.数字化变电站综述[J].水利电力科技.2007(2)：7-15.
[3]高翔.数字化变电站应用技术[M].北京：中国电力出版社,2008.
[4]党晓勇.基于IEC61850电子式互感器数字接口硬件方案研究[D].西南交通大学,2010.
[5]罗承沐.电子式互感器与数字化变电站[M].北京：中国电力出版社,2012.
[6]谭春雷.变电站综合自动化应用中的技术问题分析[M].北京：中国科技信息,2006.
[7]张振洋.35kV智能变电站合并单元的硬件开发研究[D].东北电力大学,2012.
[8]Xia X, Yan X, Feng P, et al. Synchronization method based on FPGA for merging unit of the electronic transformers[C].2009.
[9]Jianfeng L, Kaicheng L, Huayun Y. The design of a merging unit of electronic transformer based on arm[C].2007.
[10]张丹.光电混合式电流互感器低压侧单元的研究[D].沈阳工业大学,2009.
[11]Iec. IEC 60044-7 Instrument transformer-part 7:electrial voltage transducers[Z].2002.
[12]Iec. IEC 60044-8 Instrument transformer-part 8:electrial current transducers[Z].2002.
[13]黄灿英.基于IEC61850标准的合并单元的研究[D].西安科技大学,2008.
[14]田云杰.基于IEC61850标准的嵌入式合并单元控制器的研究[D].广东工业大学,2008.
[15]吴旻,刘进进,王红光.高精度IRIG-B码对时解码模块的设计与实现[J].工业控制计算机.2012(1)：88-91.
[16]邴志光,束坤,顾燕飞.IRIG-B码在时间同步系统中的应用[J].现代电子技术.2012(7)：16-18.
[17]谢仁祥IRIG-B码解码及网络校时的实现[D].四川大学,2006.
[18]王莉.IEEE1588协议测试方法[J].电信网技术.2010(5)：71-76.
[19]汪祺航,吴在军,赵上林,等.IEEE1588时钟同步技术在数字化变电站中的应用[J].电力系统保护与控制.2010(19)：137-141.
[20]樊陈,倪益民,沈健,等.IEEE1588在基于IEC 61850-9-2标准的合并单元中的应用[J].电力系统自动化.2011(6)：55-59.
[21]Yin Z L, Liu W S. A novel FPGA-based method to design the merging unit following IEC 61850[C]. 2004.
[22]王芸,杨彬.IEEE1588(?)寸钟同步实现方式研究[Z].中国天津：20099-12.
[23]胡春江.基于IEC61850标准的电子式互感器方案研究[D].西南交通大学,2009.
[24]Chen L, Jehng Y, Chiueh T. Pipeline interleaving design for FIR, IIR, and FFT array processors[J]. Journal of VLSI Signal Processing.1995(3).
[25]李群湛,贺建闽.牵引供电系统分析[M].成都：西南交通大学出版社,2007.
[26]陈峰.Blackfin系列DSP原理与系统设计[M].北京：电子工业出版社,2010.
[27]Blackfin Processor and SDRAM Technology[Z]. Analog Devices,2008.
[28]ADSP-BF534/ADSP-BF536/ADSP-BF537:Blackfin Embedded Processor Data Sheet[Z]. Analog Devices,2010.
[29]Interfacing Blackfin Processors to the Intellon INT5200 HomePlug PHY [Z]. Analog Devices,2008.
[30]Cyclone Ⅱ Device Family Data Sheet[Z]. Altera,2008.
[31]吴剑斌.接触网定点监测系统的硬件设计[D].西南交通大学,2011.
[32]8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC[Z]. Analog Devices, 2010.
[33]SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS[Z]. TEXAS INSTRUMENTS,2005.
[34]Dual-Output, Low Dropout Volt Regs Integrated SVS for Split Voltage Systems[Z]. TEXAS INSTRUMENTS,2010.
[35]Processor Supervisory Circuits TPS382x-xx[Z]. TEXAS INSTRUMENTS,1998.
[36]Cyclone Ⅱ Clock Management[Z]. Altera,2007.
[37]PLLs in Cyclone Ⅱ Devices[Z]. Altera,2008.
[38]External Memory Interfaces[Z]. Altera,2007.
[39]IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone Ⅱ Devices[Z]. Altera,2007.
[40]林倩.Flash闪存技术浅析[J].产业与科技论坛.2007(9)：143-144.
[41]程飞龙刘冬焦明华.基于可编程逻辑器件的高速SDRAM控制器的实现[J].电脑知识与技术.2012(32).
[42]6-Port Fast Ethernet Switch 88E6060[Z]. Marvell Semiconductor,2002.
[43]周润景,苏良碧.Cadence高速电路板设计与仿真：信号与电源完整性分析[M].北京：电子工业出版社,2011.
[44]张海风HyperLynx仿真与PCB设计[M].北京：机械工业出版社,2005.
[45]周润景,赵建凯,任冠中.OrCAD & PADS高速电路板设计与仿真[M].北京：电子工业出版社,2011.
[46]Bogatin Eric. Signal integrity:simplified信号完整性分析[M].北京：北京电子工业出版社,2007.
[47]覃婕,阎波,林水生.基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真[J].现代电子技术.2011(10)：169-171.
[48]周润景.Cadence高速电路板设计与仿真[M].北京：电子工业出版社,2009.
[49]周路.高速电路信号完整性分析与设计[D].电子科技大学,2011.
[50]厉科立,景占荣,严会会.基于HyperLynx的FPGA系统信号完整性仿真分析[J].现代电子技术. 2011(8)：144-146.
[51]李成,程晓宇,毕笃彦,等.基于HyperLynx的高速DSP系统信号完整性仿真研究[J].电子器件.2009(2)：445-451.
[52]熊青松,吴兆华,陈品,等.基于Hyperlynx的高速互连信号串扰分析[J].桂林电子科技大学学报.2010(6)：537-540.