基于全数字锁相环的时间数字转换器的研究
摘要
TDC(Time Digital Converter,TDC)是一种时间测量的常用电路,主要计算参考信号到事件发生的时间及两个脉冲间的时间间隔,将时间的间隔直接转化为高精度的数字值,并实现数字输出。目前已被广泛应用于电子领域,如用于全数字锁相环ADPLL中,提高其测试器件和信号的时间特性。近几年,最受关注的TDC是使用高速CMOS数字电路的结构,主要原因是被测试信号能实现较高的时间精度。对TDC精确度进行研究,将有利于TDC的应用和质量保证。
本论文旨在研究时间数字转换器的精度,根据一种全数字锁相环电路中时间数字转换器的结构和性能,提出了TDC的设计方法。采用EDA软件,将电路图绘制出来,引入千分尺自较正算法,通过VHDL语言对TDC电路信号进行编码。最后通过测试电路,得出仿真结果,达到对TDC精确度的准确测量。本文的主要工作和成果如下:
1.设计出TDC模块的电路构成;在PSPICE软件工具下,通过引入基本触发器,放大器等器件,建立了顶层TDC模型,为进一步分析TDC精确度打下了基础。通过仿真,分析了温度电流电压对数字信号传输延迟的影响。
2.研究TDC核心结构;在HSPICE软件工具下,通过将触发器门电路进行剖析,由程序设计实现每个器件的漏源栅极,以及线路长度等底层参数,设计各种主要器件的不同传输性能。得到CMOS下电压电流以及器件线路的部局对直接延迟的具体影响,确定了这些因素的优先等级,测得在CMOS下时间延迟的线性趋势。
3.根据全数字锁相环中的TDC性能,在深入研究现有TDC的优缺点的基础上,引入了一种实现信号自纠正的算法一千分尺算法。在TDC的仿真过程中,建立分析上的自纠正方案,通过对改进后的固定矢量进行仿真研究,验证了该方案的合理性与可行性。
4.对本文自顶向下的工作进行了详细解析,针对软件硬件基础和开发流程,做了更为层次化的介绍。在对本文研究的总结的同时,也对今后的研究工作作出分析与展望。
TDC (Time Digital Converter, TDC) is the common measurement of the time circuit, its main function is to calculate the main reference signal to the incident and the time interval between pulses, and digital output.The interval of time will directly translate into high-precision digital value and achieve digital signals. TDC has been widely used in electronics, often used in the field of electronic testing (for example: DPLL,ADPLL)to improve their test devices and signal characteristics of the time. In recent years, the TDC is most concerned about the use of high-speed digital CMOS circuit structure, mainly due to be test signals to achieve a higher accuracy of the time. TDC on the accuracy of research will be beneficial to the application of TDC and quality assurance.
This paper aims to study the time-to-digital converter's accuracy, according to an all-digital phase locked loop circuit in time-to-digital converter on the structure and performance, the TDC design method. Using the EDA software to draw circuit diagrams,and the fastest logic-level regenerative timing algorithm through the VHDL language of the TDC circuit encoded signal. Finally, design the test circuit and get the simulation results obtained to TDC for the accuracy of the measurement accuracy. The main work and achievements are as follows:
1. Design of the TDC module circuit; Using PSPICE software tools, through the introduction of the basic flip-flops, amplifiers, and other devices, design a top-level model of TDC, make the foundation for the further analysis of the accuracy. Make the circuit simulation, analysis of the temperature of the current and voltage digital signal transmission delay.
2. Study on the structure of the TDC core; Using the HSPICE software tools, through the gate circuit to analyze the flip-flop by programming the devices to achieve each of the gate leakage source, as well as the length of the line, and other parameters of the underlying design of the main devices of different transmission capability. Get the specific impact to the delay from the voltage-current and the the bureau of the department of the device line to determine the priority level, measured the time delay under the CMOS linear trend.
3. According to the TDC's performance in ADPLL, study in-depth of the strengths and weaknesses of the existing TDC on the basis of a self-correcting algorithm. Based on the establishment of the correct analysis of the program,through improve the fixed vector for TDC simulation, prove the rationality and feasibility of the research.
4. This article on the work of top-down analysis in detail, the basis for software and hardware development process, the introduction of a more level. In this paper, sum at the same time the research analysis and prospects in the future.
本论文旨在研究时间数字转换器的精度,根据一种全数字锁相环电路中时间数字转换器的结构和性能,提出了TDC的设计方法。采用EDA软件,将电路图绘制出来,引入千分尺自较正算法,通过VHDL语言对TDC电路信号进行编码。最后通过测试电路,得出仿真结果,达到对TDC精确度的准确测量。本文的主要工作和成果如下:
1.设计出TDC模块的电路构成;在PSPICE软件工具下,通过引入基本触发器,放大器等器件,建立了顶层TDC模型,为进一步分析TDC精确度打下了基础。通过仿真,分析了温度电流电压对数字信号传输延迟的影响。
2.研究TDC核心结构;在HSPICE软件工具下,通过将触发器门电路进行剖析,由程序设计实现每个器件的漏源栅极,以及线路长度等底层参数,设计各种主要器件的不同传输性能。得到CMOS下电压电流以及器件线路的部局对直接延迟的具体影响,确定了这些因素的优先等级,测得在CMOS下时间延迟的线性趋势。
3.根据全数字锁相环中的TDC性能,在深入研究现有TDC的优缺点的基础上,引入了一种实现信号自纠正的算法一千分尺算法。在TDC的仿真过程中,建立分析上的自纠正方案,通过对改进后的固定矢量进行仿真研究,验证了该方案的合理性与可行性。
4.对本文自顶向下的工作进行了详细解析,针对软件硬件基础和开发流程,做了更为层次化的介绍。在对本文研究的总结的同时,也对今后的研究工作作出分析与展望。
TDC (Time Digital Converter, TDC) is the common measurement of the time circuit, its main function is to calculate the main reference signal to the incident and the time interval between pulses, and digital output.The interval of time will directly translate into high-precision digital value and achieve digital signals. TDC has been widely used in electronics, often used in the field of electronic testing (for example: DPLL,ADPLL)to improve their test devices and signal characteristics of the time. In recent years, the TDC is most concerned about the use of high-speed digital CMOS circuit structure, mainly due to be test signals to achieve a higher accuracy of the time. TDC on the accuracy of research will be beneficial to the application of TDC and quality assurance.
This paper aims to study the time-to-digital converter's accuracy, according to an all-digital phase locked loop circuit in time-to-digital converter on the structure and performance, the TDC design method. Using the EDA software to draw circuit diagrams,and the fastest logic-level regenerative timing algorithm through the VHDL language of the TDC circuit encoded signal. Finally, design the test circuit and get the simulation results obtained to TDC for the accuracy of the measurement accuracy. The main work and achievements are as follows:
1. Design of the TDC module circuit; Using PSPICE software tools, through the introduction of the basic flip-flops, amplifiers, and other devices, design a top-level model of TDC, make the foundation for the further analysis of the accuracy. Make the circuit simulation, analysis of the temperature of the current and voltage digital signal transmission delay.
2. Study on the structure of the TDC core; Using the HSPICE software tools, through the gate circuit to analyze the flip-flop by programming the devices to achieve each of the gate leakage source, as well as the length of the line, and other parameters of the underlying design of the main devices of different transmission capability. Get the specific impact to the delay from the voltage-current and the the bureau of the department of the device line to determine the priority level, measured the time delay under the CMOS linear trend.
3. According to the TDC's performance in ADPLL, study in-depth of the strengths and weaknesses of the existing TDC on the basis of a self-correcting algorithm. Based on the establishment of the correct analysis of the program,through improve the fixed vector for TDC simulation, prove the rationality and feasibility of the research.
4. This article on the work of top-down analysis in detail, the basis for software and hardware development process, the introduction of a more level. In this paper, sum at the same time the research analysis and prospects in the future.
引文
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[4]Floyd M.Gardner.锁相环技术Phaseloek techniques[M].北京:人民邮电出版社,2007
[5]张兴,黄如,刘晓彦.微电子概论[M],北京:北京大学出版社,2000
[6]甘学温,赵宝瑛.集成电路原理与设计[M],北京:北京大学出版社,2006
[7]毕查德.拉扎维,陈贵灿译.模拟CMOS集成电路设计[M],西安:西安交通大学出版社,2003
[8]谢嘉奎.电子线路-线性部分[M].北京:高等教育出版社,1999
[9]张延,黄佩诚.高精度时间间隔测量技术与方法[J].上海:天文学进,2006.24(1).1-15
[10]谢程宏.全数字锁相环的设计[M].北京:电子设计应用,2003.4-12
[11]李永平.PSPICE电路仿真程序设计[M].北京:国防出版社,2006
[12]苏宏宁.PSPICE电路编辑程序设计[M].北京:国防出版社,2004
[13]Robert Bogdan Staszewski,1.3V 20ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS[J].IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS——Ⅱ:EXPRESS BRIEFS,VOL.53,2006.NO.3
[14]姚立真.通用电路模拟技术及软件应用SPICE和Pspice[M].北京:电子工业出版社,1994
[15]Behzad Razavi.Principles of Data Conversion System Design[J].New York:IEEE Press,1995
[16]Floyd M.Gardner.Phaselock Techniques(第3版)[M],北京:人民邮电出版社,2007
[17]张灿,刘笑宙.DDS+PLL可编程全数字锁相环及其应用[N].北京:遥测遥控技术报,2007.10
[18]仇善忠,张冠百.锁相与频率合成技术[M].北京:电子工业出版社,1986
[19]Behzad Razavi.模拟CMOS集成电路设计(影印版)[M].北京.清华大学出版社,2005
[20]Behzad Razavi.Monolithic phase-locked loops and clock recovery circuits[J].New York:The Institute of Electuical and Electronics Engineers,Inc,1996
[21]秦世才等.模拟集成电子学[M].天津:天津科学技术出版社,1996
[22]张伟,李竹.超高速CMOs锁相环集成电路设计[D].电子工程世界,模拟电路.2007
[23]A SEUMOSFETCY P&S TPS2816 TPS2817 TPS2818 TPS2819时间电压关系 [S].1994
[24]Ching-Che Chung and Chen-Yi Lee.An All-Digital Phase-Locked Loop for High-Speed Clock Generation[J].IEEE JOURNAL OF SOLD-STATE CIRCUTTS,VOL.38,NO.2,FEBRUARY 2003
[25]林延畅,王小斌.一种时间-数字转换MINI插件的研制[J].北京:核电子学与探测技术.2008
[26]Rohde,Ulrich L.Low-Noise Frequency Synthesizers Using Fractional N Phase-Locked Loops[J].Proc.IEEE,vol.69,April 1981
[27]B.Razavi,ed.Phase-Locking in High-Performance Systems,Reprint Volume[J],.IEEE Press,New York,and Wiley,New York,2003
[28]B.Razavi,ed.Challenges in the Design of High-Speed Clock and Data Recovery Circuits[J],IEEE Communications Magazine 40,94-101,2002
[29]J.Tal.Speed Control by Phase-Locked servo Systems:New Possibilities and limitations.Ieee Trans[P].Ind Electron.Control Instrum.IECI-24,118-125,1981
[30]李庆常.数字电子技术基础(第4版)[M].北京:机械工业出版社,2008
[31]武俊鹏,孟昭林,付小晶等.数字电路与可编程技术实验教程[M].哈尔滨:哈尔滨工程大学出版社,2007
[32]蔡锦福等.运算放大器原理与应用[M].北京:科学出版社,2005
[33]李本俊.MOS集成电路原理与设计[M].北京:北京邮电大学出版社,1997
[34]陈炳权等.基于FPGA中专用进位连线的精密TDC设计[J].长沙:湘潭大学自然科学学报.2008
[35]刘国福,刘波.TDC-GP1高精度时间间隔测量芯片及其应用[J].新器件新技术.2004
[36]Michael Perrott.High Speed Communication Circuits and Systems Lecture 15Integer-N Frequency Synthesizers[D].Massachusetts Institute Of Technology.2003
[37]C.Lo and H.Luong.A 1.5-V 900-MHZ monolithic CMOS fast-switching frequency syn -thesizer for wireless applications[J].IEEE J.Solid-State ircuits,vol.27,pp.459-470,Apr.2002
[38]龙忠琪,贾立新.数字集成电路教程[M].北京:科学出版社,2001
[39]余冬菊,苏玉萍,郑琼琼.基于FPGA的数字TDC设计[J].中国科技信息报.2008-8
[40]梁家昌.线性电路瞬态分析[M].北京:机械工业出版社,1987
[41]小林春夫.TDC可以采用CMOS工艺[J].北京:电子设计应用.2007
[42]Rohde,Ulrich L.Low-Noise Frequency Synthesizers Using Fractional N Phase-Locked Loops[J].Englewood Cliffs,NJ,1983
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