射频功率LDMOSFET中的热累积效应研究
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摘要
摘要随着射频集成电路的迅速发展,射频功率器件在个人消费类电子、移动通讯设备、乃至军用雷达上的需求都在与日俱增。由于现有的射频功率器件大都存在工艺复杂,造价昂贵的特点,所以迫切需要一种工艺简单,造价低廉且易于集成的功率器件来满足市场的需求。
由于横向双扩散金属氧化物场效应晶体管(LDMOSFET)具有良好的电学特性和射频表现,并且可以与标准CMOS工艺完全兼容,因而在射频集成电路中得到了越来越广泛的应用[1]-[5]。
然而,作为功率器件,器件自身的热效应越来越成为影响器件正常工作的重要因素。在某些情况下,半导体器件或电路必须工作在电磁脉冲(EMP)干扰之下。特别地,当一个高功率电磁脉冲(HEMP)突然注入器件时,会导致器件内部电场强度过大或温度升高超过正常工作阈值温度,从而产生电击穿或热击穿。为了确定EMP参数对半导体器件的干扰及损伤程度,通常情况下可以采用试验测试和理论研究的方法。但是由于受到器件、系统的复杂性和电磁环境诸多因素的限制,准确的试验非常困难,因此有必要从理论上研究电磁脉冲对电子系统的破坏机理,而电子系统的基本组成部分是半导体器件,所以首先要对半导体器件进行研究。
本文将运用理论研究的方法分析LDMOSFET在电磁脉冲影响下的热效应。通过有限元方法对典型LDMOSFET进行瞬态电-热建模仿真,获得电磁脉冲影响下LDMOSFET器件的热效应,以分析不同参数电磁脉冲对器件的干扰和损伤程度。本文的主要研究内容如下:
第二章将分析LDMOSFET的基本结构及特点。对典型的LDMOSFET进行器件结构建模。
第三章将介绍半导体器件二维仿真的理论基础,包括器件参数和模型建立所需的基本方程和边界条件;建立二维稳态和瞬态模型下半导体器件所满足的刚性、耦合、非线性偏微分方程组,并对边界条件及参数的确定进行讨论。
第四章将介绍利用时域有限元方法进行器件数值模拟的步骤,建立基于时域有限元方法的二维稳态和瞬态的半导体器件数值模拟矩阵,然后运用FORTRAN语言对方程组进行数值计算。
第五章将对单个电磁脉冲作用下LDMOSFET的热效应进行讨论,比较不同脉冲参数情况下器件温度升高的不同情况,并定义热击穿区域(Thermal Breakdown Zone)以衡量不同电磁脉冲对器件的损伤程度。
第六章将对周期电磁脉冲作用下LDMOSFET的热累积效应进行分析,比较不同周期情况下器件热累积效应的严重程度。
第七章将对本文的研究工作进行系统总结。
Due to the rapid development of radio frequency integrated circuit, the demands of RF power devices in consumer electronics, mobile communications and military radars are growing rapidly now. The applications of current RF power devices are limited because of the high cost and complicated technology, so new RF power devices with compatible technology and low fabrication cost are badly needed to satisfy the demands of the market.
Lateral double-diffused MOSFET (LDMOSFET), compatible with standard silicon CMOS technology, has excellent electronic characteristics and RF performance. So it is used more and more widely in RFIC industry nowadays [1]-[5]. But as power device, the thermal effect of LDMOSFET itself has become an increasingly important issue that influences its performance. In some situations, semiconductor devices and circuits must operate under possible impact of an electromagnetic pulse (EMP). In particular, as a high-power EMP is suddenly injected into a semiconductor device, electrical or thermal breakdown can be definitely caused. Normally, there are two methods to investigate breakdown phenomena of electronic devices under the impact of EMP, one is through experimental tests, and the other is by theoretical analysis. The theoretical analysis is very essential because precise test results are difficult to get since the restrictions of complicated semiconductor structures and test environment.
In this thesis, we will investigate the thermal effect of LDMOSFET under the impact of an EMP theoretically. By applying Finite Element Method (FEM) in the transient electro-thermal analysis, we can get the thermal effect of LDMOSFET and further evaluate the possibility of thermal breakdown caused by different EMPs. The thesis will be formed as follows:
In the second chapter, we will introduce the physical structure and characteristics of a typical LDMOSFET with its physical model given.
In the third chapter, the semiconductor operation equations for two-dimensional simulation, which are stiff, coupled and nonlinear partial differential, are set up, with the parameters of these equations discussed.
In the fourth chapter, hybrid time-domain finite element method (FEM) is employed for our mathematical treatment.
In the fifth chapter, thermal effect of LDMOSFET under signal electromagnetic pulse is simulated. Temperature rises are compared for different pulse parameters. We will define the thermal breakdown zone to evaluate the possibility of thermal breakdown caused by an EMP but for different parameters.
In the sixth chapter, thermal accumulation effects in LDMOSFET under periodic electromagnetic pulses are simulated where thermal accumulation effects are compared for different periodicity of the repeated pulses.
由于横向双扩散金属氧化物场效应晶体管(LDMOSFET)具有良好的电学特性和射频表现,并且可以与标准CMOS工艺完全兼容,因而在射频集成电路中得到了越来越广泛的应用[1]-[5]。
然而,作为功率器件,器件自身的热效应越来越成为影响器件正常工作的重要因素。在某些情况下,半导体器件或电路必须工作在电磁脉冲(EMP)干扰之下。特别地,当一个高功率电磁脉冲(HEMP)突然注入器件时,会导致器件内部电场强度过大或温度升高超过正常工作阈值温度,从而产生电击穿或热击穿。为了确定EMP参数对半导体器件的干扰及损伤程度,通常情况下可以采用试验测试和理论研究的方法。但是由于受到器件、系统的复杂性和电磁环境诸多因素的限制,准确的试验非常困难,因此有必要从理论上研究电磁脉冲对电子系统的破坏机理,而电子系统的基本组成部分是半导体器件,所以首先要对半导体器件进行研究。
本文将运用理论研究的方法分析LDMOSFET在电磁脉冲影响下的热效应。通过有限元方法对典型LDMOSFET进行瞬态电-热建模仿真,获得电磁脉冲影响下LDMOSFET器件的热效应,以分析不同参数电磁脉冲对器件的干扰和损伤程度。本文的主要研究内容如下:
第二章将分析LDMOSFET的基本结构及特点。对典型的LDMOSFET进行器件结构建模。
第三章将介绍半导体器件二维仿真的理论基础,包括器件参数和模型建立所需的基本方程和边界条件;建立二维稳态和瞬态模型下半导体器件所满足的刚性、耦合、非线性偏微分方程组,并对边界条件及参数的确定进行讨论。
第四章将介绍利用时域有限元方法进行器件数值模拟的步骤,建立基于时域有限元方法的二维稳态和瞬态的半导体器件数值模拟矩阵,然后运用FORTRAN语言对方程组进行数值计算。
第五章将对单个电磁脉冲作用下LDMOSFET的热效应进行讨论,比较不同脉冲参数情况下器件温度升高的不同情况,并定义热击穿区域(Thermal Breakdown Zone)以衡量不同电磁脉冲对器件的损伤程度。
第六章将对周期电磁脉冲作用下LDMOSFET的热累积效应进行分析,比较不同周期情况下器件热累积效应的严重程度。
第七章将对本文的研究工作进行系统总结。
Due to the rapid development of radio frequency integrated circuit, the demands of RF power devices in consumer electronics, mobile communications and military radars are growing rapidly now. The applications of current RF power devices are limited because of the high cost and complicated technology, so new RF power devices with compatible technology and low fabrication cost are badly needed to satisfy the demands of the market.
Lateral double-diffused MOSFET (LDMOSFET), compatible with standard silicon CMOS technology, has excellent electronic characteristics and RF performance. So it is used more and more widely in RFIC industry nowadays [1]-[5]. But as power device, the thermal effect of LDMOSFET itself has become an increasingly important issue that influences its performance. In some situations, semiconductor devices and circuits must operate under possible impact of an electromagnetic pulse (EMP). In particular, as a high-power EMP is suddenly injected into a semiconductor device, electrical or thermal breakdown can be definitely caused. Normally, there are two methods to investigate breakdown phenomena of electronic devices under the impact of EMP, one is through experimental tests, and the other is by theoretical analysis. The theoretical analysis is very essential because precise test results are difficult to get since the restrictions of complicated semiconductor structures and test environment.
In this thesis, we will investigate the thermal effect of LDMOSFET under the impact of an EMP theoretically. By applying Finite Element Method (FEM) in the transient electro-thermal analysis, we can get the thermal effect of LDMOSFET and further evaluate the possibility of thermal breakdown caused by different EMPs. The thesis will be formed as follows:
In the second chapter, we will introduce the physical structure and characteristics of a typical LDMOSFET with its physical model given.
In the third chapter, the semiconductor operation equations for two-dimensional simulation, which are stiff, coupled and nonlinear partial differential, are set up, with the parameters of these equations discussed.
In the fourth chapter, hybrid time-domain finite element method (FEM) is employed for our mathematical treatment.
In the fifth chapter, thermal effect of LDMOSFET under signal electromagnetic pulse is simulated. Temperature rises are compared for different pulse parameters. We will define the thermal breakdown zone to evaluate the possibility of thermal breakdown caused by an EMP but for different parameters.
In the sixth chapter, thermal accumulation effects in LDMOSFET under periodic electromagnetic pulses are simulated where thermal accumulation effects are compared for different periodicity of the repeated pulses.
引文
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[3] J. Luo, G. Cao and S. N. Ekkanath,“A high performance RF LDMOSFET in thin film SOI technology with step drift profile,”Solid-State Electronics, vol. 47, no. 11, pp. 1937-1941, 2003.
[4] Y. Tan, M. Kumar, J. K. O. Sin, J. Cai, and J. Lau,“A LDMOS technology compatible with CMOS and passive components for integrated RF power amplifiers,”IEEE Electron Device Lett., vol. 21, no. 2, pp. 82-84, Feb. 2000.
[5] M Kumar, Y. Tan, J. K. O. Sin and J. Cai,“An SOI LDMOS/CMOS/BJT technology for integrated power amplifiers used in wireless transceiver applications,”IEEE Electron Device Lett., vol. 22, no. 3, pp. 136-138, Mar. 2001.
[6] R. Menozzi and A. C. Kingswood,“A new technique to measure the thermal resistance of LDMOS transistors,”IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 515-521, Sep. 2005.
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[9] V. Khemka, V. Parthasarathy, R. H. Zhu, A. Bose,“A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET,”IEEE Electron Device Lett., vol. 25, no. 10, pp. 705-707.
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[15] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, A. Bose and R. Ida,“A double RESURF LDMOS with drain profile engineering for improved ESD robustness,”IEEE Electron Device Lett., vol. 23, no. 4, pp. 212-214, Apr. 2002.
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[2] S. M. Xu, K. P. Gan, G. S. Samudra, Y. C. Liang and J. K. O. Sin,“120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit,”IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1980-1985, Oct. 2000.
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[4] Y. Tan, M. Kumar, J. K. O. Sin, J. Cai, and J. Lau,“A LDMOS technology compatible with CMOS and passive components for integrated RF power amplifiers,”IEEE Electron Device Lett., vol. 21, no. 2, pp. 82-84, Feb. 2000.
[5] M Kumar, Y. Tan, J. K. O. Sin and J. Cai,“An SOI LDMOS/CMOS/BJT technology for integrated power amplifiers used in wireless transceiver applications,”IEEE Electron Device Lett., vol. 22, no. 3, pp. 136-138, Mar. 2001.
[6] R. Menozzi and A. C. Kingswood,“A new technique to measure the thermal resistance of LDMOS transistors,”IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 515-521, Sep. 2005.
[7] J. M. Collantes, P. Bouysse and R. Quere,“Characterising and modelling thermal behaviour of radio-frequency power LDMOS transistors,”Electronics Lett., vol. 34, no. 14, pp. 1428-1430, Jul. 1998.
[8] P. Moens and G. Van Den Bosch,“Characterization of total safe operating area of lateral DMOS transistors,”IEEE Trans. Device and Materials Reliability, vol. 6, no. 3, pp. 349-357, Sep. 2006.
[9] V. Khemka, V. Parthasarathy, R. H. Zhu, A. Bose,“A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET,”IEEE Electron Device Lett., vol. 25, no. 10, pp. 705-707.
[10] W. A. Radasky, C. E. Baum, and M. W. Wik,“Introduction to the special issue on high-power electromagnetics (HPEM) and intentional electromagnetic interference (IEMI),”IEEE Trans. Electromagnetic Compatibility, vol. 46, no. 3, pp. 314-321, 2004.
[11] F. Sabath, M. Backstrom, B. Nordstrom, D. Serafin, A. Kaiser, B. A. Kerr, and D. Nitsch,“Overview of four European high-power microwave narrow-band test facilities,”IEEE Trans. Electromagnetic Compatibility, vol. 46, no.3, pp. 329-334, Aug. 2004.
[12] W. D. Prather, C. E. Baum, R. J. Torres, F. Sabath, and D. Nitsch,“Survey of worldwide high-power wideband capabilities,”IEEE Trans. Electromagnetic Compatibility, vol. 46, no.3, pp. 335-344, Aug. 2004.
[13] M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner,“Analysis of lateral DMOS power devices under ESD stress conditions,”IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2128-2137, Nov. 2000.
[14] K. Kawamoto, S. Takahashi, S. Fujino and I. Shirakawa,“A no-snapback LDMOSFET with automotive ESD endurance,”IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2047-2053, Nov. 2002.
[15] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, A. Bose and R. Ida,“A double RESURF LDMOS with drain profile engineering for improved ESD robustness,”IEEE Electron Device Lett., vol. 23, no. 4, pp. 212-214, Apr. 2002.
[16] M. D. Ker and K. H. Lin,“Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design,”IEEE Electron Device Lett., vol. 25, no. 9, pp. 640-642, Sep. 2004.
[17] S. H. Voldman, ESD: Physics and Devices, John Wiley & Sons, Ltd., 2004.
[18] S. H.Voldman, ESD: Circuits and Devices, John Wiley & Sons, 2005.
[19] S. H. Voldman, ESD: RF Technology and Circuits, John Wiley & Sons, Ltd, 2006.
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