电磁脉冲冲击下无源结构的瞬态电热力耦合一体化分析
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摘要
在需求和技术发展的推动下,集成电路的集成度和互连的复杂程度正在不断地提高。同时,晶圆级全局互连,键合线等三维互连技术的实际性能和可靠性在现代电子器件和设备的应用中正显示出越来越重要的作用。尤其是当它们应用于高温高功率环境下,它们的可靠性和电磁兼容性正在受到越来越多的关注。
在受到ESD脉冲冲击或在高功率脉冲环境下,当电压或电场超过了介质或互连线的击穿阈值的时候,损坏就很容易发生。从物理上来进行分析的话,一个击穿过程实质上是一个电热力相互耦合的非线性的瞬态的过程。这个过程的一些物理参量还依赖于频率,温度,电场强度甚至是机械强度。因此,准确地估计和描述无源器件甚至是有源器件的击穿过程是一件非常有挑战性的事情。
本文中,为获得不同电流或电压波形的ESD脉冲和EMP脉冲入射时晶圆级全局互连,键合线的温度和结构响应,针对这两个互连结构,我们进行了全面的瞬态电热力耦合研究。为准确仿真电场,热场和应力场之间的相互作用,我们采用了混合时域有限元数值方法,编写了相应的电热力分析软件包,在算法中,所有材料的电导率、热导率、热膨胀系数和杨氏模量随温度的变化都进行了合适的处理。通过一些瞬态的电热、热力响应的例子,我们将算法的结果和一些已发表的论文的结果进行了比较,良好的吻合度使算法的正确性已经得到了局部的验证。
在此基础上,我们对ESD电流脉冲、EMP脉冲的波形参数,晶圆级全局互连和键合线结构参数,各种材料的物理参数对脉冲冲击下瞬态热,应力响应的影响进行了细致的研究。这些研究结果为芯片和设备的电磁保护甚至是避免有意的电磁脉冲冲击提供了一些有用的基本信息。
Advances in requirements and technology have resulted in a continuous increase in circuit density and interconnect complexity. Consequently, the practical behavior of three-dimensional interconnects, such as inter-wafer interconnects and wire bondings, and their reliability are increasingly important for the operational performance and electromagnetic compatibility (EMC) compliance of modern electronic devices and systems, especially when operating in high-power or high-temperature environments.
In an environment with high power pulses, breakdown can be easily caused when the applied voltage or electric field exceeds the breakdown thresholds of dielectrics or interconnects. Physically, a breakdown event can be considered as a nonlinear and transient process in which electrical, thermal, and mechanical interactions are coupled to one another, and some constitutive parameters may depend on frequency, temperature, electric field strength, and even applied mechanic strength. Hence, it is a challenging task to accurately predict and characterize the breakdown process in a passive as well as an active electronic device or system.
A comprehensive electro-thermo-mechanical transient investigation is carried out to characterize time-dependent thermal and mechanical responses of inter-wafer interconnects and metal wire bonding interconnects, as they suffer from the impact of an electrostatic discharge (ESD) current or an electromagnetic pulse (EMP) with different current or voltage waveforms. In our mathematical implementation, a hybrid time-domain finite element method is applied to simulate mutual interactions among electrical, thermal, and mechanical fields, with all nonlinearities of temperature-dependent electrical conductivities, thermal conductivities, thermal expansion coefficients, and even the Young’s modulus of materials being treated appropriately. The developed algorithm is partially validated by computing transient temperature and thermal stress of other interconnects with good agreement with reference results. Parametric studies are performed to show the effects of ESD and EMP waveform parameters, geometrical and physical parameters of inter-wafer interconnects and various wire bonding interconnects on their transient thermal and mechanical responses, thus providing basic information for their electromagnetic protection so as to suppress the impact of an intentional EMP.
在受到ESD脉冲冲击或在高功率脉冲环境下,当电压或电场超过了介质或互连线的击穿阈值的时候,损坏就很容易发生。从物理上来进行分析的话,一个击穿过程实质上是一个电热力相互耦合的非线性的瞬态的过程。这个过程的一些物理参量还依赖于频率,温度,电场强度甚至是机械强度。因此,准确地估计和描述无源器件甚至是有源器件的击穿过程是一件非常有挑战性的事情。
本文中,为获得不同电流或电压波形的ESD脉冲和EMP脉冲入射时晶圆级全局互连,键合线的温度和结构响应,针对这两个互连结构,我们进行了全面的瞬态电热力耦合研究。为准确仿真电场,热场和应力场之间的相互作用,我们采用了混合时域有限元数值方法,编写了相应的电热力分析软件包,在算法中,所有材料的电导率、热导率、热膨胀系数和杨氏模量随温度的变化都进行了合适的处理。通过一些瞬态的电热、热力响应的例子,我们将算法的结果和一些已发表的论文的结果进行了比较,良好的吻合度使算法的正确性已经得到了局部的验证。
在此基础上,我们对ESD电流脉冲、EMP脉冲的波形参数,晶圆级全局互连和键合线结构参数,各种材料的物理参数对脉冲冲击下瞬态热,应力响应的影响进行了细致的研究。这些研究结果为芯片和设备的电磁保护甚至是避免有意的电磁脉冲冲击提供了一些有用的基本信息。
Advances in requirements and technology have resulted in a continuous increase in circuit density and interconnect complexity. Consequently, the practical behavior of three-dimensional interconnects, such as inter-wafer interconnects and wire bondings, and their reliability are increasingly important for the operational performance and electromagnetic compatibility (EMC) compliance of modern electronic devices and systems, especially when operating in high-power or high-temperature environments.
In an environment with high power pulses, breakdown can be easily caused when the applied voltage or electric field exceeds the breakdown thresholds of dielectrics or interconnects. Physically, a breakdown event can be considered as a nonlinear and transient process in which electrical, thermal, and mechanical interactions are coupled to one another, and some constitutive parameters may depend on frequency, temperature, electric field strength, and even applied mechanic strength. Hence, it is a challenging task to accurately predict and characterize the breakdown process in a passive as well as an active electronic device or system.
A comprehensive electro-thermo-mechanical transient investigation is carried out to characterize time-dependent thermal and mechanical responses of inter-wafer interconnects and metal wire bonding interconnects, as they suffer from the impact of an electrostatic discharge (ESD) current or an electromagnetic pulse (EMP) with different current or voltage waveforms. In our mathematical implementation, a hybrid time-domain finite element method is applied to simulate mutual interactions among electrical, thermal, and mechanical fields, with all nonlinearities of temperature-dependent electrical conductivities, thermal conductivities, thermal expansion coefficients, and even the Young’s modulus of materials being treated appropriately. The developed algorithm is partially validated by computing transient temperature and thermal stress of other interconnects with good agreement with reference results. Parametric studies are performed to show the effects of ESD and EMP waveform parameters, geometrical and physical parameters of inter-wafer interconnects and various wire bonding interconnects on their transient thermal and mechanical responses, thus providing basic information for their electromagnetic protection so as to suppress the impact of an intentional EMP.
引文
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[3] Kyuchul Chong, Xi Zhang, King-Ning Tu, Daquan Huang, Mau-Chung Chang, and Ya-Hong Xie,“Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC),”IEEE Trans. Electron Device, vol. 52, no. 11, pp. 2440-2446, Nov. 2005.
[4] Afsahi, A., Rael, J.J., and Behzad, A. etc.“A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13μm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit,”IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1101-1118, May 2008.
[5] Yo-Sheng Lin,“An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-chip (SoC) applications,”IEEE Trans. Electron Device, vol. 52, no. 7, pp. 1442-1451, Jul. 2005.
[6] Harrer, H., Katopis, G.A., and Becker, W.,“Feature - From chips to systems via packaging - A comparison of IBM's mainframe servers,”IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 32-41, 2006.
[7] Lishchynska, M., O'Mahony, C., Slattery, O., Wittler, O., and Walter, H.,“Evaluation of Packaging Effect on MEMS Performance: Simulation and Experimental Study,”IEEE Trans. Advanced Packaging , vol. 30, no. 4, pp. 629-635, Nov. 2007.
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[13]谭志良,刘尚合,林永涛,国海广,“电子设备高功率电磁辐照效应”,高电压技术,2005,31(10): 33～35。
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