基于FPGA平台数字信道化接收机的开发与研制
摘要
数字信道化接收机是一种具有截获概率大、测频精度高、动态范围大,灵敏度高等优点的侦察接收机,在复杂的电磁环境中,具有极好的处理多个同时到达信号的能力。FPGA在速度、体积方面和设计的灵活性上,都能适应现代电子战信号处理系统的要求,基于FPGA的数字信道化接收机能够充分发挥FPGA硬件资源丰富的特点,并且易于实现并行处理,从而大幅度提高系统的处理速度。
本文研究的内容来源于某射频干涉定位系统信号处理领域内的一个预研专题。针对数字信道化接收机的FPGA实现,本文对相关的技术进行了研究,这其中包括：信号采样理论、数字下变频原理、数字正交混频技术,信号抽取理论等。在此基础上对高速数据流数字下变频器的设计以及实现进行了专门的阐述并给出了相关的仿真报告。最后结合系统要求,在现有硬件平台上进行了数字信道化接收机的FPGA实现,并通过系统仿真及调试验证了方案的正确性。
The channelized digital receiver has quite many advantages, such as high ability of probability capturing、high accuracy of frequency detection、wide range of dynamic, high sensitivity, it can simultaneously process multi-signal in a complex electromagnetic environment.Considering all the aspects of the speed and volume or the agility of design, FPGA can meet the need of modern electronic warface signal processing system. The Channelized digital receiver based on FPGA can make full use of the advantage of FPGA's abundant resource, easiness to implement parallel processing to speed the system process.
The content of this paper is about the RF interference positioning system signal processing. According how to implement channelized digital receiver under the FPGA platform, we studied the related technology:including the theories on signal sampling、digital down converter、Digital orthogonal frequency mixing, Signal decimation and so on. Under this foundation we gave detailed explanations and a simulation report about how to achieve the design of High-speed data streams digital down-converter. Finally, according to the system's requirements, we used the existing hadware to implement the channelized digital receiver in the FPGA platform, and through the system simulation and testing verified the validity of the scheme.
本文研究的内容来源于某射频干涉定位系统信号处理领域内的一个预研专题。针对数字信道化接收机的FPGA实现,本文对相关的技术进行了研究,这其中包括：信号采样理论、数字下变频原理、数字正交混频技术,信号抽取理论等。在此基础上对高速数据流数字下变频器的设计以及实现进行了专门的阐述并给出了相关的仿真报告。最后结合系统要求,在现有硬件平台上进行了数字信道化接收机的FPGA实现,并通过系统仿真及调试验证了方案的正确性。
The channelized digital receiver has quite many advantages, such as high ability of probability capturing、high accuracy of frequency detection、wide range of dynamic, high sensitivity, it can simultaneously process multi-signal in a complex electromagnetic environment.Considering all the aspects of the speed and volume or the agility of design, FPGA can meet the need of modern electronic warface signal processing system. The Channelized digital receiver based on FPGA can make full use of the advantage of FPGA's abundant resource, easiness to implement parallel processing to speed the system process.
The content of this paper is about the RF interference positioning system signal processing. According how to implement channelized digital receiver under the FPGA platform, we studied the related technology:including the theories on signal sampling、digital down converter、Digital orthogonal frequency mixing, Signal decimation and so on. Under this foundation we gave detailed explanations and a simulation report about how to achieve the design of High-speed data streams digital down-converter. Finally, according to the system's requirements, we used the existing hadware to implement the channelized digital receiver in the FPGA platform, and through the system simulation and testing verified the validity of the scheme.
引文
[1]James T.宽带数字接收机[M].杨小牛等译.北京：电子工业出版社,2002.
[2]戈稳.雷达接收机技术.北京：电子工业出版社,2005.4.
[3]杨小牛,楼才义,徐建良著.软件无线电原理与应用.电子工业出版社,2001.1-74.
[4]丁玉美,高西全.数字信号处理(第二版).西安电子科技大学出版社,2001.
[5]R.E.克劳切,LR.拉宾纳著.多采样率数字信号处理.人民邮电出版社,1988.
[6]Fudge J, Legako M, Sehreiner C. An approach to efficient wideband digital downconversion[c]//Proc. ICSPAT. Toronto, Canada,1998:713-717.
[7]Wayne Wolf(美).基于FPGA的系统设计.北京：机械工业出版社(影印),2005.
[8]李勇,徐震.Matlab辅助现代工程数字信号处理.西安：西安电子科技大学出版社,2002.
[9]Uwe Meyer-base著.刘凌译.数字信号处理的FPGA实现(第二版).北京：清华大学出版社,2006.6.
[10]National Semiconductor. ADC08D1000 High Performance, Low Powe, Dual 8-bit,1GSPS A/D Converter Data Sheet, December 2005.
[11]XC4VSX55TM-11FF1148DGQ_I Xilinx Data Sheet:www. xilinx. com,2002.
[12]赵国庆.雷达对抗原理.西安：西安电子科技大学出版社,1999.10.
[13]Rosel G, Fliege N J. Transmultiplexer filter banks with extremely low crosstalk and intersymbol interference. IEEE.1995:1448-1451.
[14]侯伯亨,顾新.VHDL硬件描述语言与数字逻辑电路设计.西安：西安电子科技大学出版社，1997.
[15]辛明.一种高效数字信道化接收方法[J].电子对抗技术,2004,19(5)：10-13.
[16]付永庆,李预.基于多相滤波器的信道化接收机及其应用研究.VOL.20NO.5.2004：517-520.
[17]张嵘.宽带高灵敏度数字接收机：[博士学位论文],成都：电子科技大学,2002.
[18]吴地金.无线通信中数字中频接收系统研究.浙江杭州：浙江大学,2004,23.34.
[19]陈勇.基于FPGA实现高速专用数字下变频器,四川成都：电子科技大学,2005,7-24.
[20]戴绍港,张福洪.软件无线电信道化接收机的FPGA实现方案.杭州电子工业学院学报,2004,24(4)：47-51.
[21]何伟.新型宽带数字接收机[PHD].成都：电子科学技术大学,2005.
[22]Ren G H, zhao Y Q, Wu Z L. Channelized receiver platform of SDR based of FPGAS. IEEE.2003:840-843.
[23]Madihally J N, Allen M P. Design and applications of uniform digital bandpass filter banks. IEEE 1978:499-503.
[24]Youngbeom, Jang, Sejung Yang. Low-power CSD linear phase FIR filter structure using vertical common sub-expression.2002, Electronics Letters Volume 38, Issue 15:777-779.
[25]Lillington J. Comparison of wideband channelisation architectures. International signal processing conference, Dallas,2003:1-6.
[26]MITOLA J. The software radio architecture [J]. IEEE Communication Magazine, 1995,33(5):26-38.
[27]HARRIS F J, DICK C, RJCE M, et al. Digital receivers and tansmitters using polyphase filter banks for wireless communication[J]. IEEE Trans on Microwave Theory and Techniques,2003,51(4):1395-1412.
[28]徐文明,刘渝.FPGA在数字信道化接收机中的应用.雷达与对抗,2005(1)：50-54.
[29]陈永其,黄爱苹,严文忠.一种宽带中频数字信道化侦察接收机方案.电子对抗技术,2003,33(8)：34-35.
[30]胡来招.雷达侦察接收机设计[M].北京：国防工业出版社,2000.
[31]蔡德林,郑生华.雷达数字接收机实现[C].第八届全国雷达学术年会论文集,2003.
[32]邱兆坤,马云,陈曾平.DDC在雷达正交接收机中的应用[J].现代雷达,2004,26(10)：44-47.
[33]郑立岗.数字接收机若干技术研究及系统实现,四川成都：电子科技大学,2004，13.66.
[34]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具-Xilinx ISE使用详解.人民邮电出版社,2005.
[35]顾耀平译.宽带接收机数字技术.1996年5月,电子战文库15.
[36]史学书,陆海峰.软件无线电系统中NCO的设计与实现.现代电子技术200515第206期：6-9.
[37]高志成.电子侦察中的信号采集技术研究[PHD].成都：电子科学技术大学,2000.7.
[38]Dempster, A. G. Macleod, M. D. Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Circuits and Systems,1995, Volume 42, Issue 9: 569-577.
[39]Hyeong-Ju Kang, In-Cheol Park, FIR filter synthesis algorithms for minimizing the delay and the number of adders, IEEE Circuits and Systems,2001, Volume 48, Issue 8:770-777.
[40]马亮.信道化数字接收机硬件实现技术研究[PHD].成都：电子科技大学,2006.
[41]李双田,李昌立,陈丹平,袁津润.短波数字接收机的算法研究和DSP实现.电子学报,1999.7 VOL 27 NO7：27-30.
[2]戈稳.雷达接收机技术.北京：电子工业出版社,2005.4.
[3]杨小牛,楼才义,徐建良著.软件无线电原理与应用.电子工业出版社,2001.1-74.
[4]丁玉美,高西全.数字信号处理(第二版).西安电子科技大学出版社,2001.
[5]R.E.克劳切,LR.拉宾纳著.多采样率数字信号处理.人民邮电出版社,1988.
[6]Fudge J, Legako M, Sehreiner C. An approach to efficient wideband digital downconversion[c]//Proc. ICSPAT. Toronto, Canada,1998:713-717.
[7]Wayne Wolf(美).基于FPGA的系统设计.北京：机械工业出版社(影印),2005.
[8]李勇,徐震.Matlab辅助现代工程数字信号处理.西安：西安电子科技大学出版社,2002.
[9]Uwe Meyer-base著.刘凌译.数字信号处理的FPGA实现(第二版).北京：清华大学出版社,2006.6.
[10]National Semiconductor. ADC08D1000 High Performance, Low Powe, Dual 8-bit,1GSPS A/D Converter Data Sheet, December 2005.
[11]XC4VSX55TM-11FF1148DGQ_I Xilinx Data Sheet:www. xilinx. com,2002.
[12]赵国庆.雷达对抗原理.西安：西安电子科技大学出版社,1999.10.
[13]Rosel G, Fliege N J. Transmultiplexer filter banks with extremely low crosstalk and intersymbol interference. IEEE.1995:1448-1451.
[14]侯伯亨,顾新.VHDL硬件描述语言与数字逻辑电路设计.西安：西安电子科技大学出版社，1997.
[15]辛明.一种高效数字信道化接收方法[J].电子对抗技术,2004,19(5)：10-13.
[16]付永庆,李预.基于多相滤波器的信道化接收机及其应用研究.VOL.20NO.5.2004：517-520.
[17]张嵘.宽带高灵敏度数字接收机：[博士学位论文],成都：电子科技大学,2002.
[18]吴地金.无线通信中数字中频接收系统研究.浙江杭州：浙江大学,2004,23.34.
[19]陈勇.基于FPGA实现高速专用数字下变频器,四川成都：电子科技大学,2005,7-24.
[20]戴绍港,张福洪.软件无线电信道化接收机的FPGA实现方案.杭州电子工业学院学报,2004,24(4)：47-51.
[21]何伟.新型宽带数字接收机[PHD].成都：电子科学技术大学,2005.
[22]Ren G H, zhao Y Q, Wu Z L. Channelized receiver platform of SDR based of FPGAS. IEEE.2003:840-843.
[23]Madihally J N, Allen M P. Design and applications of uniform digital bandpass filter banks. IEEE 1978:499-503.
[24]Youngbeom, Jang, Sejung Yang. Low-power CSD linear phase FIR filter structure using vertical common sub-expression.2002, Electronics Letters Volume 38, Issue 15:777-779.
[25]Lillington J. Comparison of wideband channelisation architectures. International signal processing conference, Dallas,2003:1-6.
[26]MITOLA J. The software radio architecture [J]. IEEE Communication Magazine, 1995,33(5):26-38.
[27]HARRIS F J, DICK C, RJCE M, et al. Digital receivers and tansmitters using polyphase filter banks for wireless communication[J]. IEEE Trans on Microwave Theory and Techniques,2003,51(4):1395-1412.
[28]徐文明,刘渝.FPGA在数字信道化接收机中的应用.雷达与对抗,2005(1)：50-54.
[29]陈永其,黄爱苹,严文忠.一种宽带中频数字信道化侦察接收机方案.电子对抗技术,2003,33(8)：34-35.
[30]胡来招.雷达侦察接收机设计[M].北京：国防工业出版社,2000.
[31]蔡德林,郑生华.雷达数字接收机实现[C].第八届全国雷达学术年会论文集,2003.
[32]邱兆坤,马云,陈曾平.DDC在雷达正交接收机中的应用[J].现代雷达,2004,26(10)：44-47.
[33]郑立岗.数字接收机若干技术研究及系统实现,四川成都：电子科技大学,2004，13.66.
[34]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具-Xilinx ISE使用详解.人民邮电出版社,2005.
[35]顾耀平译.宽带接收机数字技术.1996年5月,电子战文库15.
[36]史学书,陆海峰.软件无线电系统中NCO的设计与实现.现代电子技术200515第206期：6-9.
[37]高志成.电子侦察中的信号采集技术研究[PHD].成都：电子科学技术大学,2000.7.
[38]Dempster, A. G. Macleod, M. D. Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Circuits and Systems,1995, Volume 42, Issue 9: 569-577.
[39]Hyeong-Ju Kang, In-Cheol Park, FIR filter synthesis algorithms for minimizing the delay and the number of adders, IEEE Circuits and Systems,2001, Volume 48, Issue 8:770-777.
[40]马亮.信道化数字接收机硬件实现技术研究[PHD].成都：电子科技大学,2006.
[41]李双田,李昌立,陈丹平,袁津润.短波数字接收机的算法研究和DSP实现.电子学报,1999.7 VOL 27 NO7：27-30.