SrTiO_3基阻变存储器的制备和性能研究
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摘要
阻变存储(RRAM)以其在存储密度和存储速度上的独特优势,被认为是颇具潜力的下一代非易失性存储技术。然而阻变的微观机制一直不明晰,这成为RRAM存储应用的主要障碍。本论文采用脉冲激光沉积技术(PLD)制备了SrTiO3(STO)基电阻开关薄膜材料,通过改变金属电极和引入介质层的方法,系统研究了阻变器件的电阻开关特性,及其在新原理器件中的应用。本论文主要内容包括以下几个方面：
1. Au/STO/Ti存储器件的制备和电阻开关性能研究
以STO薄膜为阻变材料,选取具有不同功函的金属Au(5.1eV)和Ti(4.3eV)作为上下电极制备了Au/STO/Ti结构的存储器件。电学特性研究表明,STO/Ti之间形成欧姆接触,而Au/STO之间为肖特基接触。在±2.5V的偏压范围内,存储器件表现出逆时针双极电阻开关行为,对I-V和C-V曲线的分析表明阻变源于Au/STO界面肖特基势垒宽度或高度的改变,该界面势垒的改变是由缺陷能级的电荷俘获/释放诱导的；在经历了负极性的电形成电压操作后,器件在同样的±2.5V偏压范围内呈现出顺时针双极电阻开关行为,电学特性分析表明该阻变源于氧空位迁移诱导的氧化还原反应。薄膜内缺陷分布的不同导致了这两种不同特征的双极电阻开关行为。
2. Au/STO/Pt存储器件的电阻开关性能研究及其在实质蕴涵(IMP)逻辑运算中的应用
(1)由于金属/氧化物界面对存储器件的开关特性有重要影响,选择高功函Pt(5.6eV)为下电极制备了Au/STO/Pt结构的存储器。XPS分析说明STO薄膜所含元素价态分别为Sr2+、Ti4+和O2-,并且有氧空位存在。存储器件的初始态表现出整流行为,在经历过负极性的电形成偏压(约-6～-8V)之后,器件表现出单极或双极性电阻开关行为,其开关极性依赖于电形成过程中所设限制电流的大小。当限制电流为1mA,器件表现出双极电阻开关行为；当限制电流为10mA,表现出单极开关行为,并且两种极性之间可以相互转换。该现象表明不同的限制电流,器件内部形成的缺陷不同。对I-V特性的分析表明双极电阻开关是由于Au/STO界面处肖特基势垒的变化引起的；而单极电阻开关是由于缺陷构成的导电丝的形成与破裂致使的。对器件的非易失性研究表明,单极开关的高、低阻态均具有很好的保持能力,两周时间之后电阻值仍无较大的改变,但双极开关的电阻态仅能保持几个小时。
(2)IMP逻辑的研究还处于初始阶段,目前还未见单极忆阻器实现IMP“状态”逻辑的报道。本文选择具有单极开关特性的Au/STO/Pt器件为忆阻器构成了IMP逻辑电路,并通过理论模拟计算,探索IMP逻辑运算中电压、电流等参数设置的特点,以及逻辑运算的稳定性。该单极忆阻器具有较大的开关比值(大于1000),且在低阻态呈现线性Ⅰ-V关系,较小的调制因子(1.2)表明由于串联电阻(RG)的引入导致的开关比值的退偏非常弱,这证明IMP的可靠性被有效增强了。但单极开关阈值电压的离散性会影响IMP运算的重复性,计算表明通过选择合适的串联电阻(RG,500Ω)能减小阈值电压不稳定对IMP运算的影响；但彻底解决该问题,应优化忆阻器结构以使开关电压稳定在较小的范围内。
3. Au/NiO/STO/Pt存储单元的电学性能研究
界面势垒在电阻开关中起着重要作用,在金属/氧化物间插入非常薄的介质层将改变界面性质,进而影响存储器的电阻开关性质,所以本文采用PLD技术沉积了p-NiO/n-STO异质结,并制备了Au/NiO/STO/Pt结构的阻变存储器件。该器件的电学测试结果如下：
(1)在电形成过程中设置较小的限制电流,由于界面势垒的存在,器件表现出双极电阻开关行为,并且他们的回线方向可以在顺时针和逆时针间可逆转换；通过对I-V曲线的拟合发现,高阻态和低阻态分别对应肖特基整流和隧穿机制,进一步分析表明,逆时针(顺时针)双极开关是由于NiO/STO上界面处p-n结势垒(STO/Pt下界面肖特基势垒)的改变引起的,该界面势磊的改变由电荷诱捕效应导致。
(2)在电形成过程中若设置较大的限制电流(10mA),界面势垒消失,器件表现单极电阻开关行为；负偏压下,单极开关能反复切换,但正偏压下,开关仅重复约4-7个周期便消失。其原因是不同极性的偏压驱使氧空位向相反方向移动,使得开关发生的位置随之上下移动。负偏压时,由缺陷组成的导电细丝断开和复合的位置在STO薄膜内；正偏压下,导电细丝的断开位置向NiO/STO上界面移动,同时氧离子将NiO薄膜中的Ni导电丝氧化,致使开关现象消失。
Resistance random access memory (RRAM) is an intriguing approach for next generation non-volatile storage, owing to its attractive combination of density and speed. However, the microscopic physical mechanism of RRAM has been controversial, which became a major obstacle to potential applications. In this dissertation, the RRAM memory cells based on peroskite oxide SrTiO3(STO) are prepared. By means of changing the metal electrode and the introduction of a dielectric layer, the resistance switching characteristics are investigated, and the new principle of logic devices is developed. The main results are as follows:
1. Study on Au/STO/Ti memory cells
The Au/STO/Ti memory cells are prepared. The electrical measurements show that the contact on STO/Ti interface is ohmic, while the contact on the Au/STO interface is Schottky. In the range of±2.5V, the memory showes a bipolar resistance switching with counter clockwise polarity. The analyses on I-V and C-V data show that the resistance change is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states. Netative bias applied to memory can induce a bipolar resistance switching with clockwise polarity which comes from redox reactions induced by the migration of oxygen vacancies. These two bipolar swithing with opposite polarity is due to the different distribution of defect states in STO films.
2. Study on Au/STO/Pt memory cells and its application in new principle devices
(I) The metal/oxide interface has crucial effect on the switching properties of memory cells. Pt as bottom electrodes and the electrical characteristics of Au/STO/Pt are investigated. XPS analysis shows that the valence states of contained elements in STO films are Sr2+, Ti4+, O2-,and there exists a certain amount of oxygen vacancies. The initial state of the Au/STO/Pt cell show rectifying characteristics due to Schottky contact between Au and n-STO. The memory, applied a large reverse bias (about-6～-8V) with1mA compliance current (CC), showes bipolar switching behavior. However, if the CC is set to10mA, the memory will show unipolar switching behavior. Both types of switching with different polarity are interchangeable. The polarity dependence of the CC is due to different current in forming process resulting in the formation of different defect density. Bipolar resistance switching is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states, and unipolar switching is due to the formation and rupture of conductive filament. The non-volatile properties show that the resistance state in unipolar switching has continued for two weeks without significant change, while the resistance state in bipolar switching would be changed after a few hours.
(2) The study on IMP logic is still in an initial stage, and there is no report about IMP logic enabled by unipolar memristors. In this work, the IMP logic circuit is formed by Au/STO/Pt unipolar switch memory. By means of the combination of theoretical simulation and experiment, it is explored that the electric parameters of voltage and current to obtain IMP logic and the stability of the device. This unipolar memristors have a large switching ratio (>1000), linear I-V relationship in low resistance state, and modulation factor of1.2showing that the weak depolarization of switch. These rusults prove that the reliability of IMP is effectively enhanced. However, there is a large variation in set and reset threshold voltage for the Au/STO/Pt unipolar switching device, which could impact the reproducibility of IMP results. The calculation indicates that the influence of the threshold voltage instability on the IMP operation can be lessened by selecting the appropriate value of RG in series. To thoroughly solve this problem, the set and reset threshold voltage should be stabilized through the optimization of unipolar switching materials and the design of memristor structures.
3. Study on Au/NiO/STO/Pt memory cells
The interface barrier plays an important role in resistance switching, so p-NiO/n-STO heterojunction prepared by PLD technique. and resistance switching characteristics of the Au/NiO/STO/Pt memory are investigated in detail. The main results are follows:
(1) When a lower CC is set during the electrical test, the memory presents bipolar resistance switching due to the presence of the interface barrier, which can reversiblly convert between clockwise and counter clockwise. The bipolar resistance switching with clockwise (counter clockwise) is due to a change in interface barrier height and/or width by trapping/detrapping effects at NiO/STO (STO/Pt) interface defect states.
(2) When a higher CC (10mA) is set during the electrical test, the memory shows unipolar resistance switching due to the disappearance of the interface barrier. The unipolar switching can be repeatedly switched in the negative bias, while in positive bias the switching disappear after only about4-7cycles. The reason is the different bias polarity driving oxygen vacancies in opposite direction, so the location of switch moves up and down with the bias. Under negative bias, conductive filaments consisted of defects rupture and form in STO films. While under positive bias the rupture position of conductive filaments move to the NiO/STO interface, and the Ni conductive filaments in NiO films is oxidized by O2-, which results in the disappearance of switch.
1. Au/STO/Ti存储器件的制备和电阻开关性能研究
以STO薄膜为阻变材料,选取具有不同功函的金属Au(5.1eV)和Ti(4.3eV)作为上下电极制备了Au/STO/Ti结构的存储器件。电学特性研究表明,STO/Ti之间形成欧姆接触,而Au/STO之间为肖特基接触。在±2.5V的偏压范围内,存储器件表现出逆时针双极电阻开关行为,对I-V和C-V曲线的分析表明阻变源于Au/STO界面肖特基势垒宽度或高度的改变,该界面势垒的改变是由缺陷能级的电荷俘获/释放诱导的；在经历了负极性的电形成电压操作后,器件在同样的±2.5V偏压范围内呈现出顺时针双极电阻开关行为,电学特性分析表明该阻变源于氧空位迁移诱导的氧化还原反应。薄膜内缺陷分布的不同导致了这两种不同特征的双极电阻开关行为。
2. Au/STO/Pt存储器件的电阻开关性能研究及其在实质蕴涵(IMP)逻辑运算中的应用
(1)由于金属/氧化物界面对存储器件的开关特性有重要影响,选择高功函Pt(5.6eV)为下电极制备了Au/STO/Pt结构的存储器。XPS分析说明STO薄膜所含元素价态分别为Sr2+、Ti4+和O2-,并且有氧空位存在。存储器件的初始态表现出整流行为,在经历过负极性的电形成偏压(约-6～-8V)之后,器件表现出单极或双极性电阻开关行为,其开关极性依赖于电形成过程中所设限制电流的大小。当限制电流为1mA,器件表现出双极电阻开关行为；当限制电流为10mA,表现出单极开关行为,并且两种极性之间可以相互转换。该现象表明不同的限制电流,器件内部形成的缺陷不同。对I-V特性的分析表明双极电阻开关是由于Au/STO界面处肖特基势垒的变化引起的；而单极电阻开关是由于缺陷构成的导电丝的形成与破裂致使的。对器件的非易失性研究表明,单极开关的高、低阻态均具有很好的保持能力,两周时间之后电阻值仍无较大的改变,但双极开关的电阻态仅能保持几个小时。
(2)IMP逻辑的研究还处于初始阶段,目前还未见单极忆阻器实现IMP“状态”逻辑的报道。本文选择具有单极开关特性的Au/STO/Pt器件为忆阻器构成了IMP逻辑电路,并通过理论模拟计算,探索IMP逻辑运算中电压、电流等参数设置的特点,以及逻辑运算的稳定性。该单极忆阻器具有较大的开关比值(大于1000),且在低阻态呈现线性Ⅰ-V关系,较小的调制因子(1.2)表明由于串联电阻(RG)的引入导致的开关比值的退偏非常弱,这证明IMP的可靠性被有效增强了。但单极开关阈值电压的离散性会影响IMP运算的重复性,计算表明通过选择合适的串联电阻(RG,500Ω)能减小阈值电压不稳定对IMP运算的影响；但彻底解决该问题,应优化忆阻器结构以使开关电压稳定在较小的范围内。
3. Au/NiO/STO/Pt存储单元的电学性能研究
界面势垒在电阻开关中起着重要作用,在金属/氧化物间插入非常薄的介质层将改变界面性质,进而影响存储器的电阻开关性质,所以本文采用PLD技术沉积了p-NiO/n-STO异质结,并制备了Au/NiO/STO/Pt结构的阻变存储器件。该器件的电学测试结果如下：
(1)在电形成过程中设置较小的限制电流,由于界面势垒的存在,器件表现出双极电阻开关行为,并且他们的回线方向可以在顺时针和逆时针间可逆转换；通过对I-V曲线的拟合发现,高阻态和低阻态分别对应肖特基整流和隧穿机制,进一步分析表明,逆时针(顺时针)双极开关是由于NiO/STO上界面处p-n结势垒(STO/Pt下界面肖特基势垒)的改变引起的,该界面势磊的改变由电荷诱捕效应导致。
(2)在电形成过程中若设置较大的限制电流(10mA),界面势垒消失,器件表现单极电阻开关行为；负偏压下,单极开关能反复切换,但正偏压下,开关仅重复约4-7个周期便消失。其原因是不同极性的偏压驱使氧空位向相反方向移动,使得开关发生的位置随之上下移动。负偏压时,由缺陷组成的导电细丝断开和复合的位置在STO薄膜内；正偏压下,导电细丝的断开位置向NiO/STO上界面移动,同时氧离子将NiO薄膜中的Ni导电丝氧化,致使开关现象消失。
Resistance random access memory (RRAM) is an intriguing approach for next generation non-volatile storage, owing to its attractive combination of density and speed. However, the microscopic physical mechanism of RRAM has been controversial, which became a major obstacle to potential applications. In this dissertation, the RRAM memory cells based on peroskite oxide SrTiO3(STO) are prepared. By means of changing the metal electrode and the introduction of a dielectric layer, the resistance switching characteristics are investigated, and the new principle of logic devices is developed. The main results are as follows:
1. Study on Au/STO/Ti memory cells
The Au/STO/Ti memory cells are prepared. The electrical measurements show that the contact on STO/Ti interface is ohmic, while the contact on the Au/STO interface is Schottky. In the range of±2.5V, the memory showes a bipolar resistance switching with counter clockwise polarity. The analyses on I-V and C-V data show that the resistance change is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states. Netative bias applied to memory can induce a bipolar resistance switching with clockwise polarity which comes from redox reactions induced by the migration of oxygen vacancies. These two bipolar swithing with opposite polarity is due to the different distribution of defect states in STO films.
2. Study on Au/STO/Pt memory cells and its application in new principle devices
(I) The metal/oxide interface has crucial effect on the switching properties of memory cells. Pt as bottom electrodes and the electrical characteristics of Au/STO/Pt are investigated. XPS analysis shows that the valence states of contained elements in STO films are Sr2+, Ti4+, O2-,and there exists a certain amount of oxygen vacancies. The initial state of the Au/STO/Pt cell show rectifying characteristics due to Schottky contact between Au and n-STO. The memory, applied a large reverse bias (about-6～-8V) with1mA compliance current (CC), showes bipolar switching behavior. However, if the CC is set to10mA, the memory will show unipolar switching behavior. Both types of switching with different polarity are interchangeable. The polarity dependence of the CC is due to different current in forming process resulting in the formation of different defect density. Bipolar resistance switching is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states, and unipolar switching is due to the formation and rupture of conductive filament. The non-volatile properties show that the resistance state in unipolar switching has continued for two weeks without significant change, while the resistance state in bipolar switching would be changed after a few hours.
(2) The study on IMP logic is still in an initial stage, and there is no report about IMP logic enabled by unipolar memristors. In this work, the IMP logic circuit is formed by Au/STO/Pt unipolar switch memory. By means of the combination of theoretical simulation and experiment, it is explored that the electric parameters of voltage and current to obtain IMP logic and the stability of the device. This unipolar memristors have a large switching ratio (>1000), linear I-V relationship in low resistance state, and modulation factor of1.2showing that the weak depolarization of switch. These rusults prove that the reliability of IMP is effectively enhanced. However, there is a large variation in set and reset threshold voltage for the Au/STO/Pt unipolar switching device, which could impact the reproducibility of IMP results. The calculation indicates that the influence of the threshold voltage instability on the IMP operation can be lessened by selecting the appropriate value of RG in series. To thoroughly solve this problem, the set and reset threshold voltage should be stabilized through the optimization of unipolar switching materials and the design of memristor structures.
3. Study on Au/NiO/STO/Pt memory cells
The interface barrier plays an important role in resistance switching, so p-NiO/n-STO heterojunction prepared by PLD technique. and resistance switching characteristics of the Au/NiO/STO/Pt memory are investigated in detail. The main results are follows:
(1) When a lower CC is set during the electrical test, the memory presents bipolar resistance switching due to the presence of the interface barrier, which can reversiblly convert between clockwise and counter clockwise. The bipolar resistance switching with clockwise (counter clockwise) is due to a change in interface barrier height and/or width by trapping/detrapping effects at NiO/STO (STO/Pt) interface defect states.
(2) When a higher CC (10mA) is set during the electrical test, the memory shows unipolar resistance switching due to the disappearance of the interface barrier. The unipolar switching can be repeatedly switched in the negative bias, while in positive bias the switching disappear after only about4-7cycles. The reason is the different bias polarity driving oxygen vacancies in opposite direction, so the location of switch moves up and down with the bias. Under negative bias, conductive filaments consisted of defects rupture and form in STO films. While under positive bias the rupture position of conductive filaments move to the NiO/STO interface, and the Ni conductive filaments in NiO films is oxidized by O2-, which results in the disappearance of switch.
引文
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