数字信号处理器中的乘加器设计及其低功耗优化
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摘要
在数字信号处理器(DSP)设计中,乘加操作是DSP的关键部分,乘加器决定时钟周期且占据相当大的芯片面积,单位时间内能够完成乘加操作的数量是衡量DSP芯片性能的一个重要指标。
本文的工作内容是基于数字信号处理器的乘加器的优化设计,首先在分析传统修正Booth编解码实现电路的基础上,提出一种新的低功耗编解码电路实现方案,设计具有较小开销的压缩树形,完成了17位带符号二进制数相乘的压缩过程。对于压缩完成后最终双输入的累加过程,设计采用平方根分组进位结构的混合加法器实现。最后提出一种有效的结构实现通用信号数字处理其所需的分数模式、零检测、饱和溢出控制、舍入操作等异常处理功能,提高判断效率。和传统的Booth编码性能比较,这种有限符号扩展结合乘加操作一步进行与混合加法器的结构在速度方面最快能提高20%,硬件资源最多能减少37%。该乘法器在一个时钟周期内可以完成17位有符号二进制数乘法运算和乘加运算,频率可达90MHz以上。
在乘加器设计完成后使用了W.C.的改进Booth编码电路、动态编码、DOT、SPST、门控信号、NDA等技术优化算法,通过理论分析与综合后仿真实验,改善乘加器的功耗指标。论文完成乘加器的物理设计,并进行后仿真,实验表明低功耗优化具有一定的效果。
DSP multiplier-accumulator is the key unit in digital signal processing. One of the most important standards of DSP performance is the number of MAC operations in unit time.
This paper mainly discusses the multiplier based on the digital signal processor optimized adder design, puts forward a new low-power circuit program, designed with a smaller overhead compression tree, completes 17 bits with a signed binary number multiplied by the compression process. This design uses the square root of the structure of mixed groups carry adder implementation, concludes with an effective structure to achieve universal signal digital processing of their required score model, zero detection, saturation overflow control and rounding operation. Booth encoding and the traditional performance comparison, sign extension with such a limited step of multiply-add operations carried out with the hybrid adder structure can improve the speed of the fastest 20%, hardware resources can reduce up to 37%. The frequency is up to 90MHz or more.
We have been completed five kinds of technical optimization algorithms through theoretical analysis and synthesis of post-simulation experiments. These technologies improve the multiply-adder power consumption. Physical design and post-simulation experiments will show the low-power optimization has some effect.
本文的工作内容是基于数字信号处理器的乘加器的优化设计,首先在分析传统修正Booth编解码实现电路的基础上,提出一种新的低功耗编解码电路实现方案,设计具有较小开销的压缩树形,完成了17位带符号二进制数相乘的压缩过程。对于压缩完成后最终双输入的累加过程,设计采用平方根分组进位结构的混合加法器实现。最后提出一种有效的结构实现通用信号数字处理其所需的分数模式、零检测、饱和溢出控制、舍入操作等异常处理功能,提高判断效率。和传统的Booth编码性能比较,这种有限符号扩展结合乘加操作一步进行与混合加法器的结构在速度方面最快能提高20%,硬件资源最多能减少37%。该乘法器在一个时钟周期内可以完成17位有符号二进制数乘法运算和乘加运算,频率可达90MHz以上。
在乘加器设计完成后使用了W.C.的改进Booth编码电路、动态编码、DOT、SPST、门控信号、NDA等技术优化算法,通过理论分析与综合后仿真实验,改善乘加器的功耗指标。论文完成乘加器的物理设计,并进行后仿真,实验表明低功耗优化具有一定的效果。
DSP multiplier-accumulator is the key unit in digital signal processing. One of the most important standards of DSP performance is the number of MAC operations in unit time.
This paper mainly discusses the multiplier based on the digital signal processor optimized adder design, puts forward a new low-power circuit program, designed with a smaller overhead compression tree, completes 17 bits with a signed binary number multiplied by the compression process. This design uses the square root of the structure of mixed groups carry adder implementation, concludes with an effective structure to achieve universal signal digital processing of their required score model, zero detection, saturation overflow control and rounding operation. Booth encoding and the traditional performance comparison, sign extension with such a limited step of multiply-add operations carried out with the hybrid adder structure can improve the speed of the fastest 20%, hardware resources can reduce up to 37%. The frequency is up to 90MHz or more.
We have been completed five kinds of technical optimization algorithms through theoretical analysis and synthesis of post-simulation experiments. These technologies improve the multiply-adder power consumption. Physical design and post-simulation experiments will show the low-power optimization has some effect.
引文
[1] Texas Instruments Incorporated. TMS320C54x系列DSP的CPU与外设,清华大学出版社,梁晓霞等译, 2006年9月
[2] E. Sternheim, R. Signh and Y. Trivedi,“Digital Design and Synthesis with Verilog HDL”, Automata Publishing Company, CA, 1993
[3] C. S. Wallace,“A Suggestion for a Fast Multiplier”, IEEE Trans.Electronic Computer, Feb. 1964 13: 14-17
[4] G. Economakos, K. Anagnostopoulos,“Bit level architectural exploration technique for the design of low power multipliers,”Proc. IEEE International Symposium on Circuits and Systems 2006, ISCAS2006, Island of Kos, Greece, 2006: 1483-1486
[5] W. C. Yeh, C. W. Jen.“High-Speed Booth Encoded Parallel Multiplier Design,”IEEE Transactions On Computers, July 2000, 49 (7): 692-701
[6]傅志晖,程东方,梅其元等. 32位浮点阵列乘法器的设计及算法比较,微电子学, 2003 3: 190-195
[7] A. D. Booth,“A Signed Binary Multiplication Technique”, Quarterly J. Mechanical and Applied Math, 1951 4: 236-240
[8] L. Dadda,“Some Schemes for Parallel Multiplier”, Alta Frequenza, Mar, 1965 34: 349-356
[9]范靖. DSP处理器数据通路设计,西北工业大学, 2001年硕士论文
[10] R. B. Hussin, A. Y. M. Shakaff et al.“An Efficient Modified Booth Multiplier Architecture,”2008 International Conference on Electronic Design, the Park Royal Hotel, Penang, Malaysia, 2008: 1-4
[11]侯华敏,杨虹,高性能乘加单元的设计,微电子学, 2005, 35 (5): 509-512
[12] P. F. Stelling, P. F. Oklobdzija,“Optimal Designs for Multipliers and Multiply-Accumulators,”Proc. 15th IMACS World Congress Scientific Computation, Modeling, and Applied Math., A. Sydow, ed. Berlin, Germany, Aug 1997: 739-744
[13] E. D. Angel, E. Swartzlander,“Low Power Parallel Multipliers,”Department of Electrical and Computer Engineering University of Texas at Austin, Austin, IEEE, 1996: 199-208
[14]黎宝峰.嵌入式DSP处理器的设计验证,湖南大学2003硕士学位论文
[15]周昔平.高速数字电路的微系统结构研究,西北工业大学2002硕士学位论文
[16]徐锋,邵丙铣. 16*16位高速低功耗并行乘法器的实现,微电子学, 2003, 1 (33)
[17] A. J. AL-Khalili,“32-bit Constant Coefficient Multiplier”, Electrical and Electronic Technology, 2001. TENCON. Proceedings of IEEE Region 10 International Conference on, IEEE, Singapore, 2001 1: 306-308
[18]安印龙,许琪,杨银堂.并行加法器的研究与设计,晋中师范高等专科学校学报, 2003, 4 (20)
[19] O.L. MacSorley,“High Speed Arithmetic in Binary Computers,”Proc. IRE, 1961 49: 67-91
[20] E. D. Angel and E. E. Swartzlander“Low Power Parallel Multipliers”, Jr. Departmentof Electrical and Computer Engineering University of Texas at Austin, VLSI Signal Processing, IX, 1996, San Francisco, CA, USA: 199-208
[21] E. E. Swartzlander, Jr.,“Merged Arithmetic,”IEEE Trans. Computers, 1980 29: 946-950
[22] F. Elguibaly.“A Fast Parallel MAC Using The Modified Booth Algorithm”, IEEE Trans. on Circuits and Systems.II, Sep. 2000, 47 (9): 902 - 908
[23] H. Parandeh-Afshar, M. Ahmadvand“A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor”, Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran, Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on, Nice, 2006: 119-122
[24]王田,陈健,付宇卓.一种32位全定制高速乘法器设计,小型微型计算机系统, 2005, 26 (2)
[25]石碧,程伟综. 16*16带符号/无符号基于RTL级实现的可综合高速乘法器,微电子与基础产品, 2003, 29 (6)
[26]李楠,喻明艳. 16×16快速乘法器的设计与实现,微电子学与计算机, 2008, 25 (4)
[27] A . A. Fayed, F. A. Bayoumi,“A Merged Multiplier-Accumulator for High speed Signal Processing Applications,”The Center for Advanced Computer Studies University of Louisiana at Lafayette, IEEE, 2002: 3212-3215
[28] H. Lee“A Power-Aware Scalable Pipelined Booth Multiplier”, SOC Conference, 2004. Proceedings. IEEE International, 12-15 Sept. 2004: 123-126
[29] V.A. Bartlett and E. Grass“A low-power concurrent multiplier-accumulator using conditionalevaluation”IEEE Electronics, Circuits and Systems, Proceedings of ICECS 99. The 6th IEEE International Conference on, Pafos, Cyprus, 1999 2: 629-633
[30] K-Y. Khoo, Z. Yu and A. N. Willson,“Improved-Booth encoding for low-power multipliers”Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on, Orlando, FL, USA, 1999 1: 62-65
[31] K-H. Chen, Y-M. Chen, and Y-S. Chu,“A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique”Department of Electrical Engineering National Chung Cheng UniversityChiayi 621, Taiwan,2006 IEEE, Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, Hangzhou : 111-114
[32] T-C. Oscal , S. Wang, and Y. W. Wu,“Minimization of switching activities of partial products for designing low-power multipliers,”IEEE Trans. VLSI, June, 2003 11: 418-433
[33] M. Fujino and V. G. Moshnyaga“Dynamic operand transformation for low-power multiplier-accumulator design”Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on 2003 5: 345-348
[34] K-H. Chen and Y-S. Chu“A Low-Power Multiplier With the Spurious Power Suppression Technique”,IEEE Transactions on Very Large Scale Intergation(VLSI) Systems, July 2007 15: 7-8
[35] H. T. Ngo and V. K. Asari ,“Design of a Radix-4 Booth Multiplier with Neighborhood Dependent Approach for Video Processing Applications”, IEEE,Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, Montreal, Que. 2007: 53-56
[36] H. P. Afshar, M. Ahmadvand,“A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor”,IEEE, 2006: 119-122
[37]郭炜,郭筝. SoC设计方法与实现,电子工业出版社, 2007 6: 21-35
[38] A. R. Masoleh, M. A. Hasan,“Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m), computers,”IEEE Trans. Comput. Aug. 2004, 53, (8): 945-959
[39] Synopsys, Inc, NanoSim?-VCS? User Guide, Version Z-2007.03, March 2007: 62-66
[40]孙世磊,薛金涛,王高峰.精确寄生参数提取软件设计和实现.计算机工程与应用. 2008, 44 (21): 49-51
[2] E. Sternheim, R. Signh and Y. Trivedi,“Digital Design and Synthesis with Verilog HDL”, Automata Publishing Company, CA, 1993
[3] C. S. Wallace,“A Suggestion for a Fast Multiplier”, IEEE Trans.Electronic Computer, Feb. 1964 13: 14-17
[4] G. Economakos, K. Anagnostopoulos,“Bit level architectural exploration technique for the design of low power multipliers,”Proc. IEEE International Symposium on Circuits and Systems 2006, ISCAS2006, Island of Kos, Greece, 2006: 1483-1486
[5] W. C. Yeh, C. W. Jen.“High-Speed Booth Encoded Parallel Multiplier Design,”IEEE Transactions On Computers, July 2000, 49 (7): 692-701
[6]傅志晖,程东方,梅其元等. 32位浮点阵列乘法器的设计及算法比较,微电子学, 2003 3: 190-195
[7] A. D. Booth,“A Signed Binary Multiplication Technique”, Quarterly J. Mechanical and Applied Math, 1951 4: 236-240
[8] L. Dadda,“Some Schemes for Parallel Multiplier”, Alta Frequenza, Mar, 1965 34: 349-356
[9]范靖. DSP处理器数据通路设计,西北工业大学, 2001年硕士论文
[10] R. B. Hussin, A. Y. M. Shakaff et al.“An Efficient Modified Booth Multiplier Architecture,”2008 International Conference on Electronic Design, the Park Royal Hotel, Penang, Malaysia, 2008: 1-4
[11]侯华敏,杨虹,高性能乘加单元的设计,微电子学, 2005, 35 (5): 509-512
[12] P. F. Stelling, P. F. Oklobdzija,“Optimal Designs for Multipliers and Multiply-Accumulators,”Proc. 15th IMACS World Congress Scientific Computation, Modeling, and Applied Math., A. Sydow, ed. Berlin, Germany, Aug 1997: 739-744
[13] E. D. Angel, E. Swartzlander,“Low Power Parallel Multipliers,”Department of Electrical and Computer Engineering University of Texas at Austin, Austin, IEEE, 1996: 199-208
[14]黎宝峰.嵌入式DSP处理器的设计验证,湖南大学2003硕士学位论文
[15]周昔平.高速数字电路的微系统结构研究,西北工业大学2002硕士学位论文
[16]徐锋,邵丙铣. 16*16位高速低功耗并行乘法器的实现,微电子学, 2003, 1 (33)
[17] A. J. AL-Khalili,“32-bit Constant Coefficient Multiplier”, Electrical and Electronic Technology, 2001. TENCON. Proceedings of IEEE Region 10 International Conference on, IEEE, Singapore, 2001 1: 306-308
[18]安印龙,许琪,杨银堂.并行加法器的研究与设计,晋中师范高等专科学校学报, 2003, 4 (20)
[19] O.L. MacSorley,“High Speed Arithmetic in Binary Computers,”Proc. IRE, 1961 49: 67-91
[20] E. D. Angel and E. E. Swartzlander“Low Power Parallel Multipliers”, Jr. Departmentof Electrical and Computer Engineering University of Texas at Austin, VLSI Signal Processing, IX, 1996, San Francisco, CA, USA: 199-208
[21] E. E. Swartzlander, Jr.,“Merged Arithmetic,”IEEE Trans. Computers, 1980 29: 946-950
[22] F. Elguibaly.“A Fast Parallel MAC Using The Modified Booth Algorithm”, IEEE Trans. on Circuits and Systems.II, Sep. 2000, 47 (9): 902 - 908
[23] H. Parandeh-Afshar, M. Ahmadvand“A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor”, Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran, Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on, Nice, 2006: 119-122
[24]王田,陈健,付宇卓.一种32位全定制高速乘法器设计,小型微型计算机系统, 2005, 26 (2)
[25]石碧,程伟综. 16*16带符号/无符号基于RTL级实现的可综合高速乘法器,微电子与基础产品, 2003, 29 (6)
[26]李楠,喻明艳. 16×16快速乘法器的设计与实现,微电子学与计算机, 2008, 25 (4)
[27] A . A. Fayed, F. A. Bayoumi,“A Merged Multiplier-Accumulator for High speed Signal Processing Applications,”The Center for Advanced Computer Studies University of Louisiana at Lafayette, IEEE, 2002: 3212-3215
[28] H. Lee“A Power-Aware Scalable Pipelined Booth Multiplier”, SOC Conference, 2004. Proceedings. IEEE International, 12-15 Sept. 2004: 123-126
[29] V.A. Bartlett and E. Grass“A low-power concurrent multiplier-accumulator using conditionalevaluation”IEEE Electronics, Circuits and Systems, Proceedings of ICECS 99. The 6th IEEE International Conference on, Pafos, Cyprus, 1999 2: 629-633
[30] K-Y. Khoo, Z. Yu and A. N. Willson,“Improved-Booth encoding for low-power multipliers”Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on, Orlando, FL, USA, 1999 1: 62-65
[31] K-H. Chen, Y-M. Chen, and Y-S. Chu,“A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique”Department of Electrical Engineering National Chung Cheng UniversityChiayi 621, Taiwan,2006 IEEE, Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, Hangzhou : 111-114
[32] T-C. Oscal , S. Wang, and Y. W. Wu,“Minimization of switching activities of partial products for designing low-power multipliers,”IEEE Trans. VLSI, June, 2003 11: 418-433
[33] M. Fujino and V. G. Moshnyaga“Dynamic operand transformation for low-power multiplier-accumulator design”Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on 2003 5: 345-348
[34] K-H. Chen and Y-S. Chu“A Low-Power Multiplier With the Spurious Power Suppression Technique”,IEEE Transactions on Very Large Scale Intergation(VLSI) Systems, July 2007 15: 7-8
[35] H. T. Ngo and V. K. Asari ,“Design of a Radix-4 Booth Multiplier with Neighborhood Dependent Approach for Video Processing Applications”, IEEE,Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, Montreal, Que. 2007: 53-56
[36] H. P. Afshar, M. Ahmadvand,“A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor”,IEEE, 2006: 119-122
[37]郭炜,郭筝. SoC设计方法与实现,电子工业出版社, 2007 6: 21-35
[38] A. R. Masoleh, M. A. Hasan,“Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m), computers,”IEEE Trans. Comput. Aug. 2004, 53, (8): 945-959
[39] Synopsys, Inc, NanoSim?-VCS? User Guide, Version Z-2007.03, March 2007: 62-66
[40]孙世磊,薛金涛,王高峰.精确寄生参数提取软件设计和实现.计算机工程与应用. 2008, 44 (21): 49-51