“银河飞腾-DSP”Viterbi译码协处理器（VCP）的设计与实现
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摘要
“银河飞腾-EX”(YHFT-EX)是国防科大计算机学院正在研制的一款高性能DSP芯片,它针对3G标准作了一系列优化。3G对语音和数据通信的速率和误码率的提出了更高要求,这就使得通常用软件实现的纠错码需要占用更多的处理资源。YHFT-EX中针对纠错码的问题设置了两个协处理器(Viterbi译码协处理器和Turbo码协处理器)。这一新的设计方法极大地加快了纠错码的译码速率,同时释放了更多的DSP资源。
3G标准中一般采用卷积码或Trubo码来实现信道纠错,本文深入研究了卷积码的Viterbi译码算法,并根据3G要求,同时适应DSP本身的结构特点,设计实现了一款高性能Viterbi译码协处理器(VCP)。
ACS单元是Viterbi译码器的一个主要部件,它的性能好坏对整个译码器性能起着至关重要的作用。传统的级连结构在约束度大时延迟单元数多、可配置性差。本设计把传统级连结构的级连长度根据约束度分相实现,很好的解决了上述问题,同时有结构简单的优点。
VCP在译码输出部分采用了“部分寄存器交换-整体回溯”法,它同时具有寄存器交换法速度快和回溯法功耗小的优点,又与ACS单元的分相结构相对应,有效解决了译码输出部分速度和功耗之间的矛盾。
论文中详细阐述了各个模块的设计实现过程,分析了级连ACS结构中不同约束度的数据读写冲突问题、不同相时刻状态度量存储器地址调度问题以及不同回溯模式产生的问题等。最后,VCP通过了功能验证和FPGA仿真验证,并进行了误码率和速率的性能分析,它完全可以满足3G标准中对于语音编码的要求。
YHFT-EX is a high perfomance DSP which is designed by the YHFT-DSP Design Group of Computer School of National University of Defense Technology, and it is optimized based on the 3G(Third-Generation) standard. 3G demands for higher voice-quality and lower bit-error-rate (BER). It's become a problem for the traditional implement of forward error correction (FEC) which handing all FEC in software which in general eats up a great deal of DSP capacity. YHFT-EX has integrated Viterbi and Turbo hardware accelerators, and the two coprocessors handle the majority of the FEC decoding computations. This method greatly improved the speed of decoding while freeing more DSP capacity for other functions.
In general, the implement of FEC using Convolutional codes or Turbo codes in 3G. This article studied the algorithm of Viterbi, and developed the high performance VCP coprocessor based on the demand of 3G and the architecture of DSP.
ACS is one of the main part of Viterbi decoder, which affects the performance of the decoder. Traditional Cascase ACS architecture has more delay units and poorer configurable. Our design separated the original cascade architecture to two phases based on the constraint. This new cascade ACS architecture sovled the above problems and has the merit of easy to implement.
The method of decoding output is "partly register-exchange, wholly traceback ", which has the merits of register exchange which run faster and the merits of traceback which wasted lower power. Also, the structure corresponds to the new cascade ACS structure which has two phases and offsets the speed and power.
The article explained the design and implemention of each module, analyzed the read-write conflict caused by the differential of constraints in cascade ACS structure, the address attemperation of state metric memory in each symbol period, and the problem caused by the differential of traceback modes and so on. In the end, VCP has been passed the functional verification and FPGA emulation. The BER performance and code rates is perfect satisfied the Voice-Coding demand in 3G standard.
3G标准中一般采用卷积码或Trubo码来实现信道纠错,本文深入研究了卷积码的Viterbi译码算法,并根据3G要求,同时适应DSP本身的结构特点,设计实现了一款高性能Viterbi译码协处理器(VCP)。
ACS单元是Viterbi译码器的一个主要部件,它的性能好坏对整个译码器性能起着至关重要的作用。传统的级连结构在约束度大时延迟单元数多、可配置性差。本设计把传统级连结构的级连长度根据约束度分相实现,很好的解决了上述问题,同时有结构简单的优点。
VCP在译码输出部分采用了“部分寄存器交换-整体回溯”法,它同时具有寄存器交换法速度快和回溯法功耗小的优点,又与ACS单元的分相结构相对应,有效解决了译码输出部分速度和功耗之间的矛盾。
论文中详细阐述了各个模块的设计实现过程,分析了级连ACS结构中不同约束度的数据读写冲突问题、不同相时刻状态度量存储器地址调度问题以及不同回溯模式产生的问题等。最后,VCP通过了功能验证和FPGA仿真验证,并进行了误码率和速率的性能分析,它完全可以满足3G标准中对于语音编码的要求。
YHFT-EX is a high perfomance DSP which is designed by the YHFT-DSP Design Group of Computer School of National University of Defense Technology, and it is optimized based on the 3G(Third-Generation) standard. 3G demands for higher voice-quality and lower bit-error-rate (BER). It's become a problem for the traditional implement of forward error correction (FEC) which handing all FEC in software which in general eats up a great deal of DSP capacity. YHFT-EX has integrated Viterbi and Turbo hardware accelerators, and the two coprocessors handle the majority of the FEC decoding computations. This method greatly improved the speed of decoding while freeing more DSP capacity for other functions.
In general, the implement of FEC using Convolutional codes or Turbo codes in 3G. This article studied the algorithm of Viterbi, and developed the high performance VCP coprocessor based on the demand of 3G and the architecture of DSP.
ACS is one of the main part of Viterbi decoder, which affects the performance of the decoder. Traditional Cascase ACS architecture has more delay units and poorer configurable. Our design separated the original cascade architecture to two phases based on the constraint. This new cascade ACS architecture sovled the above problems and has the merit of easy to implement.
The method of decoding output is "partly register-exchange, wholly traceback ", which has the merits of register exchange which run faster and the merits of traceback which wasted lower power. Also, the structure corresponds to the new cascade ACS structure which has two phases and offsets the speed and power.
The article explained the design and implemention of each module, analyzed the read-write conflict caused by the differential of constraints in cascade ACS structure, the address attemperation of state metric memory in each symbol period, and the problem caused by the differential of traceback modes and so on. In the end, VCP has been passed the functional verification and FPGA emulation. The BER performance and code rates is perfect satisfied the Voice-Coding demand in 3G standard.
引文
[1]王新梅,肖国镇.纠错码-原理与方法.西安电子科技大学出版社(修订版),2001
[2]李方慧,王飞,何培琨.TMS320C6000系列DSPs原理与应用(第2版).电子工业出版社,2003
[3]Michael John Sebastian Smith.Application-Specific Integrated Circuits(专用集成电路).电子工业出版社,2004
[4]G D Forney Jr.The Viterbi Algorithm.Proc.IEEE,61:268-278,March 1973
[5]A J Viterbi.Error bounds for convolutional codes and an asymptotically optimum decoding algorithm.IEEE Transactions on Information Theory,vol.IT-13,260-269,April 1967
[6]G.Gulak and T.Kailath.Locally Connected VLSI Architectures for the Viterbi Algorithm.IEEE Journal on Selected Areas in Communications,6:527-538,April 1988
[7]Gennady Feygin,Paul Chow,P Glenn Gulak,John Chappel and Grant Goodes.A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.IEEE International Symposium on Circuits and Systems,pp.1945-1948,May 1993
[8]Gennady Feygin,Patrick G Gulak,and Paul Chow.A Multiprocessor Architecture for Viterbi Decoders with Linear Speedup.IEEE Transactions on signal processing,vol.41,NO.9,September 1993
[9]Dale E.Hocevar,Alan Gatherer.Achieving Flexibility in a Viterbi Decoder DSP Coprocessor.IEEE,VTCFaI1,pp.2257-2264,2000
[10]TI.TMS320C64x DSP Viterbi-Decoder Coprocessor(VCP)Reference Guide.Texas Instruments,2004
[11]TI.Using TMS320C6416 Coprocessors:Viterbi Coprocessor(VCP).Texas Instruments,2003
[12]Patrick H.Kelly,Dr.Paul M.Chau.A Flexible constraint length,foldable Viterbi decoder.Proc,IEEE global Telecommunication Conference.vol 1,pp 631-635
[13]A.P.Hekstra.An alternative to Metric Rescaling in Viterbi Decoders.IEEE Transactions on Communications,vol 37,NO.11,November 1989,pp.1220-1222
[14] P.J.Black, T.H.Meng. A 140-Mb/s, 32-state, radix-4 Viterbi decoder. IEEE Journal of Solid State Circuit, vol.27, no.12, pp.1877—1885, December 1992
[15] C. M. Rader. Memory management in a Viterbi decoder. IEEE Trans Commun., vol. COM-29, pp 1399-1401, Sept 1981
[16] G.Fettweiss, H. Meyer. High Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture. IEEE Comm. Magazine, May 1991.
[17] C.Bernard Shung, Paul H.Siegel, Gottfried Ungerboeck, Hemant K Thapar. VLSI Architectures for Metric Normalization in the Viterbi Algorithm. Proc IEEE International Conference Communications (ICC'90), vol.4, Atlanta, Ga, Apr. 16-19, 1990, pp 1723-1728
[18] Hirosuke Yamamoto, Kohji Itoh. Viterbi Decoding Algorithm for Convolutional Codes with Repeat Request. IEEE Transaction on Information Theory, Vol. IT-26, No.5, September 1980
[19] G.Fettweis, H.Meyr. Parallel Viterbi Algorithm Implementation: Breaking the ACS-Bottleneck. IEEE Transaction on Communications 37(8): 285-90, Aug, 1989
[20] Boo, M., Arguello, F., Bruguera, J.D., Doallo, R., Zapatta, E.L. High performance VLSI Architecture for the Viterbi Algorithm . IEEE Transactions on Communications, Vol.45, No.2, Feb, 1997
[21] Jelena Nikolic-Popovic, Nat Sesha. DSP/Coprocessor Combos Streamline 3G Basestations. CommsDesign, Vol.8, Mar 01 2002
[22] C.Y.Chang, K. Yao. Viterbi decoding by systolic array. Proc Twenty-Third Annu. Allerton Conf Commun., Cont. Comput, Allerton House, Monticello, IL, Oct. 2-4, 1985, pp. 430-439.
[23] Gennady Feygin, Paul Chow, P Glenn Gulak, John Chappel, Grant Goodes. A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. IEEE International Symposium on Circuits and Systems, pp 1945-1948. May 1993
[2]李方慧,王飞,何培琨.TMS320C6000系列DSPs原理与应用(第2版).电子工业出版社,2003
[3]Michael John Sebastian Smith.Application-Specific Integrated Circuits(专用集成电路).电子工业出版社,2004
[4]G D Forney Jr.The Viterbi Algorithm.Proc.IEEE,61:268-278,March 1973
[5]A J Viterbi.Error bounds for convolutional codes and an asymptotically optimum decoding algorithm.IEEE Transactions on Information Theory,vol.IT-13,260-269,April 1967
[6]G.Gulak and T.Kailath.Locally Connected VLSI Architectures for the Viterbi Algorithm.IEEE Journal on Selected Areas in Communications,6:527-538,April 1988
[7]Gennady Feygin,Paul Chow,P Glenn Gulak,John Chappel and Grant Goodes.A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.IEEE International Symposium on Circuits and Systems,pp.1945-1948,May 1993
[8]Gennady Feygin,Patrick G Gulak,and Paul Chow.A Multiprocessor Architecture for Viterbi Decoders with Linear Speedup.IEEE Transactions on signal processing,vol.41,NO.9,September 1993
[9]Dale E.Hocevar,Alan Gatherer.Achieving Flexibility in a Viterbi Decoder DSP Coprocessor.IEEE,VTCFaI1,pp.2257-2264,2000
[10]TI.TMS320C64x DSP Viterbi-Decoder Coprocessor(VCP)Reference Guide.Texas Instruments,2004
[11]TI.Using TMS320C6416 Coprocessors:Viterbi Coprocessor(VCP).Texas Instruments,2003
[12]Patrick H.Kelly,Dr.Paul M.Chau.A Flexible constraint length,foldable Viterbi decoder.Proc,IEEE global Telecommunication Conference.vol 1,pp 631-635
[13]A.P.Hekstra.An alternative to Metric Rescaling in Viterbi Decoders.IEEE Transactions on Communications,vol 37,NO.11,November 1989,pp.1220-1222
[14] P.J.Black, T.H.Meng. A 140-Mb/s, 32-state, radix-4 Viterbi decoder. IEEE Journal of Solid State Circuit, vol.27, no.12, pp.1877—1885, December 1992
[15] C. M. Rader. Memory management in a Viterbi decoder. IEEE Trans Commun., vol. COM-29, pp 1399-1401, Sept 1981
[16] G.Fettweiss, H. Meyer. High Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture. IEEE Comm. Magazine, May 1991.
[17] C.Bernard Shung, Paul H.Siegel, Gottfried Ungerboeck, Hemant K Thapar. VLSI Architectures for Metric Normalization in the Viterbi Algorithm. Proc IEEE International Conference Communications (ICC'90), vol.4, Atlanta, Ga, Apr. 16-19, 1990, pp 1723-1728
[18] Hirosuke Yamamoto, Kohji Itoh. Viterbi Decoding Algorithm for Convolutional Codes with Repeat Request. IEEE Transaction on Information Theory, Vol. IT-26, No.5, September 1980
[19] G.Fettweis, H.Meyr. Parallel Viterbi Algorithm Implementation: Breaking the ACS-Bottleneck. IEEE Transaction on Communications 37(8): 285-90, Aug, 1989
[20] Boo, M., Arguello, F., Bruguera, J.D., Doallo, R., Zapatta, E.L. High performance VLSI Architecture for the Viterbi Algorithm . IEEE Transactions on Communications, Vol.45, No.2, Feb, 1997
[21] Jelena Nikolic-Popovic, Nat Sesha. DSP/Coprocessor Combos Streamline 3G Basestations. CommsDesign, Vol.8, Mar 01 2002
[22] C.Y.Chang, K. Yao. Viterbi decoding by systolic array. Proc Twenty-Third Annu. Allerton Conf Commun., Cont. Comput, Allerton House, Monticello, IL, Oct. 2-4, 1985, pp. 430-439.
[23] Gennady Feygin, Paul Chow, P Glenn Gulak, John Chappel, Grant Goodes. A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. IEEE International Symposium on Circuits and Systems, pp 1945-1948. May 1993