时分交换的新型FPGA互连结构研究
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摘要
现场可编程门阵歹(?)(FPGA)以其独特的可编程特性、低掩膜成本、快速产品开发、方便产品升级等优势成为过去二十年中迅速发展的数字系统核心。FPGA的结构决定其独特的可编程性能,而在大规模FPGA芯片中,可编程互连资源占据整个芯片70%的面积和60%的延时,因此互连资源的结构很大程度上决定了FPGA芯片的性能,是FPGA设计的重中之重。
本文总结了国内外FPGA互连资源的研究现状,指出传统互连结构的特点是通过空间上的大量冗余以满足实现各种电路连接的灵活性,造成大量互连资源的浪费。随着FPGA的规模越来越大,传统互连结构成为提升速度和密度的瓶颈。本文在时分复用、源同步传输、串行流水线技术的基础上,结合通信系统中的时隙交换原理,提出一种新型时分交换FPGA(时分交换即基于时分复用的时隙交换,简称TDE-FPGA)(?)的互连结构。这种新型互连结构可以减少互连资源占用芯片的面积、降低设计复杂性、提高可靠性,为开发新型的高逻辑密度、高性能FPGA产品打下基础。若该研究能在国产FPGA芯片中推广应用,将为FPGA器件的国产化带来巨大的社会效益和经济效益。
首先提出TDE-FPGA的整体硬件架构：在传统FPGA的互连资源中添加时隙交换单元、时分复用单元、串化器、解串器等关键电路,以支持本文提出的时分交换思想。并采用TSMC65nm工艺库对关键电路进行仿真,仿真结果证实了TDE-FPGA互连结构的设计思想。
然后将TDE-FPGA中的时分交换互连结构转换为等价的空间交换互连结构,建立等价参数化空间交换模型,在CAD工具VPR的基础上改进算法和程序,建立新型TDE-FPGA的软件模型TDE-VPR。
最后在软件模型TDE-VPR的基础上,对TDE-FPGA结构进行评估。将20个MCNC标准测试电路集在TDE-VPR中进行布局布线,比较TDE-FPGA与传统FPGA结构布局布线成功所需的最小通道宽度数量Wmin,结果显示TDE-FPGA可以减少Wmin数量,减少互连资源,提高布通率,而且复用度越高,时分交换的效果越好。并在本文提出的面积评估模型上比较TDE-FPGA和传统FPGA结构在而积上的差异,结果显示,新型TDE-FPGA相较于传统FPGA结构,复用度为8时,最多可节省29.6%的而积,平均最多节省15.2%的互连资源而积。证实使用时分交换的新型TDE-FPGA结构可有效减少互连资源占用芯片的而积。
FPGA has become one of the key digital system over the last two decades because of its unique programmable technology, low mask cost, shorten time-to-market and easy to upgrade. The programmable feature of FPGA is decided by its unique architecture. Among the research and development of FPGA architecture, the design of programmable interconnection is the most important, because it costs approximately70%of the chip area and60%of the signal delay.
This thesis summarize the research about interconnection in FPGA, point out that the traditional fabric gain the flexibility by large redundance in space. As the scale of the chip increase, the traditional fabric soon became the bottle net of speed and density of the chip. This thesis proposed a new architecture of FPGA(Time Division Exchange-FPGA which shorten by TDE-FPGA) interconnect based on time-division multiplex, source-synchronous, pipelining, and the theory of time slot exchange. The new architecture can reduce the area of interconnection resources, play down the design complexity, improve the reliability, lay the foundation for developing high density and low power FPGA chip. It will bring enormous social and economic benefits if the research can be applied in homemade FPGA chips.
Firstly, proposes the whole hardware framework of TDE-FPGA, adds time slot exchange, time division multiplex, serializer and deserializer to the traditional FPGA, and then emulated the added circuits using TSMC65nm technology library, the results show that the design of TDE-FPGA are thoroughly correct.
Secondly, establish the software model of TDE-FPGA through transport the time division exchange fabric into the space interconnection fabric, based on the CAD tool VPR and modify its arithmetic and procedure, which named TDE-VPR.
Finally, assess the new TDE-FPGA architecture based on TDE-VPR, place and route on TDE-VPR for20MCNC standard test circuits, compared the minimal channel width Wmin between the TDE-FPGA and the traditional FPGA. The results show that the TDE-FPGA can reduce the amount of Wmin, enhance the routability compared with the traditional FPGA, and with larger M, a better result can be obtained. And then compared the area difference based on the area model, the results show that when M=8, we can save the area of29.6%at most,15.2%in average. It proves that the new TDE-FPGA architecture can reduce the area of interconnection resources.
本文总结了国内外FPGA互连资源的研究现状,指出传统互连结构的特点是通过空间上的大量冗余以满足实现各种电路连接的灵活性,造成大量互连资源的浪费。随着FPGA的规模越来越大,传统互连结构成为提升速度和密度的瓶颈。本文在时分复用、源同步传输、串行流水线技术的基础上,结合通信系统中的时隙交换原理,提出一种新型时分交换FPGA(时分交换即基于时分复用的时隙交换,简称TDE-FPGA)(?)的互连结构。这种新型互连结构可以减少互连资源占用芯片的面积、降低设计复杂性、提高可靠性,为开发新型的高逻辑密度、高性能FPGA产品打下基础。若该研究能在国产FPGA芯片中推广应用,将为FPGA器件的国产化带来巨大的社会效益和经济效益。
首先提出TDE-FPGA的整体硬件架构：在传统FPGA的互连资源中添加时隙交换单元、时分复用单元、串化器、解串器等关键电路,以支持本文提出的时分交换思想。并采用TSMC65nm工艺库对关键电路进行仿真,仿真结果证实了TDE-FPGA互连结构的设计思想。
然后将TDE-FPGA中的时分交换互连结构转换为等价的空间交换互连结构,建立等价参数化空间交换模型,在CAD工具VPR的基础上改进算法和程序,建立新型TDE-FPGA的软件模型TDE-VPR。
最后在软件模型TDE-VPR的基础上,对TDE-FPGA结构进行评估。将20个MCNC标准测试电路集在TDE-VPR中进行布局布线,比较TDE-FPGA与传统FPGA结构布局布线成功所需的最小通道宽度数量Wmin,结果显示TDE-FPGA可以减少Wmin数量,减少互连资源,提高布通率,而且复用度越高,时分交换的效果越好。并在本文提出的面积评估模型上比较TDE-FPGA和传统FPGA结构在而积上的差异,结果显示,新型TDE-FPGA相较于传统FPGA结构,复用度为8时,最多可节省29.6%的而积,平均最多节省15.2%的互连资源而积。证实使用时分交换的新型TDE-FPGA结构可有效减少互连资源占用芯片的而积。
FPGA has become one of the key digital system over the last two decades because of its unique programmable technology, low mask cost, shorten time-to-market and easy to upgrade. The programmable feature of FPGA is decided by its unique architecture. Among the research and development of FPGA architecture, the design of programmable interconnection is the most important, because it costs approximately70%of the chip area and60%of the signal delay.
This thesis summarize the research about interconnection in FPGA, point out that the traditional fabric gain the flexibility by large redundance in space. As the scale of the chip increase, the traditional fabric soon became the bottle net of speed and density of the chip. This thesis proposed a new architecture of FPGA(Time Division Exchange-FPGA which shorten by TDE-FPGA) interconnect based on time-division multiplex, source-synchronous, pipelining, and the theory of time slot exchange. The new architecture can reduce the area of interconnection resources, play down the design complexity, improve the reliability, lay the foundation for developing high density and low power FPGA chip. It will bring enormous social and economic benefits if the research can be applied in homemade FPGA chips.
Firstly, proposes the whole hardware framework of TDE-FPGA, adds time slot exchange, time division multiplex, serializer and deserializer to the traditional FPGA, and then emulated the added circuits using TSMC65nm technology library, the results show that the design of TDE-FPGA are thoroughly correct.
Secondly, establish the software model of TDE-FPGA through transport the time division exchange fabric into the space interconnection fabric, based on the CAD tool VPR and modify its arithmetic and procedure, which named TDE-VPR.
Finally, assess the new TDE-FPGA architecture based on TDE-VPR, place and route on TDE-VPR for20MCNC standard test circuits, compared the minimal channel width Wmin between the TDE-FPGA and the traditional FPGA. The results show that the TDE-FPGA can reduce the amount of Wmin, enhance the routability compared with the traditional FPGA, and with larger M, a better result can be obtained. And then compared the area difference based on the area model, the results show that when M=8, we can save the area of29.6%at most,15.2%in average. It proves that the new TDE-FPGA architecture can reduce the area of interconnection resources.
引文
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