超结器件的模型研究及优化设计
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摘要
功率MOSFET应用领域广阔,是中小功率领域内主流的功率半导体开关器件,也是DC-DC转换的核心电子器件,它占据着分立功率半导体器件市场的最大份额。基于电荷补偿原理的超结功率MOSFET,比传统的MOSFET具有更低的比导通电阻。尽管超结MOSFET本身存在着工艺难度大、体二极管反向恢复能力差等主要缺点,但新结构新思想的引入在一定程度上缓和了这些问题。超结MOSFET及其理论的深入研究与完善对功率半导体器件的发展至关重要。
     本文通过建立超结MOSFET及半超结MOSFET的二维解析模型,研究了它们的比导通电阻与击穿电压的关系,解释了器件的击穿机理,分析了超结柱的电荷非平衡对击穿电压的影响等问题。作为比较,本文还研究了传统VDMOSFET耐压层中常采用的非穿通型与穿通型的平行平面结的更准确的设计表达式。本文的主要创新工作为:
     1.考虑更准确的碰撞电离率的模型,基于数值计算的方法,提出了非穿通型与穿通型平行平面结基于Chynoweth方法的新的设计表达式。由于在考虑碰撞电离率与电场的关系时使用了更准确的Chynoweth模型,该设计表达式比传统方法利用Fulop模型得到的设计表达式更接近MEDICI器件仿真结果。作为功率器件设计的基础,本文得到的关于非穿通型与穿通型的平行平面结的表达式为器件设计人员对器件的耐压以及终端设计的参数提供了更准确的初步估算。
     2.提出了对称平衡的超结MOSFET的二维电场分布,解释了超结的柱掺杂浓度与柱深度对耐压机制的影响。研究发现,当耐压区不完全耗尽时,沿着几条特殊的电场线的电离率积分同时达到1是对称平衡的超结器件取得最小比导通电阻的条件,即比导通电阻的最优化设计。对于击穿电压大于600V的设计,与过去文献中准优化设计的结果相比,其最小比导通电阻可降低超过13%。该工作引入Catalan常数,给出纵向电场分布及过P柱与N柱交界面中心点的电场分布的近似指数分布,并从理论上验证了过去文献中仅用仿真结果发现的结论。(该工作发表于IEEE T-ED第59卷第10期。)
     3.基于电荷叠加方法和格林函数方法,提出了半超结器件的精确的二维解析模型,并给出半超结器件的比导通电阻的设计步骤。为与半超结器件的比导通电阻进行比较,对超结的柱的深宽比和击穿电压固定的超结器件的比导通电阻进行优化,从理论上验证了过去文献提出的比导通电阻与击穿电压的2.5次方的正比关系;对半超结器件的击穿电压受超结层的柱的电荷非平衡的影响的理论分析表明,最高的击穿电压发生在正的电荷非平衡条件下。(该工作发表于IEEE T-ED第60卷第3期。)
The power MOSFETs are widely employed as the main power semiconductor switching devices in low and medium power applications, which are also the main electron devices in the DC/DC converters and occupy the largest share of the power semiconductor market products. Based on the principle of charge compensation, the superjunction MOSFETs have much lower specific on-resistance than the conventional MOSFETs. Although the main drawbacks of fabrication difficulty and hard reverse-recovery of the body diode are existed in the S J MOSFETs, the introduction of some new structures, to some degree, alleviates these problems, and accordingly, a deep inside into the SJ MOSFETs is still important.
     In this thesis, the two-dimensional analytical models of the electric fields for the superjunction(SJ) and semisuperjunction (SemiSJ) MOSFETs are established. The relations of the specific on-resistance and the breakdown voltage of these two devices are also studied. The mechanisms of the avalanche breakdown are explained, and the impact on the breakdown voltages by the charge imbalance in the SJ layers is analyzed. Moreover, as a comparison, new design expressions for the abrupt parallel plain nonpunchthrough and punchthrough junctions, which are used as the sustaining layers of the VDMOSFETs, are proposed. The main innovations of this thesis are included as follows:
     1. Based on the Chynoweth law of the ionization rate, new design expressions for the NPT and PT junctions are proposed by using the numerical calculation method. The expressions are more accurate in terms of the MEDICI device simulations as compared with the results by using Fulop model. The new expressions allow more accurate evaluation in the design of the breakdown voltages and the parameters choices for the device designers.
     2. A useful approximation on the2-D electric field for the interdigitated balanced symmetric SJ devices is proposed, and the breakdown voltage mechanisms are explained by the doping concentration and depth in the SJ columns. It is found that the condition to obtain the minimum specific on-resistance for the SJ structure is that, when the voltage-sustaining layer is not fully depleted, the ionization integrals along different field lines approach one simultaneously. For the design of BV larger than600V, the optimized specific on-resistance can be lower down by larger than13%, compared with the conventional suboptimal design. By using the Catalan constant, G, the electric fields along the vertical direction and along the field line across the middle point in the boundary of P and N columns are approximated as the exponential function, and the previous conclusion that obtained by simulations is theoretically verified.
     3. Analytical models of the2-D electric field distributions of the interdigitated balanced symmetric SemiSJ structure, based on the charge superposition method, are derived. An accurate approximation of the exact analytical solution of the vertical electric field is also proposed and demonstrated by device simulation. The optimization method and its numerical calculation results of the specific on-resistance of the SemiSJ trench MOSFETs with constant aspect ratio are presented and verified by simulations. The calculation results show that the optimized specific on-resistance of SemiSJ trench MOSFETs can be reduced by larger than12%as aspect ratio equaling three, as compared with that of SJ trench MOSFETs. The effect of charge imbalance on the breakdown voltage is also investigated. It is found that the maximum BV is achieved at positive charge imbalance condition rather than at charge balance condition.
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