高性能DSP关键电路及EDA技术研究
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摘要
数字信号处理器(Digital Signal Processor:DSP)是一种专用于数字信号处理的嵌入式处理器,拥有强大的运算能力。在无线通信、多媒体、便携式数字终端、医疗设备、计算机网络、雷达和精确制导武器等领域有广泛应用。改进电路设计是提高DSP性能的有效方法,改进电路设计包括采用先进的电路技术和先进的电路设计方法,而EDA技术是设计方法中非常关键的一个要素。本文以600MHz YHFT-DSP/MHM数据通路的设计为背景,从关键电路和EDA技术两个方面入手,对高性能DSP的电路设计技术进行了深入研究,并取得了以下成果:
1.为了降低动态电路的功耗,避免或减少同步开销,提出了有限动态电路设计方法。阐述了有限动态电路设计方法的基本思想,结合一个32位加法器环路的设计,系统介绍了有限动态电路设计方法的关键技术:动态电路的选择与设计,时钟设计,延迟预充技术,双态电路和抗噪声设计方法。实验结果表明:有限动态电路的速度略优于完全动态电路,功耗降低了52.78%。
2.针对13读/9写寄存器文件的设计,提出了端口复用技术,将寄存器单元端口的数目和译码器的数目均减少了7个,并完成了与端口复用相关电路的设计。提出了沟道增长Dual-Vt位线技术,通过增加Dual-Vt位线结构中高阈值器件的栅长,获得了更快的速度,并改善了电路的噪声特性。实验结果表明,在90nm工艺中,沟道增长Dual-Vt位线结构的主要指标均优于伪静态位线结构,与LBSF位线结构相比功耗降低了28.5%,漏电流降低了99.78%,面积增加了9.5%。
3.基于二位Booth乘法,提出了16位混合乘法器的算法。与同类型研究相比部分积减少了6个,面积、延时和功耗的改善均超过了20%。在180nm工艺下完成了乘法器的全定制设计优化和测试芯片的设计,提出并实现了一种通用、灵活、低成本的模块级电路测试方案。测试结果表明,芯片的工作频率在SIMD模式下高于475.2 MHz,在普通模式下介于404.8MHz和475.2MHz之间。
4.完成了全定制电路功能模型提取关键算法的研究,实现了一个功能模型提取工具TranSpirit。实验结果表明TranSpirit具有很高的效率,能够满足模块级全定制设计功能验证的要求。
5.阐述了晶体管级混合时序分析方法的基本思想和流程,提出了考虑MIS效应的最大延时和最小延时测试波形生成算法,实现了一个晶体管级混合时序分析工具SpiceTime。与Hspice相比,SpiceTime具有更高的分析效率,而且最大延时的误差不超过2.89%,最小延时的误差不超过7%。
6.研究了有限动态电路时序验证方法。基于四事件周期模型,研究并总结了HI-CMOS、LO-CMOS、NTP动态门和N-C~2MOS锁存器正确工作所需要满足的时序约束;率先将混合时序分析方法应用于动态电路的延时计算,提出了动态门延时测试波形的生成算法。有限动态电路的时序验证方法已经在SpiceTime中得到了实现,并且应用于32位加法器环路的设计验证。该方法提高了设计效率,帮助发现了设计中存在的问题。如果不考虑伪路径的影响,求值方向和预充方向延时的最大误差分别为3.62%和8.26%。
本文的研究为YHFF-DSP/MHM数据通路的设计提供了可行的设计方案,为进一步研究如何提高DSP的电路设计技术奠定了坚实的基础。
Digital signal processors (DSPs), a class of embedded microprocessors optimized for digital signal processing, have become a key component in many multimedia appliances, communication devices, medical instruments, and industrial products. Improving circuit designs, such as employing advanced circuits and new circuit design methodology, are vital to enhance the performance of DSPs. EDA techniques play an important role in design methodology. The circuit design techniques of high performance DSPs are researched in this thesis, with an emphasis on key circuits and EDA techniques. The main contributions are as follows:
1. To reduce the power of dynamic circuits, limited dynamic circuit design methodology has been proposed. Combining with the design of a 32-bit adder loop, the key techniques of this methodology are introduced, such as selection and design of dynamic circuits, clock design, delayed precharge, dual-mode circuits, and noise control method. Simulation results showed that dynamic power has been reduced by 52.78% when compared to fully dynamic circuits.
2. Port multiplex techniques has been proposed in the design of a register file with 13 read ports and 9 write ports. The number of decoders and the ports of register cells have been both reduced by seven. Channel-enhanced Dual-Vt bitline has been proposed to improve the noise stability and to reduce leakage power of the dynamic read bitlines. For 90nm CMOS process, the proposed bitline has great advantage over the pseudostatic bitline. Compared to LBSF bitline, dynamic power is reduced by 28.5% and the leakage power is reduced by 2-3 orders with an area overhead of 9.5%.
3. An algorithm of a 16-bit hybrid multiplier has been proposed. The proposed algorithm is based on the radix-4 modified Booth's algorithm. The algorithm generates ten partial products and one modifier, which is six less than the other algorithms. The delay, power and area are all reduced by more than 20%. The multiplier has been designed in 180nm CMOS process by full custom design and a test chip has been fabricated. The test results showed the multiplier works well at 404.8MHz in normal mode, and 475.2MHz in SIMD mode.
4. Key algorithms for functional model extraction of transistor-level circuits have been proposed. A transistor-level functional model extractor named TranSpirit has been coded in C/C++. The experimental results showed TranSpirit has high speed and can meet the functional verification requirements of unit-level full custom designs.
5. Key techniques of transistor-level hybrid timing analysis methods have been studied. Test waveform generation algorithms for max and min delay considering multiple inputs simultaneous switching have been proposed. A transistor-level hybrid timing analysis tool named SpiceTime is coded in C/C++. The errors of max and min delay of SpiceTime are less than 2.89% and 7% respectively when compared to Hspice. Experimental results showed that SpiceTime has higher efficiency than Hspice. The effect of multiple inputs simultaneous switching on path delay has also been studied.
6. Timing verification of limited dynamic circuits has been studied. Based on the four-event periodic waveform models, the timing constraints for HI-CMOS, LO-CMOS, NTP dynamic circuits and N-C~2MOS have been constructed. Hybrid timing analysis method has been applied to calculate the delay of dynamic circuits for the first time. Delay test waveform generation algorithms for dynamic circuits have been proposed. The algorithms have been implemented in SpiceTime and applied to the design of a 32-bit adder based on limited dynamic circuits. It helped to increase the design efficiency and find several design problems. Without false paths, the errors of evaluation delay and precharge delay are within 3.62% and 8.26% respectively.
The research in this dissertation provides a practical solution for implementing the datapath of YHFT-DSP/MHM. The research lays a solid foundation for further investigation on high performance DSP designs.
1.为了降低动态电路的功耗,避免或减少同步开销,提出了有限动态电路设计方法。阐述了有限动态电路设计方法的基本思想,结合一个32位加法器环路的设计,系统介绍了有限动态电路设计方法的关键技术:动态电路的选择与设计,时钟设计,延迟预充技术,双态电路和抗噪声设计方法。实验结果表明:有限动态电路的速度略优于完全动态电路,功耗降低了52.78%。
2.针对13读/9写寄存器文件的设计,提出了端口复用技术,将寄存器单元端口的数目和译码器的数目均减少了7个,并完成了与端口复用相关电路的设计。提出了沟道增长Dual-Vt位线技术,通过增加Dual-Vt位线结构中高阈值器件的栅长,获得了更快的速度,并改善了电路的噪声特性。实验结果表明,在90nm工艺中,沟道增长Dual-Vt位线结构的主要指标均优于伪静态位线结构,与LBSF位线结构相比功耗降低了28.5%,漏电流降低了99.78%,面积增加了9.5%。
3.基于二位Booth乘法,提出了16位混合乘法器的算法。与同类型研究相比部分积减少了6个,面积、延时和功耗的改善均超过了20%。在180nm工艺下完成了乘法器的全定制设计优化和测试芯片的设计,提出并实现了一种通用、灵活、低成本的模块级电路测试方案。测试结果表明,芯片的工作频率在SIMD模式下高于475.2 MHz,在普通模式下介于404.8MHz和475.2MHz之间。
4.完成了全定制电路功能模型提取关键算法的研究,实现了一个功能模型提取工具TranSpirit。实验结果表明TranSpirit具有很高的效率,能够满足模块级全定制设计功能验证的要求。
5.阐述了晶体管级混合时序分析方法的基本思想和流程,提出了考虑MIS效应的最大延时和最小延时测试波形生成算法,实现了一个晶体管级混合时序分析工具SpiceTime。与Hspice相比,SpiceTime具有更高的分析效率,而且最大延时的误差不超过2.89%,最小延时的误差不超过7%。
6.研究了有限动态电路时序验证方法。基于四事件周期模型,研究并总结了HI-CMOS、LO-CMOS、NTP动态门和N-C~2MOS锁存器正确工作所需要满足的时序约束;率先将混合时序分析方法应用于动态电路的延时计算,提出了动态门延时测试波形的生成算法。有限动态电路的时序验证方法已经在SpiceTime中得到了实现,并且应用于32位加法器环路的设计验证。该方法提高了设计效率,帮助发现了设计中存在的问题。如果不考虑伪路径的影响,求值方向和预充方向延时的最大误差分别为3.62%和8.26%。
本文的研究为YHFF-DSP/MHM数据通路的设计提供了可行的设计方案,为进一步研究如何提高DSP的电路设计技术奠定了坚实的基础。
Digital signal processors (DSPs), a class of embedded microprocessors optimized for digital signal processing, have become a key component in many multimedia appliances, communication devices, medical instruments, and industrial products. Improving circuit designs, such as employing advanced circuits and new circuit design methodology, are vital to enhance the performance of DSPs. EDA techniques play an important role in design methodology. The circuit design techniques of high performance DSPs are researched in this thesis, with an emphasis on key circuits and EDA techniques. The main contributions are as follows:
1. To reduce the power of dynamic circuits, limited dynamic circuit design methodology has been proposed. Combining with the design of a 32-bit adder loop, the key techniques of this methodology are introduced, such as selection and design of dynamic circuits, clock design, delayed precharge, dual-mode circuits, and noise control method. Simulation results showed that dynamic power has been reduced by 52.78% when compared to fully dynamic circuits.
2. Port multiplex techniques has been proposed in the design of a register file with 13 read ports and 9 write ports. The number of decoders and the ports of register cells have been both reduced by seven. Channel-enhanced Dual-Vt bitline has been proposed to improve the noise stability and to reduce leakage power of the dynamic read bitlines. For 90nm CMOS process, the proposed bitline has great advantage over the pseudostatic bitline. Compared to LBSF bitline, dynamic power is reduced by 28.5% and the leakage power is reduced by 2-3 orders with an area overhead of 9.5%.
3. An algorithm of a 16-bit hybrid multiplier has been proposed. The proposed algorithm is based on the radix-4 modified Booth's algorithm. The algorithm generates ten partial products and one modifier, which is six less than the other algorithms. The delay, power and area are all reduced by more than 20%. The multiplier has been designed in 180nm CMOS process by full custom design and a test chip has been fabricated. The test results showed the multiplier works well at 404.8MHz in normal mode, and 475.2MHz in SIMD mode.
4. Key algorithms for functional model extraction of transistor-level circuits have been proposed. A transistor-level functional model extractor named TranSpirit has been coded in C/C++. The experimental results showed TranSpirit has high speed and can meet the functional verification requirements of unit-level full custom designs.
5. Key techniques of transistor-level hybrid timing analysis methods have been studied. Test waveform generation algorithms for max and min delay considering multiple inputs simultaneous switching have been proposed. A transistor-level hybrid timing analysis tool named SpiceTime is coded in C/C++. The errors of max and min delay of SpiceTime are less than 2.89% and 7% respectively when compared to Hspice. Experimental results showed that SpiceTime has higher efficiency than Hspice. The effect of multiple inputs simultaneous switching on path delay has also been studied.
6. Timing verification of limited dynamic circuits has been studied. Based on the four-event periodic waveform models, the timing constraints for HI-CMOS, LO-CMOS, NTP dynamic circuits and N-C~2MOS have been constructed. Hybrid timing analysis method has been applied to calculate the delay of dynamic circuits for the first time. Delay test waveform generation algorithms for dynamic circuits have been proposed. The algorithms have been implemented in SpiceTime and applied to the design of a 32-bit adder based on limited dynamic circuits. It helped to increase the design efficiency and find several design problems. Without false paths, the errors of evaluation delay and precharge delay are within 3.62% and 8.26% respectively.
The research in this dissertation provides a practical solution for implementing the datapath of YHFT-DSP/MHM. The research lays a solid foundation for further investigation on high performance DSP designs.
引文
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