12bit-100MHz流水线模数转换器关键单元的研究与设计
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摘要
随着人类对数字生活的依赖日益加深,模拟器件的生存空间愈见兴旺,归根结底都是来源于真实感官世界的需求。自然界是一个模拟的世界,人们以模拟的方式对其进行感知和改造,作为数字领域与模拟世界的连接桥梁,模数转换器已成为现代电子系统必不可少的关键部分。如何提高模数转换器的性能、降低功耗、控制成本成为一个重要问题。流水线结构模数转换器以其高速度、高精度的特性以及兼顾面积和功耗的要求而得到了广泛的应用。因此,本文主要对一种12bit、采样频率100MHz的流水线模数转换器进行了研究和设计。
本文首先从流水线模数转换器的基本原理入手,通过分析其主要性能参数、1.5bit/级数字校正原理及非理想特性与误差来源,对其作系统级优化设计,并提出一种共享运算放大器的改进型可重构流水线结构。该结构有两种工作模式:模式1为12bit、采样频率100MHz的8级流水线模数转换器;模式2为9bit、采样频率50MHz的双通道5级流水线模数转换器,两种工作模式通过一组互斥开关相互切换。与传统结构相比,本文提出的改进型可重构流水线结构的运算放大器数量节省了近一半。最后给出了流水线级对运算放大器的要求及指标的计算方法,并对流水线模数转换器的关键单元电路如运算放大器、比较器、MDAC、线性开关做了设计与仿真。
As mankind's reliance on digital life strengthens day by day, see prosperous in the living space of the simulation device, all stem from the world demand of true sense organ after all. The nature is a world of analog, people perceive and transform it in a manner of analog, as the connection bridge of the digital field and analog world, A/D converter become an essential key part of modern electronic system. How to improve the performance of the A/D converter, reduce the power consumption, control the cost to become an important problem. Pipeline structural A/D converter is widely used because of its high-speed, high-accuracy characteristic and compromise of chip area and power consumption. So, This paper studies the pipeline A/D converter which is designed a kind of 12bit, sampling frequency 100MHz.
This paper proceeds with basic principle of the pipeline A/D converter at first, through analyzing its main performance parameter, 1.5bit /stage digital calibration principle, non-ideal characteristic and error source, do a grade of system optimization, then propose a kind of improved sharing operational amplifier reconfigurable structure of pipeline A/D converter. This structure has two kinds of work pattern: Mode 1 is 8 stages pipeline A/D converter of 12bit, sampling frequency 100MHz; The mode 2 is 5 stages dual-channels pipeline A/D converter of 9bit, sampling frequency 50MHz, the two work patterns switch over each other through a group of mutual exclusion switches. Compared with traditional structure, the improved reconfigurable pipeline A/D converter structure that This paper put forward can save nearly half operational amplifier. At last this paper provide the pipeline stage’s requirements for operational amplifier and parameter calculation,, and then design and simulation the key block circuit of the pipeline A/D converter such as operational amplifier, comparator, MDAC, linear switch..
本文首先从流水线模数转换器的基本原理入手,通过分析其主要性能参数、1.5bit/级数字校正原理及非理想特性与误差来源,对其作系统级优化设计,并提出一种共享运算放大器的改进型可重构流水线结构。该结构有两种工作模式:模式1为12bit、采样频率100MHz的8级流水线模数转换器;模式2为9bit、采样频率50MHz的双通道5级流水线模数转换器,两种工作模式通过一组互斥开关相互切换。与传统结构相比,本文提出的改进型可重构流水线结构的运算放大器数量节省了近一半。最后给出了流水线级对运算放大器的要求及指标的计算方法,并对流水线模数转换器的关键单元电路如运算放大器、比较器、MDAC、线性开关做了设计与仿真。
As mankind's reliance on digital life strengthens day by day, see prosperous in the living space of the simulation device, all stem from the world demand of true sense organ after all. The nature is a world of analog, people perceive and transform it in a manner of analog, as the connection bridge of the digital field and analog world, A/D converter become an essential key part of modern electronic system. How to improve the performance of the A/D converter, reduce the power consumption, control the cost to become an important problem. Pipeline structural A/D converter is widely used because of its high-speed, high-accuracy characteristic and compromise of chip area and power consumption. So, This paper studies the pipeline A/D converter which is designed a kind of 12bit, sampling frequency 100MHz.
This paper proceeds with basic principle of the pipeline A/D converter at first, through analyzing its main performance parameter, 1.5bit /stage digital calibration principle, non-ideal characteristic and error source, do a grade of system optimization, then propose a kind of improved sharing operational amplifier reconfigurable structure of pipeline A/D converter. This structure has two kinds of work pattern: Mode 1 is 8 stages pipeline A/D converter of 12bit, sampling frequency 100MHz; The mode 2 is 5 stages dual-channels pipeline A/D converter of 9bit, sampling frequency 50MHz, the two work patterns switch over each other through a group of mutual exclusion switches. Compared with traditional structure, the improved reconfigurable pipeline A/D converter structure that This paper put forward can save nearly half operational amplifier. At last this paper provide the pipeline stage’s requirements for operational amplifier and parameter calculation,, and then design and simulation the key block circuit of the pipeline A/D converter such as operational amplifier, comparator, MDAC, linear switch..
引文
[1] Phillip E Allen, Douglas R Holberg. CMOS模拟集成电路设计.第二版.冯军,李智群译.北京:电子工业出版社, 2005: 60-65
[2] R. J. Baker. CMOS电路设计布局与仿真.陈中建译.北京:机械工业出版社, 2006: 579-644
[3] Sunghyun Park, Palaskas. A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 2007,42(9): 1865–1872
[4] Kertis R.A, Humble J.S, Daun-Lindberg M.A. A 35 GS/s 5-Bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008.Oct: 252–255
[5] Daejeong Kim, Jaejin Park, Sungjoon Kim. A single chipΔ-ΣADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE Journal of Solid-State Circuits, 1995,30(8):940-943
[6] Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits, 2005,40(5):1047-1056
[7] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003:51-112
[8]孙磊,安建平,武岩波.信号串扰对高速模数转换器性能影响的分析.数据采集与处理, 2008,23(4):486-491
[9] Stephen H. Lewis, Paul R. Gray, A pipelined 5-Msample_s 9-bit analog-to-digital converter. IEEE Journal of Solid-State Circuits, 1987,22(6):954-961
[10] Stephen H. Lewis. Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-rate Applications. IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing, 1992,39(8):516-523
[11]董庆祥.数字校对技术在流水线ADC中的应用.电子器件.2005,28(4):878-881
[12] Lewis S H ,Fetterman H,Gross G. A 10-b 20 M sample/s analog-to-digitalconverter . I EEE J Solid2 S tate Ci rcuits ,1992 ,27:351-358
[13] Shang-yuan(sean) Chung, Terry L, Sculey. A digitally self-calibrating 14-bit 10MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002,37(6): 674-583
[14] Gines A. J., Peralias E. J., Rueda A. Full calibration digital techniques for pipeline ADCs. IEEE International Symposium on Circuits and Systems, May 2005: 1976-1979
[15] Xiaopeng Li, Bugeja A. R.. Ismail M., A fast and accurate calibration method for high-speed high-resolution pipeline ADC. IEEE International Symposium on Circuits and Systems, May 2002: 26-29
[16]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003:239-278
[17]施宇峰,许俊,任俊彦,陈诚.一种改进的流水线模数转换器结构.复旦学报, 2005,44(6):977-982
[18] Chuang S-Y., Scullery T. A digital self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-683
[19]吕彦诗,张晓林,张超.并行流水线模数转换器.电子测量技术, 2005,6:63-64
[20] Luuri Sumunen, Mikko Wulturi, Kuri Hulonen. A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters. The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000. Volume 1, 17-20 Dec. 2000:32-35
[21] Vipul Katyal, Randall L. Geiger and Degang J. Chen. A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs. IEEE Asia Pacific Conference on Circuits and Systems, 2006. 4-7 Dec. 2006:5-8
[22]宁宁,于奇,王向展.高速CMOS预放大-锁存比较器设计.微电子学, 2005,35(1):56-62
[23]胡晓宇,周玉梅.一种用于14bit50MHz流水线模数转换器的CMOS采样开关.半导体学报, 2007,28(9):1488-1493
[24] Chouia Y, El-Sankary K, Saleh A , et al. 14b, 50MS/ s CMOS front-end sample and hold module dedicated to a pipelined ADC. The 2004 47th Midwest Symposium onVolume 1,2004,25～28:353
[25]陈霞. 12位50Msps流水线A/D转换器的研究与设计: [硕士学位论文].西安:西安电子科技大学图书馆, 2007
[26]严奇. 10位40MHz流水线模数转换器的设计: [硕士学位论文].西安:西安电子科技大学图书馆, 2006
[27] Robert Wang. A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology: [Master Thesis]. University of Toronto, 2004
[28] Chang-Hyuk Cho. A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology: [Master Thesis]. Georgia Institute of Technology, 2005
[29]高彬,孟桥,沈志远.基于0.18μmCMOS工艺的超高速比较器,微电子学, 2007,37(4):599-602
[30]杨赟秀,罗静芳,宁宁,于奇.新型高速低功耗CMOS预放大锁存比较器,微电子学, 2006,36(2):213-216
[31]王波.高速CMOS A/D转换器的设计研究: [硕士学位论文].西安:西安电子科技大学图书馆, 2007
[32]陈曦.高性能流水线型模数转换器集成电路的设计: [硕士学位论文].浙江:浙江大学图书馆, 2006
[33] Mikko Waltari, Kari A. I. Halonen. 1-V 9-bit pipelined switched-opamp ADC. IEEE Journal of Solid-State Circuits, 2001,36(1): 129-134
[34]孔晓彬.基于CMOS工艺的流水线A_D转换器的实现:[硕士学位论文].浙江:浙江大学图书馆, 2006
[35] Troy Lynn stockstad. Techniques for design of low voltage, high-speed operational amplifiers: [PH.D Thesis]. Arizona state university, 1997
[36] J.Ramirez-Angulo, M.Holmes. Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps. Electronics letter, 2002,38(23):1409-1411
[37] Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio, JoséSilva-Martínez. Nonlinear effects in pseudo differential OTAs with CMFB. IEEE Transactions on Circuits andSystem-II: Analog and Digital Signal Processing, 2003,50(10):762-770
[38] Jie Yan. Strategies for enhancing DC gain and settling performance of amplifiers: [PH.D Thesis]. Iowa state university, 2002
[39] T. B. Cho, P. R. Gray. A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE Journal of Solid-State Circuits, 1995,30(3): 166-172
[40]胡小波. 12位40兆采样频率流水线结构模数转换器: [硕士学位论文].武汉:华中科技大学图书馆, 2004
[2] R. J. Baker. CMOS电路设计布局与仿真.陈中建译.北京:机械工业出版社, 2006: 579-644
[3] Sunghyun Park, Palaskas. A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 2007,42(9): 1865–1872
[4] Kertis R.A, Humble J.S, Daun-Lindberg M.A. A 35 GS/s 5-Bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008.Oct: 252–255
[5] Daejeong Kim, Jaejin Park, Sungjoon Kim. A single chipΔ-ΣADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE Journal of Solid-State Circuits, 1995,30(8):940-943
[6] Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits, 2005,40(5):1047-1056
[7] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003:51-112
[8]孙磊,安建平,武岩波.信号串扰对高速模数转换器性能影响的分析.数据采集与处理, 2008,23(4):486-491
[9] Stephen H. Lewis, Paul R. Gray, A pipelined 5-Msample_s 9-bit analog-to-digital converter. IEEE Journal of Solid-State Circuits, 1987,22(6):954-961
[10] Stephen H. Lewis. Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-rate Applications. IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing, 1992,39(8):516-523
[11]董庆祥.数字校对技术在流水线ADC中的应用.电子器件.2005,28(4):878-881
[12] Lewis S H ,Fetterman H,Gross G. A 10-b 20 M sample/s analog-to-digitalconverter . I EEE J Solid2 S tate Ci rcuits ,1992 ,27:351-358
[13] Shang-yuan(sean) Chung, Terry L, Sculey. A digitally self-calibrating 14-bit 10MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002,37(6): 674-583
[14] Gines A. J., Peralias E. J., Rueda A. Full calibration digital techniques for pipeline ADCs. IEEE International Symposium on Circuits and Systems, May 2005: 1976-1979
[15] Xiaopeng Li, Bugeja A. R.. Ismail M., A fast and accurate calibration method for high-speed high-resolution pipeline ADC. IEEE International Symposium on Circuits and Systems, May 2002: 26-29
[16]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003:239-278
[17]施宇峰,许俊,任俊彦,陈诚.一种改进的流水线模数转换器结构.复旦学报, 2005,44(6):977-982
[18] Chuang S-Y., Scullery T. A digital self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-683
[19]吕彦诗,张晓林,张超.并行流水线模数转换器.电子测量技术, 2005,6:63-64
[20] Luuri Sumunen, Mikko Wulturi, Kuri Hulonen. A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters. The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000. Volume 1, 17-20 Dec. 2000:32-35
[21] Vipul Katyal, Randall L. Geiger and Degang J. Chen. A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs. IEEE Asia Pacific Conference on Circuits and Systems, 2006. 4-7 Dec. 2006:5-8
[22]宁宁,于奇,王向展.高速CMOS预放大-锁存比较器设计.微电子学, 2005,35(1):56-62
[23]胡晓宇,周玉梅.一种用于14bit50MHz流水线模数转换器的CMOS采样开关.半导体学报, 2007,28(9):1488-1493
[24] Chouia Y, El-Sankary K, Saleh A , et al. 14b, 50MS/ s CMOS front-end sample and hold module dedicated to a pipelined ADC. The 2004 47th Midwest Symposium onVolume 1,2004,25～28:353
[25]陈霞. 12位50Msps流水线A/D转换器的研究与设计: [硕士学位论文].西安:西安电子科技大学图书馆, 2007
[26]严奇. 10位40MHz流水线模数转换器的设计: [硕士学位论文].西安:西安电子科技大学图书馆, 2006
[27] Robert Wang. A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology: [Master Thesis]. University of Toronto, 2004
[28] Chang-Hyuk Cho. A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology: [Master Thesis]. Georgia Institute of Technology, 2005
[29]高彬,孟桥,沈志远.基于0.18μmCMOS工艺的超高速比较器,微电子学, 2007,37(4):599-602
[30]杨赟秀,罗静芳,宁宁,于奇.新型高速低功耗CMOS预放大锁存比较器,微电子学, 2006,36(2):213-216
[31]王波.高速CMOS A/D转换器的设计研究: [硕士学位论文].西安:西安电子科技大学图书馆, 2007
[32]陈曦.高性能流水线型模数转换器集成电路的设计: [硕士学位论文].浙江:浙江大学图书馆, 2006
[33] Mikko Waltari, Kari A. I. Halonen. 1-V 9-bit pipelined switched-opamp ADC. IEEE Journal of Solid-State Circuits, 2001,36(1): 129-134
[34]孔晓彬.基于CMOS工艺的流水线A_D转换器的实现:[硕士学位论文].浙江:浙江大学图书馆, 2006
[35] Troy Lynn stockstad. Techniques for design of low voltage, high-speed operational amplifiers: [PH.D Thesis]. Arizona state university, 1997
[36] J.Ramirez-Angulo, M.Holmes. Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps. Electronics letter, 2002,38(23):1409-1411
[37] Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio, JoséSilva-Martínez. Nonlinear effects in pseudo differential OTAs with CMFB. IEEE Transactions on Circuits andSystem-II: Analog and Digital Signal Processing, 2003,50(10):762-770
[38] Jie Yan. Strategies for enhancing DC gain and settling performance of amplifiers: [PH.D Thesis]. Iowa state university, 2002
[39] T. B. Cho, P. R. Gray. A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE Journal of Solid-State Circuits, 1995,30(3): 166-172
[40]胡小波. 12位40兆采样频率流水线结构模数转换器: [硕士学位论文].武汉:华中科技大学图书馆, 2004