纳米MOS器件中的量子效应分析及其模拟
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摘要
本课题描述了纳米体MOS器件中的量子隧穿效应和能量量子化效应的物理机制,用自洽求解薛定谔-泊松方程组的方法模拟了直接隧穿导致的栅隧穿漏电流和能级量子化导致的栅电容退化。
采用基于自洽求解薛定谔-泊松方程组的量子修正方法,研究分布于量子化离散子能级上的载流子反型层电荷密度分布和栅极电压之间的关系。建立考虑了能量量子化对载流子分布影响的C-V特性的量子修正模型,并模拟预测了纳米MOS器件的C-V特性,模拟表明纳米MOS器件的栅电容显著退化。同时通过该量子修正方法,量子修正了栅极隧穿的解析结果,模拟预测了不同栅极和不同绝缘材料对栅隧穿漏电流的影响;模型的结果与长沟MOSFETs的实验结果和短沟MOSFETs的数值计算的结果吻合很好,从而验证了文中的分析;同时模拟结果也验证了高κ栅介质取代栅氧化物的优越性。
本文对发展物理基础模型和充分诠释及模拟小尺寸MOS器件的研究提供有力的引导,为革新器件观念和纳米MOS时代的有创意的结构设计做了基础铺垫。
In this thesis, the physical mechanism and the quantum corrected model of the advanced nano-scale bulk MOSFETs is represented. The gate leakage current induced by direct tunneling and the degradation of the gate capacitor induced by energy quantization are simulated using the self-consistent method by solving the coupled Poisson and Schr?dinger equations.
The quantum mechanism effects on the carrier distribution are studied by self-consistent solving the coupled Poisson and Schr?dinger equations. The relationship between the charge density and gate bias in MOSFETs is then simulated. Based on these results, the quantum capacitor-voltage model including the quantum mechanism effects is derived, and the capacitor-voltage characteristics of the bulk MOS devices are simulated. The analytical results of the gate tunneling are modified in quantum theory, the impact of the different gate electrodes on the gate direct tunneling current is simulated as well as the different gate insulation materials. Results from this model show a good agreement with the experimental results and the numeric simulation results of both long-channel and short-channel MOSFETs, and the simulation results shows the advantages of high-κgate dielectrics over traditional oxide.
The simulation results in this thesis provide the strong guides for the development of the physics-based models and the comprehensive understanding to the scaled MOS devices, and pave the way to the novel device concepts and the innovative structure design in nano-MOSFET age.
采用基于自洽求解薛定谔-泊松方程组的量子修正方法,研究分布于量子化离散子能级上的载流子反型层电荷密度分布和栅极电压之间的关系。建立考虑了能量量子化对载流子分布影响的C-V特性的量子修正模型,并模拟预测了纳米MOS器件的C-V特性,模拟表明纳米MOS器件的栅电容显著退化。同时通过该量子修正方法,量子修正了栅极隧穿的解析结果,模拟预测了不同栅极和不同绝缘材料对栅隧穿漏电流的影响;模型的结果与长沟MOSFETs的实验结果和短沟MOSFETs的数值计算的结果吻合很好,从而验证了文中的分析;同时模拟结果也验证了高κ栅介质取代栅氧化物的优越性。
本文对发展物理基础模型和充分诠释及模拟小尺寸MOS器件的研究提供有力的引导,为革新器件观念和纳米MOS时代的有创意的结构设计做了基础铺垫。
In this thesis, the physical mechanism and the quantum corrected model of the advanced nano-scale bulk MOSFETs is represented. The gate leakage current induced by direct tunneling and the degradation of the gate capacitor induced by energy quantization are simulated using the self-consistent method by solving the coupled Poisson and Schr?dinger equations.
The quantum mechanism effects on the carrier distribution are studied by self-consistent solving the coupled Poisson and Schr?dinger equations. The relationship between the charge density and gate bias in MOSFETs is then simulated. Based on these results, the quantum capacitor-voltage model including the quantum mechanism effects is derived, and the capacitor-voltage characteristics of the bulk MOS devices are simulated. The analytical results of the gate tunneling are modified in quantum theory, the impact of the different gate electrodes on the gate direct tunneling current is simulated as well as the different gate insulation materials. Results from this model show a good agreement with the experimental results and the numeric simulation results of both long-channel and short-channel MOSFETs, and the simulation results shows the advantages of high-κgate dielectrics over traditional oxide.
The simulation results in this thesis provide the strong guides for the development of the physics-based models and the comprehensive understanding to the scaled MOS devices, and pave the way to the novel device concepts and the innovative structure design in nano-MOSFET age.
引文
[1]л.д.朗道,ЕМ.栗弗席茨著.量子力学教程[M].北京:人民教育出版社,1981.
[2]黄昆著.固体物理学[M].第四、五章.北京:高等教育出版社,1985.
[3]杜磊,庄亦琪.纳米电子学[M].北京:电子工业出版社,2004.11.
[4]叶良修.小尺寸半导体器件的蒙特卡罗模拟[M].北京:科学出版社,1997.
[5]甘学温,黄如,刘晓彦等.纳米CMOS器件[M].北京:科学出版社,2004.1.
[6] Int. Technology Roadmap of Semiconductors. Semiconductor Industry Association, 2003 ed, [Online] Available: www.public.itrs.net.
[7] W. Haensch, E. J. Nowak and R.H. Dennard et al…Silicon CMOS devices beyond scaling [J]. IBM J. RES. & DEV. 2006, Jul/Sep, Vol.50(No.4/5). 339-362.
[8] B. Yu, M. Meyyappan. Nanotechnology: Role in emerging nano-electronics [J]. Solid-State Electronics. 2006(50), 536–544.
[9] K. K. Likharev. New prospects for terabit integration [J]. Published Future Trends in Microelectronics. 1999,Wiley, New York, 323-338.
[10] http://www.intel.com/technology/45nm/index.htm?iid=homepage+tech_45nm.
[11] Konstantin Likharev. Sub-20-nm electron devices [J]. Advanced semiconductor and organic nano-echniques. 2002.
[12] Carlo de Falco, Emilio Gatti, Andrea L. Lacaita, and Riccardo Sacco. Quantum-corrected drift-diffusion models for transport in semiconductor devices[J]. Journal of Computational Physics. 2005, Apr, Vol.204(No.2). 533-561.
[13] Vinod Kumar Khanna. Physics of carrier-transport mechanisms and ultra-small scale phenomena for theoretical modelling of nanometer MOS transistors from diffusive to ballistic regimes of operation[J]. 2004, Physics Reports. 398. 67–70.
[14] Alexei Svizhenko and M. P. Anantram. Role of scattering in nano-transistors[J]. IEEE Transactions on electron devices. 2003, Jun, Vol.50(No.6).
[15] S. Mukhopadhyay, Arijit Raychowdhury, and Koushik Ray et al…Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile[J]. IEEE Trans. On CAD. 2005, March, Vol.24(no. 3). 363-380.
[16] David K. Ferry. The onset of quantization in ultra-submicron semiconductor devices[J]. Super-lattices and Microstructures. 2000,Vol.27(No.2/3).61-66.
[17] Khalid E. Ismail, Philip F. Bagwell and Terry P. Orlando et al…Quantumphenomena in field-effect-controlled semiconductor nanostructures[J]. Proceedings of The IEEE. 1991, Aug, Vol.79(No.8). 1106-1116.
[18] I.C.Chen, C.Kaya and J.Paterson. Band-to band tunneling induced substrate hot-electron injection: a new programming mechanism for nonvolatile memory devices [J]. IEDM. 1989,263-266.
[19] M. Koh, K. Iwamoto and W. Mizubayashi et al…Threshold voltage fluctuation induced by direct tunnel leakage current through 1.2-2.8 nm thick gate oxides for scaled MOSFETs[J]. IEEE IEDM 1998, 919-922.
[20] Yiming Li, Ting-wei Tang and Xinlin Wang. Modeling of quantum effects for ultrathin oxide MOS structures with an effective potential[J]. IEEE Transactions on nanotechnology. 2002, Dec, Vol.1(No.4). 238-242.
[21] Keiichi Morikawa, Hiroaki Ueno and Daisuke Kitamaru et al…Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition [J]. J. Appl. Phys. 2002, Apr, Vol.41(No.4).
[22] R. Difrenza, P. Llinares and G. Ghibaudo. The impact of short channel and quantum effects on the MOS transistor mismatch[J]. Solid-State Electronics. 2003, Jul, Vol.47(7). 1161-1165.
[23] Naoyuki Shigyo and Hiroyoshi Tanimoto. A new quantum effect model for practical device[J]. IEEE Transactions on electron devices. 2000, May, Vol.47(No.5). 1010-1012.
[24] Yong-Tian Hou and Ming-Fu Li. A simple and efficient model for quantization effects of hole inversion layers in MOS devices[J]. IEEE Transactions on electron devices. 2001, Dec, Vol.48(No.12).
[25] Victor A. Sverdlov, Thomas J. Walls, and Konstantin K. Likharev. Nano-scale Silicon MOSFETs: A Theoretical Study[J]. IEEE Transaction on electron devices. 2003, Sep, VOL.50(NO.9).
[26] A. Martinez, J.R. Barker and A. Svizhenko et al... The impact of unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFET: classical to full quantum simulation[J]. Journal of Physics: Conference Series, 2006, 38, 192-195.
[27] Zhiping Yu, Robert W. Dutton and Richard A. Kiehl. Circuit/Device modeling at the Quantum Level[J]. IEEE Transactions on electron devices. 2000, Oct, Vol. 47(No. 10). 1819-1825.
[28] Bryan A. Biegel, Mario G. Ancona and Conor S. Rafferty. Efficient multi-dimensional simulation of quantum confinement effects in advanced MOSdevices[J]. NAS Technical Report. 2004, Aug, NAS-04-008.
[29] R.Venugopal, Z.Ren, and M.Lundstrom. Simulating Quantum Transport in Nanoscale MOSFETs: Ballistic Hole transport, Subband Engineering and Boundary Conditions[J]. IEEE Trans. Nanotechnology. 2003, Sep, Vol. 2(No. 3). 135-143.
[30] Nian Yang,W.Kirklen Henson and John R.Hauser et al...Modeling stuty of Ultrathin gate oxide using direct tunneling Current and Capacitance-voltage measurements in MOS devices[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 1999, July, Vol.46(No.7). 1464-1471.
[31] E. Nadimi, C. Radehaus and E. P. Nakhmedova et al...Calculation of the direct tunneling current in a metal-oxide-semiconductor structure with one-side open boundary[J]. JOURNAL OF APPLIED PHYSICS. 2006, May, 99. 104501.
[32] J. R. Barkre, A. Martinez and A. Svizhenko et al... Green function study of quantum transport in ultra-small devices with embedded atomistic clusters[J]. Journal of physics: conference series. 2006, 35. 233-246.
[33] H. Abebe and E. Cumberbatch. Quantum mechanical effects correction models for inversion charge and current-voltage (I-V) characteristics of the MOSFET device[C]. The 2003 Nanotech Conference Proceedings. 2003, Feb, 23-27, San Francisco, U .S .A.
[34] Jin He, Mansun Chan, Xing Zhang, and Yangyuan Wang. A Physics-Based Analytic Solution to the MOSFET Surface Potential From Accumulation to Strong-Inversion Region[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2006, SEP, Vol. 53(No. 9). 2008-2016.
[35] Wen-Chin Lee, and Chenming Hu. Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2001, July, Vol. 48(No. 7).
[36] Wuyun Quan, Dae M. Kim and Hi-Deok Lee. Quantum C–V Modeling in Depletion and Inversion: Accurate Extraction of Electrical Thickness of Gate Oxide in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, MAY, VOL. 49(NO. 5). 889-894.
[37] M. M. A. Hakim and A. Haque. Effects of Neglecting Carrier Tunneling on Electrostatic Potential in Calculating Direct Tunneling Gate Current in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, Sep, Vol. 49(NO. 9). 1669-1671.
[38] Lihui Wang. Quantum mechanical effects on MOSFETs scaling [D]. Georgia Institute of Technology. School of ELECTRICAL AND COMPUTER ENGINEERINGon Graduate studies of Georgia Institute of Technology. July 6, 2006.
[39] Wuyun Quan, Dae M. Kim and Hi-Deok Lee. Quantum C–V Modeling in Depletion and Inversion: Accurate Extraction of Electrical Thickness of Gate Oxide in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2002, MAY, Vol. 49(No. 5). 889-894.
[40] C. Leroux, F. Allain and A. Toffoli et al... Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks[J]. Microelectronic Engineering. 2007,Apr, 84. 2408–2411.
[41] Lindert Shaikh S Ahmed and Dragica Vasileska. Modelling of narrow-width SOI devices[J]. Semicond. Sci. Technol. 2004, 19. 131-133.
[42] Yang-Kyu Choi, Kazuya Asano and Nick et al... Ultra-thin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era[J]. IEEE ELECTRON DEVICE LETTERS. 2000, MAY, Vol. 21( NO. 5). 254-255.
[43] T K Chiang. A novel scaling-parameter-dependent sub-threshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE)[J]. Semicond. Sci. Technol. 2004, 19. 1386–1390.
[44] A. Martinez1, J. R. Barker1, A. Svizhenko et al...The impact of unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFET: classical to full quantum simulation[J]. Journal of Physics: Conference Series. 2006, 38. 192–195.
[45] Yiming Li and Shao-Ming Yu. A unified quantum correction model for nano-scale single- and double-gate MOSFETs under inversion conditions [J]. Nanotechnology 15. 2004, 1009–1016.
[46] Bogdan Govoreanu, Pieter Blomme and Kirklen Henson et al...An Investigation of the Electron Tunneling Leakage Current through Ultra-thin Oxides/High-k Gate Stacks at Inversion Conditions [J]. IEEE 2003, 287-290.
[47] Huixian Wu, Yijie (Sandy) Zhao, Marvin H. White. Quantum mechanical modeling of MOSFET gate leakage for high-k gate dielectrics[J]. Solid-State Electronics. 2006, 50. 1164–1169.
[48] Fabien Pr_egaldiny, Christophe Lallement and Daniel Mathiot. Accounting for quantum mechanical effects from accumulation to inversion in a fully analytical surface-potential-based MOSFET model [J]. Solid-State Electronics 2004, 48. 781–787.
[2]黄昆著.固体物理学[M].第四、五章.北京:高等教育出版社,1985.
[3]杜磊,庄亦琪.纳米电子学[M].北京:电子工业出版社,2004.11.
[4]叶良修.小尺寸半导体器件的蒙特卡罗模拟[M].北京:科学出版社,1997.
[5]甘学温,黄如,刘晓彦等.纳米CMOS器件[M].北京:科学出版社,2004.1.
[6] Int. Technology Roadmap of Semiconductors. Semiconductor Industry Association, 2003 ed, [Online] Available: www.public.itrs.net.
[7] W. Haensch, E. J. Nowak and R.H. Dennard et al…Silicon CMOS devices beyond scaling [J]. IBM J. RES. & DEV. 2006, Jul/Sep, Vol.50(No.4/5). 339-362.
[8] B. Yu, M. Meyyappan. Nanotechnology: Role in emerging nano-electronics [J]. Solid-State Electronics. 2006(50), 536–544.
[9] K. K. Likharev. New prospects for terabit integration [J]. Published Future Trends in Microelectronics. 1999,Wiley, New York, 323-338.
[10] http://www.intel.com/technology/45nm/index.htm?iid=homepage+tech_45nm.
[11] Konstantin Likharev. Sub-20-nm electron devices [J]. Advanced semiconductor and organic nano-echniques. 2002.
[12] Carlo de Falco, Emilio Gatti, Andrea L. Lacaita, and Riccardo Sacco. Quantum-corrected drift-diffusion models for transport in semiconductor devices[J]. Journal of Computational Physics. 2005, Apr, Vol.204(No.2). 533-561.
[13] Vinod Kumar Khanna. Physics of carrier-transport mechanisms and ultra-small scale phenomena for theoretical modelling of nanometer MOS transistors from diffusive to ballistic regimes of operation[J]. 2004, Physics Reports. 398. 67–70.
[14] Alexei Svizhenko and M. P. Anantram. Role of scattering in nano-transistors[J]. IEEE Transactions on electron devices. 2003, Jun, Vol.50(No.6).
[15] S. Mukhopadhyay, Arijit Raychowdhury, and Koushik Ray et al…Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile[J]. IEEE Trans. On CAD. 2005, March, Vol.24(no. 3). 363-380.
[16] David K. Ferry. The onset of quantization in ultra-submicron semiconductor devices[J]. Super-lattices and Microstructures. 2000,Vol.27(No.2/3).61-66.
[17] Khalid E. Ismail, Philip F. Bagwell and Terry P. Orlando et al…Quantumphenomena in field-effect-controlled semiconductor nanostructures[J]. Proceedings of The IEEE. 1991, Aug, Vol.79(No.8). 1106-1116.
[18] I.C.Chen, C.Kaya and J.Paterson. Band-to band tunneling induced substrate hot-electron injection: a new programming mechanism for nonvolatile memory devices [J]. IEDM. 1989,263-266.
[19] M. Koh, K. Iwamoto and W. Mizubayashi et al…Threshold voltage fluctuation induced by direct tunnel leakage current through 1.2-2.8 nm thick gate oxides for scaled MOSFETs[J]. IEEE IEDM 1998, 919-922.
[20] Yiming Li, Ting-wei Tang and Xinlin Wang. Modeling of quantum effects for ultrathin oxide MOS structures with an effective potential[J]. IEEE Transactions on nanotechnology. 2002, Dec, Vol.1(No.4). 238-242.
[21] Keiichi Morikawa, Hiroaki Ueno and Daisuke Kitamaru et al…Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition [J]. J. Appl. Phys. 2002, Apr, Vol.41(No.4).
[22] R. Difrenza, P. Llinares and G. Ghibaudo. The impact of short channel and quantum effects on the MOS transistor mismatch[J]. Solid-State Electronics. 2003, Jul, Vol.47(7). 1161-1165.
[23] Naoyuki Shigyo and Hiroyoshi Tanimoto. A new quantum effect model for practical device[J]. IEEE Transactions on electron devices. 2000, May, Vol.47(No.5). 1010-1012.
[24] Yong-Tian Hou and Ming-Fu Li. A simple and efficient model for quantization effects of hole inversion layers in MOS devices[J]. IEEE Transactions on electron devices. 2001, Dec, Vol.48(No.12).
[25] Victor A. Sverdlov, Thomas J. Walls, and Konstantin K. Likharev. Nano-scale Silicon MOSFETs: A Theoretical Study[J]. IEEE Transaction on electron devices. 2003, Sep, VOL.50(NO.9).
[26] A. Martinez, J.R. Barker and A. Svizhenko et al... The impact of unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFET: classical to full quantum simulation[J]. Journal of Physics: Conference Series, 2006, 38, 192-195.
[27] Zhiping Yu, Robert W. Dutton and Richard A. Kiehl. Circuit/Device modeling at the Quantum Level[J]. IEEE Transactions on electron devices. 2000, Oct, Vol. 47(No. 10). 1819-1825.
[28] Bryan A. Biegel, Mario G. Ancona and Conor S. Rafferty. Efficient multi-dimensional simulation of quantum confinement effects in advanced MOSdevices[J]. NAS Technical Report. 2004, Aug, NAS-04-008.
[29] R.Venugopal, Z.Ren, and M.Lundstrom. Simulating Quantum Transport in Nanoscale MOSFETs: Ballistic Hole transport, Subband Engineering and Boundary Conditions[J]. IEEE Trans. Nanotechnology. 2003, Sep, Vol. 2(No. 3). 135-143.
[30] Nian Yang,W.Kirklen Henson and John R.Hauser et al...Modeling stuty of Ultrathin gate oxide using direct tunneling Current and Capacitance-voltage measurements in MOS devices[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 1999, July, Vol.46(No.7). 1464-1471.
[31] E. Nadimi, C. Radehaus and E. P. Nakhmedova et al...Calculation of the direct tunneling current in a metal-oxide-semiconductor structure with one-side open boundary[J]. JOURNAL OF APPLIED PHYSICS. 2006, May, 99. 104501.
[32] J. R. Barkre, A. Martinez and A. Svizhenko et al... Green function study of quantum transport in ultra-small devices with embedded atomistic clusters[J]. Journal of physics: conference series. 2006, 35. 233-246.
[33] H. Abebe and E. Cumberbatch. Quantum mechanical effects correction models for inversion charge and current-voltage (I-V) characteristics of the MOSFET device[C]. The 2003 Nanotech Conference Proceedings. 2003, Feb, 23-27, San Francisco, U .S .A.
[34] Jin He, Mansun Chan, Xing Zhang, and Yangyuan Wang. A Physics-Based Analytic Solution to the MOSFET Surface Potential From Accumulation to Strong-Inversion Region[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2006, SEP, Vol. 53(No. 9). 2008-2016.
[35] Wen-Chin Lee, and Chenming Hu. Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2001, July, Vol. 48(No. 7).
[36] Wuyun Quan, Dae M. Kim and Hi-Deok Lee. Quantum C–V Modeling in Depletion and Inversion: Accurate Extraction of Electrical Thickness of Gate Oxide in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, MAY, VOL. 49(NO. 5). 889-894.
[37] M. M. A. Hakim and A. Haque. Effects of Neglecting Carrier Tunneling on Electrostatic Potential in Calculating Direct Tunneling Gate Current in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, Sep, Vol. 49(NO. 9). 1669-1671.
[38] Lihui Wang. Quantum mechanical effects on MOSFETs scaling [D]. Georgia Institute of Technology. School of ELECTRICAL AND COMPUTER ENGINEERINGon Graduate studies of Georgia Institute of Technology. July 6, 2006.
[39] Wuyun Quan, Dae M. Kim and Hi-Deok Lee. Quantum C–V Modeling in Depletion and Inversion: Accurate Extraction of Electrical Thickness of Gate Oxide in Deep Submicron MOSFETs[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2002, MAY, Vol. 49(No. 5). 889-894.
[40] C. Leroux, F. Allain and A. Toffoli et al... Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks[J]. Microelectronic Engineering. 2007,Apr, 84. 2408–2411.
[41] Lindert Shaikh S Ahmed and Dragica Vasileska. Modelling of narrow-width SOI devices[J]. Semicond. Sci. Technol. 2004, 19. 131-133.
[42] Yang-Kyu Choi, Kazuya Asano and Nick et al... Ultra-thin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era[J]. IEEE ELECTRON DEVICE LETTERS. 2000, MAY, Vol. 21( NO. 5). 254-255.
[43] T K Chiang. A novel scaling-parameter-dependent sub-threshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE)[J]. Semicond. Sci. Technol. 2004, 19. 1386–1390.
[44] A. Martinez1, J. R. Barker1, A. Svizhenko et al...The impact of unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFET: classical to full quantum simulation[J]. Journal of Physics: Conference Series. 2006, 38. 192–195.
[45] Yiming Li and Shao-Ming Yu. A unified quantum correction model for nano-scale single- and double-gate MOSFETs under inversion conditions [J]. Nanotechnology 15. 2004, 1009–1016.
[46] Bogdan Govoreanu, Pieter Blomme and Kirklen Henson et al...An Investigation of the Electron Tunneling Leakage Current through Ultra-thin Oxides/High-k Gate Stacks at Inversion Conditions [J]. IEEE 2003, 287-290.
[47] Huixian Wu, Yijie (Sandy) Zhao, Marvin H. White. Quantum mechanical modeling of MOSFET gate leakage for high-k gate dielectrics[J]. Solid-State Electronics. 2006, 50. 1164–1169.
[48] Fabien Pr_egaldiny, Christophe Lallement and Daniel Mathiot. Accounting for quantum mechanical effects from accumulation to inversion in a fully analytical surface-potential-based MOSFET model [J]. Solid-State Electronics 2004, 48. 781–787.