多频段射频CMOS功率放大器的研究与设计
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摘要
射频功率放大器模块是无线通信收发器中的重要模块,主要应用于各种无线发射机中,它的作用是放大高频信号至所需的功率,并送至天线辐射出去。功率放大器作为射频收发机中功耗和体积最大的模块,其性能直接决定了整个射频收发机的体积、功耗和成本,因此研究射频CMOS功率放大器对实现单片射频收发机意义重大。
随着第三代移动通信标准的提出和应用,各种无线通信标准的发展对射频集成电路提出了多模式、多频段的新要求,也因此对收发机的射频部分提出了新的要求—具有多频段多模式工作的性能。本文通过深入分析射频CMOS功率放大器的系统结构和工作原理,并针对目前移动通信主流标准(GSM0.9GHz/PCS1.9GHz),设计了一个并行式多频段功率放大器。
首先本文对功率放大器的基本特点、主要性能指标,器件非线性的影响以及RLC网络进行了分析,对线性和非线性功率放大器进行了系统总结,然后研究了在CMOS工艺下,射频功率放大器的局限性,并用于指导功率放大器设计。
其次,本文详细研究了本文所关注的并行式多频段功率放大器的工作原理,对多频段输入输出阻抗匹配进行了深入的理论分析及其优化;针对CMOS工艺晶体管击穿电压低和跨导能力有限等缺点,本文在电路设计中采用单端三级拓扑结构;并且在偏置电路的设计中,实现了一个高精度,高电源抑制,电路实现简单,可用于低压的电流基准。设计的射频多频段A类功率放大器能同时满足输出功率,增益,效率和线性度的要求。
最后,基于TSMC 0.35μm RFCMOS工艺,采用Cadence的SpectreRF进行电路仿真。仿真结果表明,在使用片上电感后,在两个频段上1dB压缩点均大于22dBm,输出功率达到23dBm,功率增益为23dB,功率附加效率达到30%。
Power amplifier (PA) is the key block of the wireless communication transmitter in RF, whose function mainly determines the cost, the power and the size of the transceiver. In order to meet the requirements of low cost, low power and small size, RF transceiver needs a CMOS power amplifier.
With the development and application of the third wireless communication standards, multi-band and multi-mode application requirements are brought to RF IC design as well as the power amplifier of transceiver. Through the analysis of systematic structure and the basic theory of power amplifier, a concurrent multi-band power amplifier is presented according to the mobile communication standards, GSM0.9GHz and PCS1.9GHz.
Firstly, the basic charecteristic of power amplifier, non-linear effects of devices and RLC network are introduced and discussed. Then the limitations of the CMOS process for power amplifiers are proposed,and they will be used as the instructions of the design of power amplifer.
Secondly, the theory of concurrent power amplifier is studied and discussed in details as well as analysis and optimation of multi-band input and output match. Owing to the low breakdown voltage and limited transconductonce amplification ability of the CMOS process, the design of the single-ended three-stage topology is proposed. Besides in the application of bias circuits, a reference of high pricision and high power supply rejection (PSR) is presented which can also be used in low voltage supply application.
Finally, based on TSMC 0.35μm RFCMOS process, the multi-band power amplifer is simulated by Cadecce tool. The simulation results show that, the 1dB compression point is above 22dBm, the output power is 23dBm, the power gain is 23dB, and the peak power added efficiency (PAE) is 30%.
随着第三代移动通信标准的提出和应用,各种无线通信标准的发展对射频集成电路提出了多模式、多频段的新要求,也因此对收发机的射频部分提出了新的要求—具有多频段多模式工作的性能。本文通过深入分析射频CMOS功率放大器的系统结构和工作原理,并针对目前移动通信主流标准(GSM0.9GHz/PCS1.9GHz),设计了一个并行式多频段功率放大器。
首先本文对功率放大器的基本特点、主要性能指标,器件非线性的影响以及RLC网络进行了分析,对线性和非线性功率放大器进行了系统总结,然后研究了在CMOS工艺下,射频功率放大器的局限性,并用于指导功率放大器设计。
其次,本文详细研究了本文所关注的并行式多频段功率放大器的工作原理,对多频段输入输出阻抗匹配进行了深入的理论分析及其优化;针对CMOS工艺晶体管击穿电压低和跨导能力有限等缺点,本文在电路设计中采用单端三级拓扑结构;并且在偏置电路的设计中,实现了一个高精度,高电源抑制,电路实现简单,可用于低压的电流基准。设计的射频多频段A类功率放大器能同时满足输出功率,增益,效率和线性度的要求。
最后,基于TSMC 0.35μm RFCMOS工艺,采用Cadence的SpectreRF进行电路仿真。仿真结果表明,在使用片上电感后,在两个频段上1dB压缩点均大于22dBm,输出功率达到23dBm,功率增益为23dB,功率附加效率达到30%。
Power amplifier (PA) is the key block of the wireless communication transmitter in RF, whose function mainly determines the cost, the power and the size of the transceiver. In order to meet the requirements of low cost, low power and small size, RF transceiver needs a CMOS power amplifier.
With the development and application of the third wireless communication standards, multi-band and multi-mode application requirements are brought to RF IC design as well as the power amplifier of transceiver. Through the analysis of systematic structure and the basic theory of power amplifier, a concurrent multi-band power amplifier is presented according to the mobile communication standards, GSM0.9GHz and PCS1.9GHz.
Firstly, the basic charecteristic of power amplifier, non-linear effects of devices and RLC network are introduced and discussed. Then the limitations of the CMOS process for power amplifiers are proposed,and they will be used as the instructions of the design of power amplifer.
Secondly, the theory of concurrent power amplifier is studied and discussed in details as well as analysis and optimation of multi-band input and output match. Owing to the low breakdown voltage and limited transconductonce amplification ability of the CMOS process, the design of the single-ended three-stage topology is proposed. Besides in the application of bias circuits, a reference of high pricision and high power supply rejection (PSR) is presented which can also be used in low voltage supply application.
Finally, based on TSMC 0.35μm RFCMOS process, the multi-band power amplifer is simulated by Cadecce tool. The simulation results show that, the 1dB compression point is above 22dBm, the output power is 23dBm, the power gain is 23dB, and the peak power added efficiency (PAE) is 30%.
引文
[1] Matthew M. Radmanesh.射频与微波电子学(顾继慧,李鸣).北京:科学出版社,2006,145-155
[2]王志华,吴恩.CMOS射频集成电路的现状与进展.电子学报,2001,29(2):233-238
[3]黄广宇,胡勇,杨旭,等.基于CMOS的RFIC的发展现状.微电子学,2002,32(4):283-286
[4]张国燕,黄如,张兴,等.CMOS射频集成电路的研究进展.微电子学,2004,34(4):377-382.
[5] Thomas H. Lee. CMOS射频集成电路设计(余志平,周润德等).北京:电子工业出版社,2004,393-415,226-229
[6]池保勇.CMOS射频集成电路分析与设计.北京:清华大学出版社,2006,285-287
[7] Milton Feng. Device Technologies for RF Front-End Circuits in Next-Generation Wireless Communications. Proceedings of the IEEE, 2004, 92(2): 354-372
[8] Massimo Brandolini, Paolo Rossi, Danilo Manstretta, et al. Toward Multistandard Mobile Terminals--Fully Integrated Receivers Requirements and Architectures. IEEE Transactions on Microwave Theory and Techniques, 2005, 53(3): 1026-1038
[9] Frederick H.RAAB, Idealized Operation of the Class E Tuned Power Amplifier. IEEE Transactions on Circuits and Systems, December 1977, vol. CAS-24, NO.12: 725-735
[10] Chengzhou Wang, Mani Vaidyanathan, Lawrence E. Larson.A Capacitance Compensation Technique for Improved Linearity in CMOS Class-AB Power Amplifiers. IEEE Solid-State Circuits, 2004, 39(11): 1927-1937
[11] Christina F. Jou, Pang-Ruei Huang, Kuo-Hua Cheng.Design of a 0.25μm CMOS 5.35GHz Transcerver Front-end.IEEE International Conference on Electronics Circuits and Systems, 2003: 1090-1093
[12] R. S. Narayanaswam.RF CMOS Class C Power Amplifiers for Wireless Communications: [Dissertation]. California: University of California, Berkeley, 2001, 142-144
[13] Saikat Sarkar, Padmanava Sen, Arvind Raghavan, et al. Development of 2.4GHz RF Transceiver Front-end Chipset in 0.25μm CMOS.Proceedings of the 16th International Conference on VLSI Design, 2003: 1-6
[14] Yongwang Ding, Ramesh Harjani. A CMOS High Efficiency +22 dBm Linear Power Amplifier. IEEE Custom Integrated Circuits Conference, 2004: 557-560
[15] N. Srirattana, P. Sen, H. M. Park,et al. Linear RF CMOS Power Amplifier with ImprovedEfficiency and Linearity in Wide Power Levels. IEEE Radio Frequency Integrated Circuits Symposium, 2005: 251-254
[16] Jaemin Jang, Changkun Park, Haksun Kim, et al. A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE. IEEE Microwave and Wireless Components Letters, 2007, NO. 5, MAY 2007,17: 385-387
[17] Bon-Hyun Ku, Sang-Hyun Baek, Songcheol Hong. A X-Band CMOS Power Amplifier with On-Chip Transmission Line Transformers. IEEE Custom Integrated Circuits Conference, 2008: 523-526
[18] David Ngo, Chris Dragon, Julio Costa, et al.RF Silicon MOS Integrated Power Amplifier for Analog Cellular Applications. IEEE MTT-S Digest,1996 WE2A-7: 559-562
[19] David Su, William McFarland.A 2.5-V, 1-W Monolithic CMOS RF Power Amplifier. IEEE Custom Integrated Circuits Conference, 1997: 189-192
[20]郭德彬,周峰,唐璞山.一种900MHz 20mW CMOS功率放大器的设计.微电子学,2002,32(1):62-65
[21]宗国翼,朱恩,李智群.可用于无线局域网802.11a标准的5GHz CMOS功率放大器设计.电子器件,2005,28(1):161-163
[22]李亮,李文渊,王志功.2.4GHz CMOS功率放大器设计.电子器件,2006,29(2):349-350
[23]杨柯,王志功,李志群.0.18μm CMOS工艺5GHz WLAN功率放大器设计.电子工程师.2006,32(3):1-3
[24] Jussi Ryyn?nen, Kalle Kivek?s, Jarkko Jussila, et al. A Single-Chip Multimode Receiver for GSM900, DCS1800, PCS1900, and WCDMA. IEEE Journal of Solid-State Circuits, 2003, 38(4): 594-602
[25] Liang-Hung Lu, Hsieh-Hung Hsieh, Yu-Shun Wang. A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier. IEEE Microwave and Wireless Letters, 2005, 15(10): 685-687
[26]赵夕彬.射频宽带大功率放大器模块.半导体技术,2003,28(2):64-67
[27] G. A. Rincon-Mora. Voltage References—From Diodes to High-Precision High Order Bandgap Circuits. USA: IEEE Press, John Wiley & Sons, Inc., 2002: 50-98
[28] Jiwei Chen, Bingxue Shi. 1 V CMOS current reference with 50 ppm/°C temperature coefficient. Electronics Letters, 2003, 39(2): 209-210
[29] Behzad Razavi.射频微电子(余志平,周润德等).北京:清华大学出版社,2003,232-233
[30] Hong Yang, J.S.Yuan, Enjun Xiao.Effect of Gate Oxide Breakdown on RF Device and Circuit Performance.IEEE Trans. Electron Devices, 2002, 45: 1317-1221
[31] H. M. Greenhouse. Design of Planar Rectangular Microelectronic Inductors. IEEE Transactions on Parts, Hybrids, and Packaging, 1974, 10(2): 101-107
[32] C. P. YUE,S. S. WONG.Physical modeling of spiral inductors on silicon. IEEE Transactions on Parts, Hybrids, and Packaging, 2000, 47(3): 560-568
[33]许芹.GUI在参差调谐放大器频率特性实现中的应用.农业网络信息,2008,2:104-106
[34]史又华,陆生礼,时龙兴. RF集成电路工艺探讨.电子器件,2002,25(2):187-192
[35] V. Gupta, G. A. Rincón-Mora. A low dropout, CMOS regulator with high PSR over wideband frequencies. IEEE International Symposium on Circuits and Systems, 2005, 5: 4245-4248
[36] S. K. Hoon, J. Chen, F. Maloberti. An improved bandgap reference with high power supply rejection. IEEE International Symposium on Circuits and Systems, 1997, 5: 833-836
[37] H. Lin, D. Chang. A low-voltage process corner insensitive subthreshold CMOS voltage reference circuit. 2006 International Conference on IC Design and Technology, Italy: 227-230
[38] A. Brokaw. A Simple Three-terminal IC BandgapReference. IEEE Journal of Solid-State Circuits, 1974, 9: 388-393
[39] K. N. Leung, P. K. T. Mok. A sub-1V 15ppm/°C CMOS band-gap voltage reference without requiring low threshold voltage device. IEEE Journal of Solid-State Circuits, 2002, 36: 526-530
[40] P. Malcovati, F. Maloberti, C. Fiocchi, et al. Curvaturecompensated BiCMOS bandgap reference with 1-V supply voltage. IEEE Journal of Solid-State Circuits, 2001, 36: 1076-1081
[41] B. Razavi. Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2000: 377-400
[42] Y. Tsividis. Accurate analyzes of temperature effects in IC–VBE characteristics with application to bandgap reference sources. IEEE Journal of Solid-State Circuits, 1980, 15: 1076-1084
[43] B. Song, P. Gray. A Precision Curvature-Compensated CMOS Bandgap Reference. IEEE Journal of Solid-State Circuit, 1983, 18(6):634 -643
[44] G. A. Rincón-Mora, P. E. Allen. A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap voltage reference. IEEE Journal of Solid-State Circuit, 1998, 33(10): 1551-1554
[45] M. Meijer, P. Schmale, K. Zalinge. A New Curvature-Corrected Bandgap Reference. IEEE Journal of Solid-State Circuits, 1982, 17(6): 1139-1143
[46] K. N. Leung, P. Mok, C. Y. Leung. A 2-V 23-ptA 5.3-ppm/°C curvature-compensated CMOSbandgap voltage reference. IEEE Journal of Solid-State Circuit, 2003, 38(3): 561-564
[47] I. Lee, G. Kin, W. Kim. Exponential curvature-compensated BiCMOS bandgap references. IEEE Journal of Solid-State Circuit, 1994, 29(11): 1396-1403
[48] W. C. Dillard, R. C. Jaeger. The temperature dependence of the amplification factor of bipolar-junction transistors. IEEE Transactions on Electron Devices, 1987, 34: 139-142
[49] K. M. Tham and K. Nagaraj. A low supply voltage high PSRR voltage reference in CMOS process. IEEE Journal of Solid-State Circuit, 1995, 30(5): 586-590
[50] P. R. Gray, P. J. Hurst, S. H. Lewis, et al. Analysis and Design of Analog Integrated Circuits (4th ed). New York:Wiley, 2001: 625-685
[51] Zhou Hao, Zhang Bo, Li Zhang-ji, et al. A new CMOS current reference with high order temperature compesation. 2006 International Conference on Communications, Circuits and Systems, vol.4: 2105-2108
[52] Y. Liu, G. Liu, B. He, et al. A novel CMOS current reference with low temperature and supply dependence. 2006 International Conference on Communications, Circuits and Systems, vol.4: 2201-2204
[53] P. E. Allen, D. R. Holberg. CMOS analog circuit design (Second Edition). UK: Oxford University Press, 2002: 143-349
[54] M. Steyaert, W. Sansen. Power supply rejection ratio in operational transconductance amplifiers. IEEE Transactions on Circuit and systems, 1990, 37(9): 1077-1084
[2]王志华,吴恩.CMOS射频集成电路的现状与进展.电子学报,2001,29(2):233-238
[3]黄广宇,胡勇,杨旭,等.基于CMOS的RFIC的发展现状.微电子学,2002,32(4):283-286
[4]张国燕,黄如,张兴,等.CMOS射频集成电路的研究进展.微电子学,2004,34(4):377-382.
[5] Thomas H. Lee. CMOS射频集成电路设计(余志平,周润德等).北京:电子工业出版社,2004,393-415,226-229
[6]池保勇.CMOS射频集成电路分析与设计.北京:清华大学出版社,2006,285-287
[7] Milton Feng. Device Technologies for RF Front-End Circuits in Next-Generation Wireless Communications. Proceedings of the IEEE, 2004, 92(2): 354-372
[8] Massimo Brandolini, Paolo Rossi, Danilo Manstretta, et al. Toward Multistandard Mobile Terminals--Fully Integrated Receivers Requirements and Architectures. IEEE Transactions on Microwave Theory and Techniques, 2005, 53(3): 1026-1038
[9] Frederick H.RAAB, Idealized Operation of the Class E Tuned Power Amplifier. IEEE Transactions on Circuits and Systems, December 1977, vol. CAS-24, NO.12: 725-735
[10] Chengzhou Wang, Mani Vaidyanathan, Lawrence E. Larson.A Capacitance Compensation Technique for Improved Linearity in CMOS Class-AB Power Amplifiers. IEEE Solid-State Circuits, 2004, 39(11): 1927-1937
[11] Christina F. Jou, Pang-Ruei Huang, Kuo-Hua Cheng.Design of a 0.25μm CMOS 5.35GHz Transcerver Front-end.IEEE International Conference on Electronics Circuits and Systems, 2003: 1090-1093
[12] R. S. Narayanaswam.RF CMOS Class C Power Amplifiers for Wireless Communications: [Dissertation]. California: University of California, Berkeley, 2001, 142-144
[13] Saikat Sarkar, Padmanava Sen, Arvind Raghavan, et al. Development of 2.4GHz RF Transceiver Front-end Chipset in 0.25μm CMOS.Proceedings of the 16th International Conference on VLSI Design, 2003: 1-6
[14] Yongwang Ding, Ramesh Harjani. A CMOS High Efficiency +22 dBm Linear Power Amplifier. IEEE Custom Integrated Circuits Conference, 2004: 557-560
[15] N. Srirattana, P. Sen, H. M. Park,et al. Linear RF CMOS Power Amplifier with ImprovedEfficiency and Linearity in Wide Power Levels. IEEE Radio Frequency Integrated Circuits Symposium, 2005: 251-254
[16] Jaemin Jang, Changkun Park, Haksun Kim, et al. A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE. IEEE Microwave and Wireless Components Letters, 2007, NO. 5, MAY 2007,17: 385-387
[17] Bon-Hyun Ku, Sang-Hyun Baek, Songcheol Hong. A X-Band CMOS Power Amplifier with On-Chip Transmission Line Transformers. IEEE Custom Integrated Circuits Conference, 2008: 523-526
[18] David Ngo, Chris Dragon, Julio Costa, et al.RF Silicon MOS Integrated Power Amplifier for Analog Cellular Applications. IEEE MTT-S Digest,1996 WE2A-7: 559-562
[19] David Su, William McFarland.A 2.5-V, 1-W Monolithic CMOS RF Power Amplifier. IEEE Custom Integrated Circuits Conference, 1997: 189-192
[20]郭德彬,周峰,唐璞山.一种900MHz 20mW CMOS功率放大器的设计.微电子学,2002,32(1):62-65
[21]宗国翼,朱恩,李智群.可用于无线局域网802.11a标准的5GHz CMOS功率放大器设计.电子器件,2005,28(1):161-163
[22]李亮,李文渊,王志功.2.4GHz CMOS功率放大器设计.电子器件,2006,29(2):349-350
[23]杨柯,王志功,李志群.0.18μm CMOS工艺5GHz WLAN功率放大器设计.电子工程师.2006,32(3):1-3
[24] Jussi Ryyn?nen, Kalle Kivek?s, Jarkko Jussila, et al. A Single-Chip Multimode Receiver for GSM900, DCS1800, PCS1900, and WCDMA. IEEE Journal of Solid-State Circuits, 2003, 38(4): 594-602
[25] Liang-Hung Lu, Hsieh-Hung Hsieh, Yu-Shun Wang. A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier. IEEE Microwave and Wireless Letters, 2005, 15(10): 685-687
[26]赵夕彬.射频宽带大功率放大器模块.半导体技术,2003,28(2):64-67
[27] G. A. Rincon-Mora. Voltage References—From Diodes to High-Precision High Order Bandgap Circuits. USA: IEEE Press, John Wiley & Sons, Inc., 2002: 50-98
[28] Jiwei Chen, Bingxue Shi. 1 V CMOS current reference with 50 ppm/°C temperature coefficient. Electronics Letters, 2003, 39(2): 209-210
[29] Behzad Razavi.射频微电子(余志平,周润德等).北京:清华大学出版社,2003,232-233
[30] Hong Yang, J.S.Yuan, Enjun Xiao.Effect of Gate Oxide Breakdown on RF Device and Circuit Performance.IEEE Trans. Electron Devices, 2002, 45: 1317-1221
[31] H. M. Greenhouse. Design of Planar Rectangular Microelectronic Inductors. IEEE Transactions on Parts, Hybrids, and Packaging, 1974, 10(2): 101-107
[32] C. P. YUE,S. S. WONG.Physical modeling of spiral inductors on silicon. IEEE Transactions on Parts, Hybrids, and Packaging, 2000, 47(3): 560-568
[33]许芹.GUI在参差调谐放大器频率特性实现中的应用.农业网络信息,2008,2:104-106
[34]史又华,陆生礼,时龙兴. RF集成电路工艺探讨.电子器件,2002,25(2):187-192
[35] V. Gupta, G. A. Rincón-Mora. A low dropout, CMOS regulator with high PSR over wideband frequencies. IEEE International Symposium on Circuits and Systems, 2005, 5: 4245-4248
[36] S. K. Hoon, J. Chen, F. Maloberti. An improved bandgap reference with high power supply rejection. IEEE International Symposium on Circuits and Systems, 1997, 5: 833-836
[37] H. Lin, D. Chang. A low-voltage process corner insensitive subthreshold CMOS voltage reference circuit. 2006 International Conference on IC Design and Technology, Italy: 227-230
[38] A. Brokaw. A Simple Three-terminal IC BandgapReference. IEEE Journal of Solid-State Circuits, 1974, 9: 388-393
[39] K. N. Leung, P. K. T. Mok. A sub-1V 15ppm/°C CMOS band-gap voltage reference without requiring low threshold voltage device. IEEE Journal of Solid-State Circuits, 2002, 36: 526-530
[40] P. Malcovati, F. Maloberti, C. Fiocchi, et al. Curvaturecompensated BiCMOS bandgap reference with 1-V supply voltage. IEEE Journal of Solid-State Circuits, 2001, 36: 1076-1081
[41] B. Razavi. Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2000: 377-400
[42] Y. Tsividis. Accurate analyzes of temperature effects in IC–VBE characteristics with application to bandgap reference sources. IEEE Journal of Solid-State Circuits, 1980, 15: 1076-1084
[43] B. Song, P. Gray. A Precision Curvature-Compensated CMOS Bandgap Reference. IEEE Journal of Solid-State Circuit, 1983, 18(6):634 -643
[44] G. A. Rincón-Mora, P. E. Allen. A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap voltage reference. IEEE Journal of Solid-State Circuit, 1998, 33(10): 1551-1554
[45] M. Meijer, P. Schmale, K. Zalinge. A New Curvature-Corrected Bandgap Reference. IEEE Journal of Solid-State Circuits, 1982, 17(6): 1139-1143
[46] K. N. Leung, P. Mok, C. Y. Leung. A 2-V 23-ptA 5.3-ppm/°C curvature-compensated CMOSbandgap voltage reference. IEEE Journal of Solid-State Circuit, 2003, 38(3): 561-564
[47] I. Lee, G. Kin, W. Kim. Exponential curvature-compensated BiCMOS bandgap references. IEEE Journal of Solid-State Circuit, 1994, 29(11): 1396-1403
[48] W. C. Dillard, R. C. Jaeger. The temperature dependence of the amplification factor of bipolar-junction transistors. IEEE Transactions on Electron Devices, 1987, 34: 139-142
[49] K. M. Tham and K. Nagaraj. A low supply voltage high PSRR voltage reference in CMOS process. IEEE Journal of Solid-State Circuit, 1995, 30(5): 586-590
[50] P. R. Gray, P. J. Hurst, S. H. Lewis, et al. Analysis and Design of Analog Integrated Circuits (4th ed). New York:Wiley, 2001: 625-685
[51] Zhou Hao, Zhang Bo, Li Zhang-ji, et al. A new CMOS current reference with high order temperature compesation. 2006 International Conference on Communications, Circuits and Systems, vol.4: 2105-2108
[52] Y. Liu, G. Liu, B. He, et al. A novel CMOS current reference with low temperature and supply dependence. 2006 International Conference on Communications, Circuits and Systems, vol.4: 2201-2204
[53] P. E. Allen, D. R. Holberg. CMOS analog circuit design (Second Edition). UK: Oxford University Press, 2002: 143-349
[54] M. Steyaert, W. Sansen. Power supply rejection ratio in operational transconductance amplifiers. IEEE Transactions on Circuit and systems, 1990, 37(9): 1077-1084