AVS视频解码器可变长解码和反量化反变换模块硬件设计与实现
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摘要
先进音视频编码标准(AVS)是我国自主研发制定的关于数字电视、IPTV等音视频系统的基础性数字音视频编解码标准。AVS标准第2部分(AVS-P2)是高效的第二代视频编码技术,其实现方案简洁,并拥有与H.264近似的压缩性能。AVS标准的编码效率得到了极大的提高,其运算复杂度也大大增加,另外实际应用环境中对实时运算的限制,这都对视频解码器的硬件的实现提出了很高的要求和巨大的挑战。
本文深入研究了AVS标准,详细分析了可变长解码算法、逆扫描、反量化和反变换算法,提出了适用于AVS视频解码标准的可变长解码模块、反量化模块和反变换模块的硬件架构。可变长解码模块通过桶形移位寄存器、优化压缩查找表索引等方法以及并行和复用技术的应用,达到设计的高速、低开销。在反量化模块的设计中,反量化运算与之前的逆扫描模块中两个乒乓RAM共同节省了处理时间。反变换模块通过模块复用,实现了一种新颖的流水线结构的一维整数反变换核的运算与设计,在大大节约硬件资源的同时,也明显提高了速度。
设计采用自顶向下的设计方法,运用Verilog硬件描述语言完成了可变长解码模块、反量化模块和反变换模块的RTL级建模,以参考模型RM52j为基础建立了正确的C_modeL。使用SystemVerilog语言结合高级验证方法学(AVM)搭建验证平台对设计进行了功能验证,采用事务级的验证策略,使用了随机约束和功能覆盖率等验证技术新特性。使用该验证平台能够极大的提高验证效率,并且其组件具有可重用性。应用Mentor公司的仿真工具ModelSim对三个模块进行功能仿真。采用中芯国际(SMIC)的0.18μm工艺库,用Synopsys的Design Compiler进行逻辑综合,并采用了合适的综合策略和优化手段。
综合和验证结果表明,上述三个模块的设计均达到了本课题要求的目标。
Audio Video coding Standard(AVS), independently developed and owned by China, is a fundamental standard in digital TV, IPTV and other audio/video based systems. AVS Part2, the video part, defines the highly efficient second generation video coding technology. Its implementation is simple and easy. Moreover, it has coding performance close to H.264. Although the coding efficiency of the AVS is better than previous standards, for some real-time applications, the complicated computational characteristics lead great challenges for today's VLSI implementation.
Based on analysis of Advanced Coding of Audio and Video Standard deeply, especially variable length decoding, inverse scan, inverse quantization and inverse transformation, this paper introduces the design of variable length decoder, and inverse quantization and inverse transformation. Variable length decoder uses the Barrel-Shifters and optimizes the look-up table index to meet a higher speed and a lower overhead and also reuses some modules in order to reduce the cost of hardware. Inverse quantization and two ping-pong RAM in inverse scanning module together save the processing time. A novel pipeline structure of the 1-D inverse transformation implementing way introduced in this paper is extremely low-cost and high-speed.
In whole design, the Top-down design method is used. The design is described in Verilog HDL and a software reference model is made based on RM52j. According to Advanced Verification Methodology, testbench is constructed to functionally verify the design by using SystemVerilog, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability. Function simulation has been completed on each module by using ModelSim. Based on appropriate strategy of synthesis and method of optimization, three modules are synthesize by using SMIC 0.18μm CMOS technology library.
The verification and simulation results all indicate that the design of the three modules has achieved requirement.
本文深入研究了AVS标准,详细分析了可变长解码算法、逆扫描、反量化和反变换算法,提出了适用于AVS视频解码标准的可变长解码模块、反量化模块和反变换模块的硬件架构。可变长解码模块通过桶形移位寄存器、优化压缩查找表索引等方法以及并行和复用技术的应用,达到设计的高速、低开销。在反量化模块的设计中,反量化运算与之前的逆扫描模块中两个乒乓RAM共同节省了处理时间。反变换模块通过模块复用,实现了一种新颖的流水线结构的一维整数反变换核的运算与设计,在大大节约硬件资源的同时,也明显提高了速度。
设计采用自顶向下的设计方法,运用Verilog硬件描述语言完成了可变长解码模块、反量化模块和反变换模块的RTL级建模,以参考模型RM52j为基础建立了正确的C_modeL。使用SystemVerilog语言结合高级验证方法学(AVM)搭建验证平台对设计进行了功能验证,采用事务级的验证策略,使用了随机约束和功能覆盖率等验证技术新特性。使用该验证平台能够极大的提高验证效率,并且其组件具有可重用性。应用Mentor公司的仿真工具ModelSim对三个模块进行功能仿真。采用中芯国际(SMIC)的0.18μm工艺库,用Synopsys的Design Compiler进行逻辑综合,并采用了合适的综合策略和优化手段。
综合和验证结果表明,上述三个模块的设计均达到了本课题要求的目标。
Audio Video coding Standard(AVS), independently developed and owned by China, is a fundamental standard in digital TV, IPTV and other audio/video based systems. AVS Part2, the video part, defines the highly efficient second generation video coding technology. Its implementation is simple and easy. Moreover, it has coding performance close to H.264. Although the coding efficiency of the AVS is better than previous standards, for some real-time applications, the complicated computational characteristics lead great challenges for today's VLSI implementation.
Based on analysis of Advanced Coding of Audio and Video Standard deeply, especially variable length decoding, inverse scan, inverse quantization and inverse transformation, this paper introduces the design of variable length decoder, and inverse quantization and inverse transformation. Variable length decoder uses the Barrel-Shifters and optimizes the look-up table index to meet a higher speed and a lower overhead and also reuses some modules in order to reduce the cost of hardware. Inverse quantization and two ping-pong RAM in inverse scanning module together save the processing time. A novel pipeline structure of the 1-D inverse transformation implementing way introduced in this paper is extremely low-cost and high-speed.
In whole design, the Top-down design method is used. The design is described in Verilog HDL and a software reference model is made based on RM52j. According to Advanced Verification Methodology, testbench is constructed to functionally verify the design by using SystemVerilog, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability. Function simulation has been completed on each module by using ModelSim. Based on appropriate strategy of synthesis and method of optimization, three modules are synthesize by using SMIC 0.18μm CMOS technology library.
The verification and simulation results all indicate that the design of the three modules has achieved requirement.
引文
[1]ITU-T Recommendation H.261.Line Transmission of Non-telephone Signals-Video Codec for Audiovisual Services at px64kbits.1993.
[2]ISO/IEC JTC1/SC29, Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at UP to about 1.5Mbit/s Part2:Video.ISO/IEC11172-2(MPEG-1).1993.
[3]ITU-T Recommendation H.262-150/IEC 13818-2. Information Technology Generic Coding of Moving Pictures and Associated Audio Inofrmation: Video.1995.
[4]ITU-T Recommendation H.263.Video Coding for Low Bitrate Communication. 1995.
[5]ISO-IEC 14496-2. Information Technology-Coding of Audio-Visual Objects-Part2:Visual.Amendment 1(version2).1999.
[6]ISO-IEC JTC1 and ITU-T. Joint Final Committee Dratf of Joint Specification (ITU-T Rec.H.264 ISO/IEC 14496-10 AVC).JVT-D 157.2002.
[7]高文,王强,马思伟.AVS数字音视频编解码标准[J].中兴通讯技术,2006,12(3)：6-9.
[8]藤勇.中国网通：AVS IPTV产业化的实践与创新[J].中国数字电视,2007,11(39)：68-69.
[9]高文,王强,马思伟.AVS数字音视频编解码标准[J].中兴通讯技术,2006,12(3):6-9.
[10]Cong Peng, Chao Huang, Ronggang Wang et al. Architecture of AVS Hardware Decoding System[J]. Hong Kong:Proceedings of 2004 International Symposium on Intelligent Multimedia, Video and Speech Processing,2004:306-309.
[11]邓华阳.基于DSP的AVS编码器研究：[硕士学位论文],北方工业大学,2008.
[12]数字音视频编解码技术标准工作组.信息技术先进音视频编码(第二部分：视频)2003.
[13]杨怀省.基于TMS320DM642的AVS视频解码器的实现与优化：[硕士学位论
文].青岛：中国海洋大学,2008.
[14]M.Pinson,S.Wolf.Comparing Subject Video Quality Testing Methodologies, Proceedings ofSPIE,2003.
[15]虞露等.AVS视频的技术特征.电视技术,2004年第7期(总第277期)
[16]赵阳生,黄晁,刘明业.应用于AVS视频解码器的VLD设计[J].微机发展,2005,9(15)：122-124.
[17]Liu Wei, Chen Yong-en, "VLD Design for AVS Video Decoder," Knowledge Discovery and Data Mining,2009. WKDD 2009. Second International Workshop on 23-25 Jan.2009 (s):648-651.
[18]GB／T 200090.2-2006,信息技术-先进音视频编码-第2部分：视频[S].
[19]数字音视频编解码技术标准工作组.信息技术先进音视频编码(第二部分：视频),2003.
[20]马骏,AVS视频关键技术的研究[D],硕士学位论文,南京：东南大学,2006.3.
[21]孙宁,叶兵,黄晁等.H.264及AVS高清视频解码中SDRAM控制器的设计与实现[J].微电子学与计算机,2007,24(1)：116-118.
[22]Wiegand T, Sullivan GJ, Bjφtegaard G, et al. Overview of the H.264/AVC video coding standard [J]. IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7):560-576.
[23]Nasser Kehtarnavaz, Mark Gamadia. Real-time image and video processing:from research to reality [M]. Dallas:M & C,2006.6-9.
[24]Youn-Long Steve Lin. Essential issues in SoC design[M]. New York:Springer, 2006.30-34.
[25]Yanmei Qu, Yun He.A Simple and Memory Efficient VLSI Architecture of CA-2D-VLC Decoder for AVS[M].Proc.PCS2006,in press.
[26]Wu Di, Gao Wen, Hu Mingzeng and Ji Zhenzhou, "An Exp-Golomb encoder and decoder architecture for JVT/AVS," Proc.5th International Conference on ASIC, Vol.2, pp.910-913, Oct 2003.
[27]张晨曦等,计算机体系结构[M],高等教育出版社,2003.
[28]DvaidE.Culler, " Parallel ComPuter Architectuer A Hardware/software APProach[m]",Morgan Kuafmann,1998.
[29]屈玉贵,梁晓雯,并行处理系统结构[M],中国科技大学出版社,1999.
[30]John L. Hennessy, David A. Pauerson. Computer Architecture:A Quantitative Approach(Fourth Edition)[M]. Amsterdam:Elsevier Science,2006.
[31]潘松,潘明.现代计算机组成原理[M].北京：科学出版社,2007：259-274.
[32]Weng F. Lee. VHDL coding and logic synthesis with Synopsys[M]. Amsterdam: Elsevier,2000:91-143.
[33]毛讯.高速视频解码器设计研究[D].浙江大学博士论文,2001.
[34]KIM C S, SONG S W, KIM M Y, et al.200 mega pixel rate ID-CT processor for HDTV applications [C]//IEEE International Symposiumon Circuits and Systems,[S.l.]:IEEE Press,1993:2003-2006.
[35]KIM K, KOH J. An area efficient dct architecture for MPEG-2 video encoder[J]. IEEE Trans, on Consumer Electronics,1999,45(1):62-67.
[36]HENNING R, CHAKRABARTI C. A quality/energy tradeoff approach for IDCT computation in MPEG-2 video decoding [C]//Proc.IEEE Signal Processing Systems, Lafayette:[s.n.],2000:90-99.
[37]牛凤举,刘元成,朱明程.基于IP服用的数字IC设计技术[M].北京：电子工业出版社,2003：102-165.
[38]Rangara Jan Purisai.如何选择正确的验证方法[J].电子设计应用,2005,5：82-86.
[39]IEEE Std 1800-2005 IEEE Standard for SystemVerilog-Unified Hardware Design, Specification and Verification Language[S]. New York:The Institure of Electrical and Electronics Engineers, Inc, November 2005.
[40]夏雨闻.SystemVerilog简介[J].中国集成电路,2006,15(2)：40-50.
[41]M.Glasser, A.Rose. Advanced Verification Methodology Cookbook[DB/OL]. http://www. Mentor.com,2008.
[42]杨宗凯、黄建、杜旭.数字专用集成电路的设计与验证[M].北京：电子工业出版社.2004：155-168.
[43]Mentor Graphics. ModelSim SE User's Manual(Software Version 6.4b) [DB/OL]. http://www.mentor.com,2008.
[44]Chris Spear. SystemVerilog for Verification A Guide to Learning the Testbench Language Features[M]. NewYork:Springer,2008.
[45]Janick Bergeron. Writing Testbenches using System Verilog[M]. New York:Sprin ger,2006.
[46]Jonathan Bromly, Michael Smith. A User's Experience with SystemVerilog [DB /OL]. http://solvnet. synopsys.com,2004.
[47]Himanshu Bhatnagar著,张文俊译.高级ASIC芯片综合-使用Synopsys Design Compiler Physical Compiler和PrimeTime(第二版).北京：清华大学出版社,2007.
[48]IEEE Std 1364-2001 IEEE Standard Verilog Hardware Description Language[S]. New York:The Institure of Electrical and Electronics Engineers, September 2001.
[49]IEEE Standard for Verilog Register Transfer Level Synthesis [S]. New York:The Institure of Electrical and Electronics Engineers, December 2002.
[50]姜伟,AVS解码器帧内预测和环路滤波器硬件设计与实现,硕士学位论文,济南：山东大学,2009.4.
[51]Chang L. Lee, "Parallel Implementation of Motion-Compensation for HDTV Video Decoder", vol.44, no.2, May 1998.
[2]ISO/IEC JTC1/SC29, Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at UP to about 1.5Mbit/s Part2:Video.ISO/IEC11172-2(MPEG-1).1993.
[3]ITU-T Recommendation H.262-150/IEC 13818-2. Information Technology Generic Coding of Moving Pictures and Associated Audio Inofrmation: Video.1995.
[4]ITU-T Recommendation H.263.Video Coding for Low Bitrate Communication. 1995.
[5]ISO-IEC 14496-2. Information Technology-Coding of Audio-Visual Objects-Part2:Visual.Amendment 1(version2).1999.
[6]ISO-IEC JTC1 and ITU-T. Joint Final Committee Dratf of Joint Specification (ITU-T Rec.H.264 ISO/IEC 14496-10 AVC).JVT-D 157.2002.
[7]高文,王强,马思伟.AVS数字音视频编解码标准[J].中兴通讯技术,2006,12(3)：6-9.
[8]藤勇.中国网通：AVS IPTV产业化的实践与创新[J].中国数字电视,2007,11(39)：68-69.
[9]高文,王强,马思伟.AVS数字音视频编解码标准[J].中兴通讯技术,2006,12(3):6-9.
[10]Cong Peng, Chao Huang, Ronggang Wang et al. Architecture of AVS Hardware Decoding System[J]. Hong Kong:Proceedings of 2004 International Symposium on Intelligent Multimedia, Video and Speech Processing,2004:306-309.
[11]邓华阳.基于DSP的AVS编码器研究：[硕士学位论文],北方工业大学,2008.
[12]数字音视频编解码技术标准工作组.信息技术先进音视频编码(第二部分：视频)2003.
[13]杨怀省.基于TMS320DM642的AVS视频解码器的实现与优化：[硕士学位论
文].青岛：中国海洋大学,2008.
[14]M.Pinson,S.Wolf.Comparing Subject Video Quality Testing Methodologies, Proceedings ofSPIE,2003.
[15]虞露等.AVS视频的技术特征.电视技术,2004年第7期(总第277期)
[16]赵阳生,黄晁,刘明业.应用于AVS视频解码器的VLD设计[J].微机发展,2005,9(15)：122-124.
[17]Liu Wei, Chen Yong-en, "VLD Design for AVS Video Decoder," Knowledge Discovery and Data Mining,2009. WKDD 2009. Second International Workshop on 23-25 Jan.2009 (s):648-651.
[18]GB／T 200090.2-2006,信息技术-先进音视频编码-第2部分：视频[S].
[19]数字音视频编解码技术标准工作组.信息技术先进音视频编码(第二部分：视频),2003.
[20]马骏,AVS视频关键技术的研究[D],硕士学位论文,南京：东南大学,2006.3.
[21]孙宁,叶兵,黄晁等.H.264及AVS高清视频解码中SDRAM控制器的设计与实现[J].微电子学与计算机,2007,24(1)：116-118.
[22]Wiegand T, Sullivan GJ, Bjφtegaard G, et al. Overview of the H.264/AVC video coding standard [J]. IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7):560-576.
[23]Nasser Kehtarnavaz, Mark Gamadia. Real-time image and video processing:from research to reality [M]. Dallas:M & C,2006.6-9.
[24]Youn-Long Steve Lin. Essential issues in SoC design[M]. New York:Springer, 2006.30-34.
[25]Yanmei Qu, Yun He.A Simple and Memory Efficient VLSI Architecture of CA-2D-VLC Decoder for AVS[M].Proc.PCS2006,in press.
[26]Wu Di, Gao Wen, Hu Mingzeng and Ji Zhenzhou, "An Exp-Golomb encoder and decoder architecture for JVT/AVS," Proc.5th International Conference on ASIC, Vol.2, pp.910-913, Oct 2003.
[27]张晨曦等,计算机体系结构[M],高等教育出版社,2003.
[28]DvaidE.Culler, " Parallel ComPuter Architectuer A Hardware/software APProach[m]",Morgan Kuafmann,1998.
[29]屈玉贵,梁晓雯,并行处理系统结构[M],中国科技大学出版社,1999.
[30]John L. Hennessy, David A. Pauerson. Computer Architecture:A Quantitative Approach(Fourth Edition)[M]. Amsterdam:Elsevier Science,2006.
[31]潘松,潘明.现代计算机组成原理[M].北京：科学出版社,2007：259-274.
[32]Weng F. Lee. VHDL coding and logic synthesis with Synopsys[M]. Amsterdam: Elsevier,2000:91-143.
[33]毛讯.高速视频解码器设计研究[D].浙江大学博士论文,2001.
[34]KIM C S, SONG S W, KIM M Y, et al.200 mega pixel rate ID-CT processor for HDTV applications [C]//IEEE International Symposiumon Circuits and Systems,[S.l.]:IEEE Press,1993:2003-2006.
[35]KIM K, KOH J. An area efficient dct architecture for MPEG-2 video encoder[J]. IEEE Trans, on Consumer Electronics,1999,45(1):62-67.
[36]HENNING R, CHAKRABARTI C. A quality/energy tradeoff approach for IDCT computation in MPEG-2 video decoding [C]//Proc.IEEE Signal Processing Systems, Lafayette:[s.n.],2000:90-99.
[37]牛凤举,刘元成,朱明程.基于IP服用的数字IC设计技术[M].北京：电子工业出版社,2003：102-165.
[38]Rangara Jan Purisai.如何选择正确的验证方法[J].电子设计应用,2005,5：82-86.
[39]IEEE Std 1800-2005 IEEE Standard for SystemVerilog-Unified Hardware Design, Specification and Verification Language[S]. New York:The Institure of Electrical and Electronics Engineers, Inc, November 2005.
[40]夏雨闻.SystemVerilog简介[J].中国集成电路,2006,15(2)：40-50.
[41]M.Glasser, A.Rose. Advanced Verification Methodology Cookbook[DB/OL]. http://www. Mentor.com,2008.
[42]杨宗凯、黄建、杜旭.数字专用集成电路的设计与验证[M].北京：电子工业出版社.2004：155-168.
[43]Mentor Graphics. ModelSim SE User's Manual(Software Version 6.4b) [DB/OL]. http://www.mentor.com,2008.
[44]Chris Spear. SystemVerilog for Verification A Guide to Learning the Testbench Language Features[M]. NewYork:Springer,2008.
[45]Janick Bergeron. Writing Testbenches using System Verilog[M]. New York:Sprin ger,2006.
[46]Jonathan Bromly, Michael Smith. A User's Experience with SystemVerilog [DB /OL]. http://solvnet. synopsys.com,2004.
[47]Himanshu Bhatnagar著,张文俊译.高级ASIC芯片综合-使用Synopsys Design Compiler Physical Compiler和PrimeTime(第二版).北京：清华大学出版社,2007.
[48]IEEE Std 1364-2001 IEEE Standard Verilog Hardware Description Language[S]. New York:The Institure of Electrical and Electronics Engineers, September 2001.
[49]IEEE Standard for Verilog Register Transfer Level Synthesis [S]. New York:The Institure of Electrical and Electronics Engineers, December 2002.
[50]姜伟,AVS解码器帧内预测和环路滤波器硬件设计与实现,硕士学位论文,济南：山东大学,2009.4.
[51]Chang L. Lee, "Parallel Implementation of Motion-Compensation for HDTV Video Decoder", vol.44, no.2, May 1998.