YAK SOC芯片的物理设计研究
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摘要
随着集成电路特征尺寸进入深亚微米阶段,超大规模集成电路(VLSI)中各种互联效应的影响已经变得越来重要。互联线延时(Interconnect delay)、串扰效应(Crosstalk Effect)、电压降效应(IR-Drop)、电子迁移效应(EM Effect)和天线效应(Process Antenna Effect)等问题已经成为了物理设计的瓶颈,制约着集成电路的发展。
本文针对上述5种互联效应的起因、危害和解决方法进行了深入的研究,并在互联线延时和串扰方面提出了自己的修复和预防措施。这些修复和预防措施成功地应用到YAK SOC芯片的物理设计中,并保证了芯片时序驱动下的持续收敛和完备的可制造性。
本文提出了深亚微米条件下YAK SOC芯片的逻辑综合、物理实现和验证的流程。对标准单元布局、IO布局、时钟树综合、布线等重要的步骤给出了详细的分析,最终成功完成了YAK SOC芯片的物理设计。设计得到的GDSII版图文件,经过验证,满足时序要求和达到预定的电路功能,并通过了DRC和LVS检查,可以交付流片。
YAK SOC芯片为本实验室自行开发的SOC芯片,拥有多项自主IP产权,主要应用于蓝牙和RFID的无线通信。采用HJTC的180nm工艺,工作频率为50MHz,芯片面积为3200μm?3300μm。
本文的研究结果对于深亚微米工艺下的大规模物理设计与优化,具有一定的指导意义和应用价值。
When the development of VLSI technology step into deep-submicron level (DSM), the impact of interconnect effect in VLSI become more important than before. Interconnect delay, Crosstalk Effect, IR-Drop, EM Effect, Process Antenna Effect have become the bottle-neck of the physical design and brings new challenge.
Five interconnect effect mentioned above are analyzed detailed in this paper. Method to prevent and fix interconnect effect is used in YAK SOC chip’s design, ensuring the continuous convergence and manufacturability under timing driven.
Logic synthesis, physical design and verification of YAK SOC are presented in this paper. Some important process such as floorplanning, IO placement, clock synthesis, routing are analyzed. The physical design of YAK SOC is completed successful. The GDSII layout file could fulfill with the timing requirement and implement the anticipative function. Since DRC and LVS verification process have finished, this layout is able to tape out.
YAK SOC is a SOC chip designed by our lab. Its area is 3200μm?3300μm. It use HJTC’s 180nm technology and is operated at 50 MHz. The chip is used in Bluetooth or RFID.
The research result of this paper has some directive meaning and applicable value in physical design and optimization for VLSI under deep-submicron technology.
本文针对上述5种互联效应的起因、危害和解决方法进行了深入的研究,并在互联线延时和串扰方面提出了自己的修复和预防措施。这些修复和预防措施成功地应用到YAK SOC芯片的物理设计中,并保证了芯片时序驱动下的持续收敛和完备的可制造性。
本文提出了深亚微米条件下YAK SOC芯片的逻辑综合、物理实现和验证的流程。对标准单元布局、IO布局、时钟树综合、布线等重要的步骤给出了详细的分析,最终成功完成了YAK SOC芯片的物理设计。设计得到的GDSII版图文件,经过验证,满足时序要求和达到预定的电路功能,并通过了DRC和LVS检查,可以交付流片。
YAK SOC芯片为本实验室自行开发的SOC芯片,拥有多项自主IP产权,主要应用于蓝牙和RFID的无线通信。采用HJTC的180nm工艺,工作频率为50MHz,芯片面积为3200μm?3300μm。
本文的研究结果对于深亚微米工艺下的大规模物理设计与优化,具有一定的指导意义和应用价值。
When the development of VLSI technology step into deep-submicron level (DSM), the impact of interconnect effect in VLSI become more important than before. Interconnect delay, Crosstalk Effect, IR-Drop, EM Effect, Process Antenna Effect have become the bottle-neck of the physical design and brings new challenge.
Five interconnect effect mentioned above are analyzed detailed in this paper. Method to prevent and fix interconnect effect is used in YAK SOC chip’s design, ensuring the continuous convergence and manufacturability under timing driven.
Logic synthesis, physical design and verification of YAK SOC are presented in this paper. Some important process such as floorplanning, IO placement, clock synthesis, routing are analyzed. The physical design of YAK SOC is completed successful. The GDSII layout file could fulfill with the timing requirement and implement the anticipative function. Since DRC and LVS verification process have finished, this layout is able to tape out.
YAK SOC is a SOC chip designed by our lab. Its area is 3200μm?3300μm. It use HJTC’s 180nm technology and is operated at 50 MHz. The chip is used in Bluetooth or RFID.
The research result of this paper has some directive meaning and applicable value in physical design and optimization for VLSI under deep-submicron technology.
引文
1 Flaherty Nick. Happy 40th Birthday Moore's law!. Electron World. 2005, 111(1831):12~13
2 The International Technology Roadmap for Semiconductors (ITRS), 2007 Edition. Semiconductor Industry Association. 2007. http://www.itrs.net/Links/2007ITRS/
3邢建平,曾繁泰.VHDL程序设计教程.清华大学出版社.2005:11
4 Jiri Gaisler, Edvin Catovic, Marko Isom?ki, Kristoffer Glembo, Sandi Habinc. GRLIB IP Core User’s Manual Version 1.0.18, May 2008
5 SPARC International, Inc. The SPARC Architecture Manual Version 8. 1992
6 Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic.周润德等译.数字集成电路.电子工业出版社. 2004:10
7 David A. Hodges, Horace G. Jackson, Resve A. Saleh. Analysis and Design of Digital Integrated Circuit-In Deep Submicron Technology Third Edition. Publishing House of Electronics Industry. 2005.
8 Michael John, Sebastian Smith.虞惠华等译.专用集成电路.电子工业出版社.2005:1
9 Synopsy公司.Design Compiler User Guid. Synopsy公司.2004:6
10 B. Vinnakota, N. K. Jha. Synthesis of Sequential Circuits for Parallel Scan. Proc. European Conf. Design Automation, Brussels, Belgium, 1992, Piscataway, NJ, IEEE press, 1992: 366~370
11 C.Chen, M.Sarrafzadeh. Slack equalization algorithm: precise slack distribution for low level synthesis and optimization. International Workshop on Logic Synthesis, in Proc., Granlibakken Resort, Lake Tahoe, California, June 1999. Piscataway, NJ, IEEE press: 190~192
12 Cadence公司.SOC Encounter Continuous Convergence. CADENCE公司. 2004:6
13 Cadence公司.Encounter User Guid.Cadence公司.2005:12
14 Mentor公司. Calibre Verification User’s Manual.Mentor公司.2004:2
15 E. Elmore,“The Transient Response of Damped Liner Networks with Particular Regard to Wideband Amplifiers,”Journal of Applied Physics, pp. 55-63, January 1948.
16 Joon Seo Yim, Chpng Min Kyng. Reducing Cross-coupling Aamong Interconnect Wires in Deep-submicron Datapath Design.Dennard IEEE Journal of Solid-State Circuits.1999
17 A.Vittal,M.Marek-Sadavska.Crosstalk Reduction for VLSI.IEEE Trans .CAD
18 L. Ding, D. Blaauw and P. Mazumder. Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2003,22(5):627~634
19 K. Agarwal, D.Sylvester, D. Blaauw. Modeling and analysis of crosstalk noise in coupled RLC interconnects.Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 25, Issue 5, May 2006 Page(s):892– 901
20 K. Kobayashi, J.Yamaguchi, H.Onodera. Measurement results of on-chip IR drop Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 12-15 May 2002 Pages:521-524
21 en Dhaou, H. Tenhunen. Energy Efficient High Speed On-Chip Signaling in Deep Submicron CMOS Technology. Proceedings of the 2000 international workshop on System-level interconnect prediction, in Proc., San Diego, California. United States, April.2000. New York, NY, USA, ACM Press: 69~76
22 H. Fischer, A. Abel, M. Lepper, A. E. Zitzelsberger and A. von Glasow. Experimental data and statistical models for bimodal EM failures. in Proc. IEEE 38th Annu. Reliab. Phys. Symp., 2000, Piscataway, NJ, IEEE press, 2000:359~361
23 J. Lienig, G. Jerke. Electromigration-aware physical design of integrated circuitsVLSI Design, 18th International Conference on 3-7 Jan. 2005 Page(s):77– 82
24 Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong. A novel low-power physical design methodology for MTCMOS.Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):4 pp.
25 S. Sur-Kolay, P. Dasgupta, B.B.Bhattacharya, S.T.Zachariah. Physical design trends and layout-basedfault modeling.VLSI Design, 2004. Proceedings. 17th International Conference on 2004 Page(s):6– 8
26 D.Z.Pan, Lithography-aware physical design.ASIC, 2005. ASICON 2005. 6th International Conference On olume 1, 24-27 Oct. 2005 Page(s):1172– 1173
27 K. Wakabayashi and T. Okamoto. C-based SOC design flow and EDA tools: An ASIC and system vendor perspective. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2000,19(12):1507~1522
28 Hua Xiang, Xiaoping Tang and Wong M.D.F. Bus-Driven Floorplanning. Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, Piscataway, NJ, IEEE press, 2003. 1522~1530
29 P.Sniatala, R.Rudnicki, Automated design and layout generation for switched current circuits. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):4 pp.
30 Hua-An Zhao, Chen Liu, Y. Kajitani, K.Sakanushi, A compact code for representing floorplans. Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on Volume 1, 25-28 July 2004 Page(s):I - 433-6 vol.1
31 M.D.Moffitt, A.N.Ng, I.L.Markov, M.E.Pollack, Constraint-driven floorplan repair. Design Automation Conference, 2006 43rd ACM/IEEE24-28 July 2006 Page(s):1103– 1108
32 I.H.-R.Jiang, Yao-Wen Chang, Jing-Yang Jou, Chao Kai-Yuan.Simultaneous floor plan and buffer-block optimization. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions onVolume 23, Issue 5, May 2004 Page(s):694– 703
33 E.F.Y.Young, C.C.N.Chu, M.L.Ho,Placement constraints in floorplan design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 12,Issue 7, July 2004 Page(s):735– 745
34 Caldwell A, Kahng A.B. and Mantik S etc. Implications of Area-Array I/O for Row-Based Placement Methodology. Proceedings of the IEEE Symposium on IC/Package Design Integration, 1998. Piscataway, NJ, IEEE press, 1998: 93~98
35 Yasar G, Chiu C and Proctor R A etc. I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. Proceedings of the 2nd International Symposium on Quality Electronic Design, 2001. Piscataway, NJ, IEEE press, 2001: 71~75
36 Yasar G, Chiu C and Proctor R A etc. I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. Proceedings of the 2nd International Symposium on Quality Electronic Design, 2001. Piscataway, NJ, IEEE press, 2001: 71~75
37 I-Min Liu, Hung-Ming Chen and Tan-Li Chou etc. Integrated power supply planning and floorplanning. Proceedings of the 2001 conference on Asia South Pacific design automation, Yokohama, Japan, 2001. New York, NY, USA, ACM Press, 2001: 589~594
38 J.P.Fang, Y.-S.Tong, S.J.Chen, Simultaneous routing and buffering in SOC floorplan design. Computers and Digital Techniques, IEE Proceedings-Volume 151, Issue 1, 15 Jan. 2004 Page(s):17– 22
39 Zhaowei Teng, Peng Liu, Liya Lai,Physical design of dual-core system-on-chip. VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on 28-30 May 2005 Page(s):36– 39
40 MalyW , Ouyang C, Ghosh S, Maturi S. Detection of an Antenna Effect in VLSI Designs. IEEE.Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Boston, MA, USA ,1996. Piscataway, NJ,IEEE press, 1996:86~94
2 The International Technology Roadmap for Semiconductors (ITRS), 2007 Edition. Semiconductor Industry Association. 2007. http://www.itrs.net/Links/2007ITRS/
3邢建平,曾繁泰.VHDL程序设计教程.清华大学出版社.2005:11
4 Jiri Gaisler, Edvin Catovic, Marko Isom?ki, Kristoffer Glembo, Sandi Habinc. GRLIB IP Core User’s Manual Version 1.0.18, May 2008
5 SPARC International, Inc. The SPARC Architecture Manual Version 8. 1992
6 Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic.周润德等译.数字集成电路.电子工业出版社. 2004:10
7 David A. Hodges, Horace G. Jackson, Resve A. Saleh. Analysis and Design of Digital Integrated Circuit-In Deep Submicron Technology Third Edition. Publishing House of Electronics Industry. 2005.
8 Michael John, Sebastian Smith.虞惠华等译.专用集成电路.电子工业出版社.2005:1
9 Synopsy公司.Design Compiler User Guid. Synopsy公司.2004:6
10 B. Vinnakota, N. K. Jha. Synthesis of Sequential Circuits for Parallel Scan. Proc. European Conf. Design Automation, Brussels, Belgium, 1992, Piscataway, NJ, IEEE press, 1992: 366~370
11 C.Chen, M.Sarrafzadeh. Slack equalization algorithm: precise slack distribution for low level synthesis and optimization. International Workshop on Logic Synthesis, in Proc., Granlibakken Resort, Lake Tahoe, California, June 1999. Piscataway, NJ, IEEE press: 190~192
12 Cadence公司.SOC Encounter Continuous Convergence. CADENCE公司. 2004:6
13 Cadence公司.Encounter User Guid.Cadence公司.2005:12
14 Mentor公司. Calibre Verification User’s Manual.Mentor公司.2004:2
15 E. Elmore,“The Transient Response of Damped Liner Networks with Particular Regard to Wideband Amplifiers,”Journal of Applied Physics, pp. 55-63, January 1948.
16 Joon Seo Yim, Chpng Min Kyng. Reducing Cross-coupling Aamong Interconnect Wires in Deep-submicron Datapath Design.Dennard IEEE Journal of Solid-State Circuits.1999
17 A.Vittal,M.Marek-Sadavska.Crosstalk Reduction for VLSI.IEEE Trans .CAD
18 L. Ding, D. Blaauw and P. Mazumder. Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2003,22(5):627~634
19 K. Agarwal, D.Sylvester, D. Blaauw. Modeling and analysis of crosstalk noise in coupled RLC interconnects.Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 25, Issue 5, May 2006 Page(s):892– 901
20 K. Kobayashi, J.Yamaguchi, H.Onodera. Measurement results of on-chip IR drop Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 12-15 May 2002 Pages:521-524
21 en Dhaou, H. Tenhunen. Energy Efficient High Speed On-Chip Signaling in Deep Submicron CMOS Technology. Proceedings of the 2000 international workshop on System-level interconnect prediction, in Proc., San Diego, California. United States, April.2000. New York, NY, USA, ACM Press: 69~76
22 H. Fischer, A. Abel, M. Lepper, A. E. Zitzelsberger and A. von Glasow. Experimental data and statistical models for bimodal EM failures. in Proc. IEEE 38th Annu. Reliab. Phys. Symp., 2000, Piscataway, NJ, IEEE press, 2000:359~361
23 J. Lienig, G. Jerke. Electromigration-aware physical design of integrated circuitsVLSI Design, 18th International Conference on 3-7 Jan. 2005 Page(s):77– 82
24 Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong. A novel low-power physical design methodology for MTCMOS.Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):4 pp.
25 S. Sur-Kolay, P. Dasgupta, B.B.Bhattacharya, S.T.Zachariah. Physical design trends and layout-basedfault modeling.VLSI Design, 2004. Proceedings. 17th International Conference on 2004 Page(s):6– 8
26 D.Z.Pan, Lithography-aware physical design.ASIC, 2005. ASICON 2005. 6th International Conference On olume 1, 24-27 Oct. 2005 Page(s):1172– 1173
27 K. Wakabayashi and T. Okamoto. C-based SOC design flow and EDA tools: An ASIC and system vendor perspective. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2000,19(12):1507~1522
28 Hua Xiang, Xiaoping Tang and Wong M.D.F. Bus-Driven Floorplanning. Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, Piscataway, NJ, IEEE press, 2003. 1522~1530
29 P.Sniatala, R.Rudnicki, Automated design and layout generation for switched current circuits. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):4 pp.
30 Hua-An Zhao, Chen Liu, Y. Kajitani, K.Sakanushi, A compact code for representing floorplans. Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on Volume 1, 25-28 July 2004 Page(s):I - 433-6 vol.1
31 M.D.Moffitt, A.N.Ng, I.L.Markov, M.E.Pollack, Constraint-driven floorplan repair. Design Automation Conference, 2006 43rd ACM/IEEE24-28 July 2006 Page(s):1103– 1108
32 I.H.-R.Jiang, Yao-Wen Chang, Jing-Yang Jou, Chao Kai-Yuan.Simultaneous floor plan and buffer-block optimization. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions onVolume 23, Issue 5, May 2004 Page(s):694– 703
33 E.F.Y.Young, C.C.N.Chu, M.L.Ho,Placement constraints in floorplan design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 12,Issue 7, July 2004 Page(s):735– 745
34 Caldwell A, Kahng A.B. and Mantik S etc. Implications of Area-Array I/O for Row-Based Placement Methodology. Proceedings of the IEEE Symposium on IC/Package Design Integration, 1998. Piscataway, NJ, IEEE press, 1998: 93~98
35 Yasar G, Chiu C and Proctor R A etc. I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. Proceedings of the 2nd International Symposium on Quality Electronic Design, 2001. Piscataway, NJ, IEEE press, 2001: 71~75
36 Yasar G, Chiu C and Proctor R A etc. I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. Proceedings of the 2nd International Symposium on Quality Electronic Design, 2001. Piscataway, NJ, IEEE press, 2001: 71~75
37 I-Min Liu, Hung-Ming Chen and Tan-Li Chou etc. Integrated power supply planning and floorplanning. Proceedings of the 2001 conference on Asia South Pacific design automation, Yokohama, Japan, 2001. New York, NY, USA, ACM Press, 2001: 589~594
38 J.P.Fang, Y.-S.Tong, S.J.Chen, Simultaneous routing and buffering in SOC floorplan design. Computers and Digital Techniques, IEE Proceedings-Volume 151, Issue 1, 15 Jan. 2004 Page(s):17– 22
39 Zhaowei Teng, Peng Liu, Liya Lai,Physical design of dual-core system-on-chip. VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on 28-30 May 2005 Page(s):36– 39
40 MalyW , Ouyang C, Ghosh S, Maturi S. Detection of an Antenna Effect in VLSI Designs. IEEE.Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Boston, MA, USA ,1996. Piscataway, NJ,IEEE press, 1996:86~94