GaAs通孔刻蚀微掩模形成机理研究
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摘要
通孔刻蚀是GaAs制造工艺的重要环节,通过通孔刻蚀工艺实现GaAs背面和正面金属导通互连。在通孔刻蚀工艺中,微掩模的形成对器件性能及可靠性产生不利影响。微掩模将阻碍GaAs刻蚀,形成柱状堵孔以及侧壁聚合物等,造成后续背面金属接触不良、粘附不牢,进而影响通孔接触电阻、电感等关键参数,最终影响器件性能及可靠性。分析了GaAs微掩模形成的主要原因和形成机理,通过工艺优化解决了通孔刻蚀堵孔及侧壁聚合物等问题,从而提高了器件性能及可靠性。
The via etching play a very important role in GaAs manufacture. The backside metal connect frontal metal through GaAs via. In via etching process, the formation of micro mask impact device parameter and reliability harmfully, which block the GaAs etching and form abundant pillars in GaAs vias Polymer is accumulated on the surface of GaAs via simultaneously, which can cause backside metal connect badly and cling weakly. It will impact some key parameters such as via resistance and inductance, and will affect device performance and reliability ultimately. This paper analyzes the main cause and machaism of GaAs micro mask formation systematically. The pillar and polymer formation are eliminated through process optimization, which will improve device performance and reliability ultimately.
The via etching play a very important role in GaAs manufacture. The backside metal connect frontal metal through GaAs via. In via etching process, the formation of micro mask impact device parameter and reliability harmfully, which block the GaAs etching and form abundant pillars in GaAs vias Polymer is accumulated on the surface of GaAs via simultaneously, which can cause backside metal connect badly and cling weakly. It will impact some key parameters such as via resistance and inductance, and will affect device performance and reliability ultimately. This paper analyzes the main cause and machaism of GaAs micro mask formation systematically. The pillar and polymer formation are eliminated through process optimization, which will improve device performance and reliability ultimately.
引文
[1] NAM P S, FERREIRA L M, LEE T Y, TU K N. Study of grass formation in GaAs backside via etching using inductively coupled plasma system[J]. Journal of Vacuum Science&Technology B:Microelectronics and Nanometer Structures, 2000, 18(6):2780-2784.
[2] CLAYTON F, WESTERMAN R, JOHNSON D.Characterization of a manufacturable high rate GaAs via etch process[G]. 2012 GaAs MANTECH Technical Digest.121-124.
[3] WESTERMAN R, JOHNSON D, CLAYTON F. Eliminating pillars during GaAs via etch formation[G]. 2003 GaAs MANTECH Technical Digest. 135-199.
[4] HENDRIKS Henry, CRITES Jim, D’URSO Gerald, et al.Challenge in rapidly scaling up backside processing of GaAs wafers[C]. GaAs Mantech Conference, 2001.
[2] CLAYTON F, WESTERMAN R, JOHNSON D.Characterization of a manufacturable high rate GaAs via etch process[G]. 2012 GaAs MANTECH Technical Digest.121-124.
[3] WESTERMAN R, JOHNSON D, CLAYTON F. Eliminating pillars during GaAs via etch formation[G]. 2003 GaAs MANTECH Technical Digest. 135-199.
[4] HENDRIKS Henry, CRITES Jim, D’URSO Gerald, et al.Challenge in rapidly scaling up backside processing of GaAs wafers[C]. GaAs Mantech Conference, 2001.