一种改进的整机系统实时功率建模方法
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摘要
本文通过考察处理器、内存和磁盘三个部件的活动信息,包括硬件性能事件和部件利用率,构建整机系统实时功率模型.对于处理器和内存的功耗,通过特征选择找到合适的处理器内部的性能事件,结合CPU功耗状态C-States,建立低误差的功耗模型;对于没有提供性能事件的磁盘,通过利用率对部件功耗进行估算.采用回归方法分别建立并综合两个模型即可得到整机的实时功率模型.实验使用了真实系统Eureqa建模和PosgreSQL系统运行TPC-H负载对两种功率模型进行验证,结果表明:基于硬件性能事件与C-States的实时处理器与内存功率模型的误差在3%以下;结合性能事件、C-States与利用率的整机功率模型其相对误差在4%～10%之间,优于仅使用利用率的整机功率模型,最大时提升可达7%.
This paper aims to constructs full-system power models which are independent of the running workloads. Our models exploit the activity information of the main components( CPU,disk,and memory),including performance events and device utilization. When modeling power consumption for processor and memory,by combining performance events with the processor's C-States,we obtained a power model with small error. To model disk's power consumption,we estimated its power by its utilization since there are no diskrelated performance events for use till now. These two models are constructed with the regression method and are combined to get the power model of the whole machine. We compared our models with those previously proposed by using workloads from Eureqa and TPC-H benchmark queries in PosgreSQL. Experimental results showed that the average relative errors of our power model for processor and memory is less than 3%,and similarly that average relative errors of our power models for full-system are between 4% and10%,which sometimes reach as high as 7% better than models that only exploits device utilization.
This paper aims to constructs full-system power models which are independent of the running workloads. Our models exploit the activity information of the main components( CPU,disk,and memory),including performance events and device utilization. When modeling power consumption for processor and memory,by combining performance events with the processor's C-States,we obtained a power model with small error. To model disk's power consumption,we estimated its power by its utilization since there are no diskrelated performance events for use till now. These two models are constructed with the regression method and are combined to get the power model of the whole machine. We compared our models with those previously proposed by using workloads from Eureqa and TPC-H benchmark queries in PosgreSQL. Experimental results showed that the average relative errors of our power model for processor and memory is less than 3%,and similarly that average relative errors of our power models for full-system are between 4% and10%,which sometimes reach as high as 7% better than models that only exploits device utilization.
引文
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[2]张忆文,王成,郭锐锋.资源受限周期任务低能耗调度算法[J].小型微型计算机系统,2017,38(5):1076-1080.
[11]刘辛,沈立,苏博,等.多核处理器的功耗估算模型[J].软件学报,2015,26(7):1840-1852.
1 64-ia-32-architectures-optimization-manual[EB/OL].http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architecturesoptimization-manual.html.2017 Nov.
[2]Zhang Yi-wen,Wang Cheng,Guo Rui-feng.Resource constrained periodic task low power scheduling algorithm[J].Journal of Chinese Computer Systems,2017,38(5):1076-1080.
[3]Liu Y,Cox G,Deng Q,et al.FastCap:an efficient and fair algorithm for power capping in many-core systems[C]//IEEE Int'l Symposium on Performance Analysis of Systems and Software,2016:57-68.
[4]Raghavendra R,Ranganathan P,Talwar V,et al.No power struggles:coordinated multi-level power management for the datacenter[J].ACM SIGOPS Operating Systems Review,2008,42(1):48-59.
[5]Meisner D,Wenisch T F.Peak power modeling for data center servers with switched-mode power supplies[C]//Int'l Symposium on Low-Power Electronics and Design,2010:319-324.
[6]Korkmaz M,Karsten M,Salem K,et al.Workload-aware CPU performance scaling for transactional database systems[C]//Proceedings of SIGMOD Conference,2018:291-306.
[7]Bellosa F.The benefits of event-driven energy accounting in powersensitive systems[C]//Proceedings of ACM SIGOPS European Workshop,2000:37-42.
[8]Isci C,Martonosi M.Runtime power monitoring in high-end processors:methodology and empirical data[C]//Int'l Symposium on Microarchitecture,2006:121-132.
[9]Bertran R,Gonzalez M,Martorell X,et al.Decomposable and responsive power models for multicore processors using performance counters[C]//Proceedings of the ACM Int'l Conference on Supercomputing,2010:147-158.
[10]Rance R,Arunachalam A,Israel K,et al.A study on the use of performance counters to estimate power in microprocessors[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2013,60(12):882-886.
[11]Liu Xin,Shen Li,Su Bo,et al.Power estimation model on multicore platforms[J].Journal of Software,2015,26(7):1840-1852.
[12]Bertran R,Gonzalez M,Martorell X,et al.Counter-based power modeling methods:top-down vs.bottom-up[J].The Computer Journal,2013,56(2):198-213.
[13]Zhu H,Liao X,De Laat C,et al.Evaluation of non-linear power estimation models in a computing cluster[J].Sustainable Computing:Informatics and Systems,2016,11:26-37.doi:10.1016/j.suscom.2016.02.002.
[14]Powell M D,Biswas A,Emer J S,et al.CAMP:s technique to estimate per-structure power at run-time using a few simple parameters[C]//IEEE Int'l Symposium on High Performance Computer Architecture,2009:289-300.
[15]Weaver V M.Linux perf-event features and overhead[C]//The Int'l Workshop on Performance Analysis of Workload Optimized Systems,2013:1-13.
[16]David H,Gorbatov E,Hanebutte U R,et al.RAPL:memory power estimation and capping[C]//Int'l Symposium on Low-Power Electronics and Design,2010:189-194.
[17]Henning J L.SPEC CPU2006 benchmark descriptions[J].ACMSIGARCH Computer Architecture News,2006,34(4):1-17.
[2]张忆文,王成,郭锐锋.资源受限周期任务低能耗调度算法[J].小型微型计算机系统,2017,38(5):1076-1080.
[11]刘辛,沈立,苏博,等.多核处理器的功耗估算模型[J].软件学报,2015,26(7):1840-1852.
1 64-ia-32-architectures-optimization-manual[EB/OL].http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architecturesoptimization-manual.html.2017 Nov.