基于优化混频器的数字下变频系统的设计与实现
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摘要
在利用频谱分析仪对信号进行实时频谱监测过程中,针对其数字下变频模块精度不高、逻辑资源耗费大、难以对数字中频信号进行实时处理的问题,本文对传统数字下变频系统的混频器模块进行优化并提出一种高效的数字下变频(DDC)系统。首先,设置模数转换器(ADC)的采样率为载波中心频率的4倍且采样率转换比率和子ADC的数量是4的正整数倍,此时混频器可以完全合并到多相CIC抽取滤波器中。接着,基于优化的混频器构建一套DDC系统,并为每个系统节点合理分配采样率转换倍数。最后,加入CIC补偿滤波器,提高数据传输过程中的精度。实验结果表明,与传统DDC相比,优化后的DDC资源消耗减少,数据精度误差从1.7%减小到0.8%。基本满足功耗低、精度高、稳定运行等要求。
Aiming at the shortcomings of digital down-conversion(DDC)module such as low precision,expensive logic resources and difficult to process the digital intermediate frequency(IF)signals in real-time when using spectrum analyzer to monitor spectrum,this paper optimizes the mixer module of the traditional digital down conversion system and proposes an efficient one.Firstly,the sampling rate of the analog-to-digital converter(ADC)is set to 4 times the carrier center frequency,while the sampling conversion ratio and the number of sub-ADCs is set to a positive integer multiple of 4,now the mixer can be completely merged into the multiphase Cascaded Integrator Comb(CIC)decimation filter.Then,a set of DDC system is constructed based on the optimized mixer,where each node is reasonably allocated to the system down sampling rate.Finally,CIC compensation filters are added so as to improve the accuracy of data transmission.Experimental results show that compared with the traditional DDC,resource consumption is reduced and the data accuracy error is reduced from 1.7%to 0.8%in optimized DDC.It can satisfy the requirements of small power consumption,high accuracy and stable operation.
Aiming at the shortcomings of digital down-conversion(DDC)module such as low precision,expensive logic resources and difficult to process the digital intermediate frequency(IF)signals in real-time when using spectrum analyzer to monitor spectrum,this paper optimizes the mixer module of the traditional digital down conversion system and proposes an efficient one.Firstly,the sampling rate of the analog-to-digital converter(ADC)is set to 4 times the carrier center frequency,while the sampling conversion ratio and the number of sub-ADCs is set to a positive integer multiple of 4,now the mixer can be completely merged into the multiphase Cascaded Integrator Comb(CIC)decimation filter.Then,a set of DDC system is constructed based on the optimized mixer,where each node is reasonably allocated to the system down sampling rate.Finally,CIC compensation filters are added so as to improve the accuracy of data transmission.Experimental results show that compared with the traditional DDC,resource consumption is reduced and the data accuracy error is reduced from 1.7%to 0.8%in optimized DDC.It can satisfy the requirements of small power consumption,high accuracy and stable operation.
引文
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[2]王易因,VAN LEUKEN R,VAN DER VEEN A J,等.基于FPGA的跳时延发射参考系统的基带数字信号处理[J].光学精密工程,2006,14(5):876-882.WANG Y Y,VAN LEUKEN R,VAN DER VEEN A J,et al.DSP implementation for delay hopped transmitted reference system based on FPGA[J].Optics and Precision Engineering,2006,14(5):876-882.(in Chinese)
[3]石明江,张禾,河道清.基于FPGA的手持式数字存储示波器显示驱动设计[J].液晶与显示,2010,25(5):738-742.SHI M J,ZHANG H,He D Q.Design of display driver for oscillogragh based on FPGA[J].Chinese Journal of Liquid Crystals and Displays,2010,25(5):738-742.(in Chinese)
[4]邓晓平,田茂,罗义军,等.通用多通道数字下变频器的优化与实现[J].仪器仪表学报,2011,32(9):1993-1997.DENG X P,TIAN M,LUO Y J,et al.Optimization and implementation of universal multi-channel digital downconverter[J].Chinese Journal of Scientific Instrument,2011,32(9):1993-1997.(in Chinese)
[5]LIU X,YAN X X,WANG Z K,et al.Design and FPGA implementation of a reconfigurable digital down converter for wideband applications[J].IEEE Transactions on very Large Scale Integration(VLSI)Systems,2017,25(12):3548-3552.
[6]RFEL.Wideband DDC[EB/OL].[2014].http://www.rfel.com/index.php/signal-processing/ip-cores/channelisers-ddc/wideband-ddc/#tab-5-wideband-ddc.
[7]MARTENS E,BOURDOUX A,COUVREUR A,et al.RF-to-baseband digitization in 40nm CMOS With RFbandpassΔΣmodulator and polyphase decimation Filter[J].IEEE Journal of Solid-State Circuits,2012,47(4):990-1002.
[8]FARROW C W.A continuously variable digital delay element[C]//Proceedings of 1988 IEEE International Symposium on Circuits and Systems.Espoo,Finland:IEEE,1988:2641-2645.
[9]TIETCHE B H,ROMAIN O,DENBY B.A practical FPGA-based architecture for arbitrary-ratio sample rate conversion[J].Journal of Signal Processing Systems,2015,78(2):147-154.
[10]HOGENAUER E.An economical class of digital filters for decimation and interpolation[J].IEEE Transactions on Acoustics,Speech,and Signal Processing,1981,29(2):155-162.
[11]KIM G,CAPOCCIA R,LEBLEBICI Y.Design optimization of polyphase digital down converters for extremely high frequency wireless communications[C]//Proceedings of 2015 IFIP/IEEE International Conference on Very Large Scale Integration.Daejeon,South Korea:IEEE,2015:207-212.
[12]南航,张鹏,佟首峰,等.空间光混频器分光性能的分析与优化[J].光学精密工程,2017,25(7):1748-1756.NAN H,ZHANG P,TONG S F,et al.Analysis and optimization of splitting performance for space optical hybrid[J].Optics and Precision Engineering,2017,25(7):1748-1756.(in Chinese)
[13]闵淑琴,马宏.CIC滤波器及其补偿设计滤波器的设计与实现[C]//中国通信学会第六届学术年会论文集(下).广州:中国通信学会,广东省通信管理局,2009.MIN S Q,MA H.Design and implementation of CIC filter and its compensation design filter[C]//China Communications Society Academic Annual Conference.Guangzhou:China Communications Society,Guangdong Communications Administration,2009.(in Chinese)