4GS/s-12bit ADC内置数字下变频器(DDC)的ASIC实现
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摘要
本文提出了一种适合ASIC实现的可编程的数字下变频器(DDC)设计方法,该DDC嵌入于4GS/s-12bit ADC中,能够处理频率为4GHz的输入信号,并提供抽取因子分别为4、8、16、32的降采样功能.设计的DDC由一个基于CORDIC算法实现的数控振荡器(NCO)和一个全半带滤波器(HB-FIR)级联结构的抽取滤波器组组成.优化半带滤波器系数和各级数据精度,提出多种改进结构优化设计,有效减少硬件开销.基于40nm CMOS工艺,完成数字下变频器的前端设计和后端实现,并进行了流片.仿真结果显示,该设计可以在500 MHz的工作时钟频率下达到设计目标,抽取因子为4模式下,最大无衰减通带带宽可达420MHz,版图面积1550*650μm2,0.9V工作电压,功耗为180.69mW.验证了该设计方法适合于高速高精度数字信号的2n下变频.
This paper proposes a programmable digital downconverter(DDC) design method for ASIC implementation.The DDC is embedded in a 4GS/s-12 bit ADC and is capable of processing input signals at a frequency of 4GHz and provides extraction factors of 4Downsampling function for 8,16,16 and 32.The designed DDC consists of a numerically controlled oscillator based on the CORDIC algorithm and a decimation filter bank implemented by a full HB-FIR filter.According to the HB-FIR filter coefficient characteristics and spectral response characteristics,a variety of improved structural optimization designs are proposed in hardware implementation,reducing the area by about 50%.Based on the 40 nm CMOS process,digital front-end and back-end implementations of the digital downconverter were completed and taped out.The simulation results show that the design can achieve the design goals at a working clock frequency of 500 MHz.The layout area is 1550*650um^2,and the operating voltage is 0.9V.The power consumption is 180.69 mW.It is verified that the design method is suitable for 2^n down conversion of high-speed and high-precision digital signals.
This paper proposes a programmable digital downconverter(DDC) design method for ASIC implementation.The DDC is embedded in a 4GS/s-12 bit ADC and is capable of processing input signals at a frequency of 4GHz and provides extraction factors of 4Downsampling function for 8,16,16 and 32.The designed DDC consists of a numerically controlled oscillator based on the CORDIC algorithm and a decimation filter bank implemented by a full HB-FIR filter.According to the HB-FIR filter coefficient characteristics and spectral response characteristics,a variety of improved structural optimization designs are proposed in hardware implementation,reducing the area by about 50%.Based on the 40 nm CMOS process,digital front-end and back-end implementations of the digital downconverter were completed and taped out.The simulation results show that the design can achieve the design goals at a working clock frequency of 500 MHz.The layout area is 1550*650um^2,and the operating voltage is 0.9V.The power consumption is 180.69 mW.It is verified that the design method is suitable for 2^n down conversion of high-speed and high-precision digital signals.
引文
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[2]李飞.数字控制振荡器(NCO)的FPGA实现[J].电子元器件应用,2010,11(11):42-44
[3] Zhao Kongrui,Zhang Chao.A polyphase digital down converter method for GHz high speed sampling signal[C]//2015IEEE 12th International Conference on Electronic Measurement&Instruments.Honolulu,Hawaii,USA,2015:907-910
[4] Sudhir Rao Rupanagudi,Chandrika B V.Design of a low power digital down converter for 802.16m-4G WIMAX on FPGA[C]//International Conference on Advances in Computing, Kollam, Kerala,India,IEEE,2014:2303-2308
[5] Rashmi M Mani,Abdul Imran Rasheed.Design and implementation of WDF for digital down converter on FPGA for LTE application[C]//2014International Conference on Advances in Electronics,Computers and Communications(ICAECC).[S.l].2014
[6] Hanyu Wang,Jinxiang Wang,Fangfa Fu.An efficient low-cost fixed-point digital down converter with modified filter bank[C]//2013IEEE 10th International Conference on ASIC(ASICON 2013).Shenzhen,China,2013.
[7] Zhuo Zhihai,Li Shange,Zhang Zechao.Implementation of high-performance multi-structure digital down converter based on FPGA[C]//ICSP2012 Proceedings.Beijing,China,2012:31-35.