面向硬件的帧内预测模式选择快速算法与实现
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摘要
新一代视频编码标准HEVC硬件实现的复杂性较之以前的标准有大幅提高.在保证编码性能的前提下,为了降低硬件实现的复杂度和资源消耗,提高硬件的处理速度与并行度,提出一种面向硬件实现的HEVC帧内编码快速算法.首先在Hadamard-SATD基础上引入头比特估计,简化了率失真代价计算过程;然后使用同层相邻块的最佳模式作为最有可能模式列表的输入,解除计算预测值时对重构数据的依赖性,提高了硬件的处理速度;最后采用新的预测单元处理顺序和基于16点的硬件复用结构,使之更利于硬件实现的情况下减少硬件资源的使用.实验结果表明,与参考软件HM16.7相比,文中算法可以降低约40%的编码复杂度,且没有明显性能损失;在Xilinx的Virtex6综合结果表明,硬件面积比已有算法减少了45%左右,并且可以达到30帧/s 1 080p视频序列的实时编码要求.
The complexity of hardware implementation of the new generation video coding standard HEVC has been greatly improved compared with the previous standards. Under the premise of ensuring coding performance, in order to reduce the complexity and resource consumption of hardware implementation and improve the processing speed and parallelism of hardware, a hardware-oriented HEVC intra-frame coding fast algorithm is proposed. The head bit estimation is introduced based on Hadamard-SATD, which simplifies the calculation process of rate distortion cost. The best mode of the same layer neighboring block is used as the input of the MPM, and the dependence on the reconstructed data is removed when the predicted value is calculated, and hence the processing speed of hardware increases; The utilization of new Prediction Unit processing sequence and 16-point based hardware multiplexing structure makes it more effective to reduce the usages of hardware resources. The proposed algorithm can reduce the coding complexity by about 40% without obvious performance loss compared with HM16.7. Simulations conducted in Xilinx Virtex 6 show that the proposed algorithm is able to achieve real-time encoding requirements of 30 fps 1080 p and the required hardware area can be reduced by about 45% compared with the existing literature.
The complexity of hardware implementation of the new generation video coding standard HEVC has been greatly improved compared with the previous standards. Under the premise of ensuring coding performance, in order to reduce the complexity and resource consumption of hardware implementation and improve the processing speed and parallelism of hardware, a hardware-oriented HEVC intra-frame coding fast algorithm is proposed. The head bit estimation is introduced based on Hadamard-SATD, which simplifies the calculation process of rate distortion cost. The best mode of the same layer neighboring block is used as the input of the MPM, and the dependence on the reconstructed data is removed when the predicted value is calculated, and hence the processing speed of hardware increases; The utilization of new Prediction Unit processing sequence and 16-point based hardware multiplexing structure makes it more effective to reduce the usages of hardware resources. The proposed algorithm can reduce the coding complexity by about 40% without obvious performance loss compared with HM16.7. Simulations conducted in Xilinx Virtex 6 show that the proposed algorithm is able to achieve real-time encoding requirements of 30 fps 1080 p and the required hardware area can be reduced by about 45% compared with the existing literature.
引文
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[3]Jiang W,Ma H J,Chen Y W.Gradient based fast mode decision algorithm for intra prediction in HEVC[C]//Proceedings of the2nd International Conference on Consumer Electronics,Communications and Networks.Los Alamitos:IEEE Computer Society Press,2012:1836-1840
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[7]Abramowski A,Pastuszak G.A novel intra prediction architecture for the hardware HEVC encoder[C]//Proceedings of Euromicro Conference on Digital System Design.Los Alamitos:IEEE Computer Society Press,2013:429-436
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[9]Liu Z Y,Wang D S,Zhu H X,et al.41.7BN-pixels/s reconfigurable intra prediction architecture for HEVC 2560×1600encoder[C]//Proceedings of the IEEE International Conference on Acoustics Speech,and Signal Processing.Los Alamitos:IEEE Computer Society Press,2013:2634-2638
[10]Amish F,Bourennane E B.Fully pipelined real time hardware solution for high efficiency video coding(HEVC)intra prediction[J].Journal of Systems Architecture,2016,64:133-147
[11]Jiang Y B,Llamocca D,Pattichis M,et al.A unified and pipelined hardware architecture for implementing intra prediction in HEVC[C]//Proceedings of Southwest Symposium on Image Analysis and Interpretation.Los Alamitos:IEEE Computer Society Press,2014:29-32
[2]Reuze K,Philippe P,Deforges O,et al.Intra prediction modes signaling in HEVC[C]//Proceedings of Picture Coding Symposium.Los Alamitos:IEEE Computer Society Press,2016:1-5
[3]Jiang W,Ma H J,Chen Y W.Gradient based fast mode decision algorithm for intra prediction in HEVC[C]//Proceedings of the2nd International Conference on Consumer Electronics,Communications and Networks.Los Alamitos:IEEE Computer Society Press,2012:1836-1840
[4]Na S,Lee W,Yoo K.Edge-based fast mode decision algorithm for intra prediction in HEVC[C]//Proceedings of the IEEE International Conference on Consumer Electronics.Los Alamitos:IEEE Computer Society Press,2014:11-14
[5]Zhang H,Ma Z.Fast intra mode decision for high efficiency video coding(HEVC)[J].IEEE Transactions on Circuits and Systems for Video Technology,2014,24(4):660-668
[6]Li F,Shi G M.A pipelined architecture for 4×4 intra frame mode decision in the high efficiency video coding[C]//Proceedings of the 13th IEEE International Workshop on Multimedia Signal Processing.Los Alamitos:IEEE Computer Society Press,2011:1-5
[7]Abramowski A,Pastuszak G.A novel intra prediction architecture for the hardware HEVC encoder[C]//Proceedings of Euromicro Conference on Digital System Design.Los Alamitos:IEEE Computer Society Press,2013:429-436
[8]Kalali E,Adibelli Y,Hamzaoglu I,et al.A high performance and low energy intra prediction hardware for HEVC video decoding[C]//Proceedings of the Conference on Design and Architectures for Signal and Image Processing.Los Alamitos:IEEE Computer Society Press,2012:1-8
[9]Liu Z Y,Wang D S,Zhu H X,et al.41.7BN-pixels/s reconfigurable intra prediction architecture for HEVC 2560×1600encoder[C]//Proceedings of the IEEE International Conference on Acoustics Speech,and Signal Processing.Los Alamitos:IEEE Computer Society Press,2013:2634-2638
[10]Amish F,Bourennane E B.Fully pipelined real time hardware solution for high efficiency video coding(HEVC)intra prediction[J].Journal of Systems Architecture,2016,64:133-147
[11]Jiang Y B,Llamocca D,Pattichis M,et al.A unified and pipelined hardware architecture for implementing intra prediction in HEVC[C]//Proceedings of Southwest Symposium on Image Analysis and Interpretation.Los Alamitos:IEEE Computer Society Press,2014:29-32